Pentacene-based Thin-film Transistors Research Articles

Stability of pentacene-based top gate thin film transistor with thick parylene as dielectric under humid environment

This study presents the influence of humidity effect in top gate transistors using pentacene as active layer. The devices are made on a planarized kapton substrate, and 1 μm thick parylene has been used both as gate dielectric and encapsulating layer. Two series of measurement conditions have been used. First, the humidity rate was varied from 0 to 90% in a cell by setting exposure times of 15 min and device characterized, followed to 15 min vacuum. Secondly, humidity rate is fixed at 90% during 144 min and the electrical characteristics recorded successively. The main electrical parameters such as threshold voltage (VT), mobility (μ), on-current (Ion), depletion current (Ioff) and subthreshold slope (S) have been investigated. The results showed that only the electrical parameters in subthreshold region have been affected at different relative humidity (RH) levels for the first series. Under vacuum, the device exhibited stable electrical performances whereas in RH ranging from 24% to 90% we observe an increase of depletion current, and this Ioff increase was found to be reversible. After exposing the device with 90% of RH (second series), from 0 to 108 min in humid environment, threshold voltage, Ion current, VT and charge carrier mobility remain unchanged while Ioff and S are highly affected. Beyond 108 min, Ioff current keeps increasing with a noticeable Ion current degradation. Two effects have to be taken into account: (i) Ioff current increase without any change in on-state regime is the consequence of cumulative effect of Leakage current increase in the parylene dielectric and electrical conductivity increase in pentacene semiconductor, (ii) Ion current decrease is the consequence of absorbed water molecule diffusing and interacting with pentacene. All these parameters are reversible under vacuum after pumping down.

Highly conductive, transparent and metal-free electrodes with a PEDOT:PSS/SWNT bilayer for high-performance organic thin film transistors

Abstract Conductive organic materials including polymers, small molecules, and carbon nanotubes (CNTs) are a promising alternative to inorganic materials in electronic devices. Conventionally, organic electrodes employing CNTs are designed using functionalization of their surfaces or formation of nanocomposites with a conductive polymer. However, phase separation limits the concentration of CNTs in a polymer matrix, hindering the formation of highly dense CNT networks and leading to poor electrical conductivity. In this paper, we introduce bilayer electrodes comprising poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) and single-walled CNTs (SWNTs) chemically modified by HNO3 treatment. Impressive conductivities of 2432 and 2438 S cm−1 are found for the SWNT/PEDOT:PSS (S/P) and PEDOT:PSS/SWNT (P/S) electrodes, respectively. Further, an increase in the work function of the electrodes after HNO3 treatment lowers the hole injection barrier, which facilitates hole injection from pentacene. The smooth surface of PEDOT:PSS also contributes to growth of large pentacene grains; consequently, the field-effect mobility of pentacene-based thin film transistors is 1.88 cm2 V−1 s−1 when the P/S electrode is employed. The metal-free electrodes also exhibit a high optical transparency of 88.7%, which suggests that they have great potential for applications in optoelectronics.

Performance of Pentacene-based Thin-film Transistors Fabricated at Different Deposition Rates

Performance of Pentacene-based Thin-film Transistors Fabricated at Different Deposition Rates

Pentacene bottom-contact thin film transistors with solution-processed BZT gate dielectrics

The solution-processed high-k barium zirconate titanate (BZT) as gate dielectrics for bottom-gate pentacene-based organic thin film transistor (OTFT) applications is presented. To reduce the transistor threshold voltage, higher work function metals (Au) is used as the gate electrodes. The threshold voltage is efficiently decreased from −3.6 to −2.15 V as compared to that of Al. In addition, the UV/ozone was employed to treat the Au (source/drain) surface to improve the poor crystalline of pentacene grown on Au. Moreover, the surface morphologies and orientations of pentacene films were analyzed through atomic force microscopy (AFM) and X-ray diffraction. As the results, the stack of pentacene molecules from disorder state changed to vertical growth on the Au surface. Finally, the electrical properties of pentacene-based thin film transistors exhibit high field-effect mobility of 4.5 cm2/V·s, low subthreshold swing of 260 mV/decade, high on/off ratio of 1.4 × 105 and low operation voltage of −5 V. These results are better than the reported data using bottom contact pentacene OTFTs.

The effect of indirect UV/ozone treatment on pentacene thin film transistors with double-stacked organic gate insulators

Abstract We investigated the indirect UV/ozone treatment, which means treating the insulator surface under tens of nanometers, rather than the direct surface of the insulator. The double-stacked organic layers are used as gate insulator and the UV/ozone treatment is conducted between these two layers. We analyzed the surface morphologies of the gate insulator and the pentacene by atomic force microscopy (AFM) to confirm the effect of indirect UV/ozone treatment. The UV/ozone treatment reduced the surface roughness of the upper side gate insulator and increased the pentacene grain size. Pentacene-based thin film transistors were fabricated and the electrical property improvement after this treatment was examined. The largest improvement was found when the UV/ozone treatment time is 10 min and the upper side gate insulator thickness is 20 nm, and the mobility at that condition is 1.21 cm2/V s, which is larger than three times that without UV/ozone treatment (0.33 cm2/V s).

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors.

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W).

A compact model of organic thin-film transistors for display device

Organic transistor has been widely studied for next generation flexible semiconductor process. In this paper, we proposed the organic thin-film transistors (OTFT) model for the display device at the moderately high temperature (above 273K). The model based on hopping theory of Gaussian disordered density-of-states (DOS) considers the dependences relationship of the carrier mobility with temperature and carrier concentrations. Charge transport is controlled by carrier jumps from trap states around the Fermi level to tail trap states at large carrier concentrations. The sub-threshold model is modified using an exponential function to make the model cover all regimes of OTFT operation. A pentacene-based thin film transistor (TFT) model has been designed using Verilog-A language. The model has been verified by device simulations and measurements.

Impact of gold deposition parameters on the drain-source leakage current in top-contact pentacene-based thin-film transistors

In this work the influence of gold deposition parameters such as substrate temperature and nominal contact thickness on the drain-source leakage current in top-contact pentacene-based thin-film transistors (TFTs) is investigated. The results reveal that the drain-source leakage current can be suppressed by increasing the substrate temperature and by decreasing the gold contact thickness. It is shown that the observed behavior cannot be fully explained by the standard leakage current model, which attributes the decrease of the leakage current to an increase of the contact resistance. Therefore an extended leakage current model is introduced which takes into account the so-called halo-effect, i.e. the formation of a layer of gold clusters during the gold diffusion process, yielding a parallel resistance between drain and source. It is shown that this model is able to describe both, the dependency of the leakage current on the substrate temperature as well as on the contact thickness.

Enhancement of Field-Effect Mobility By Controlling the Surface Potential of PVP Insulator in Pentacene-Based Thin Film Transistors

In recent years, the surface potential at insulator/semiconductor interface has received considerable attention for improving the electrical performance of various electronic and optoelectronic device. Many studies of the effect of a surface potential at insulator/semiconductor interface have been carried out. Most of these studies have focused on achieving efficient hole or electron injection at the inorganic insulator (i.e., such as SiO2)/ semiconductor interface. But the surface potential effects at the polymer insulator/semiconductor interface of organic thin-film transistors have not been sufficiently studied. In this presentation, we focus in particular on the effects of varying the surface potential on the polymer insulator/semiconductor interface. We demonstrated a method of reducing the surface energy in a polymer insulator for use in high-performance OTFTs. The surface energy of a poly(4-vinyl phenol) insulator was reduced from 45 mJ/m2 to 32 mJ/m2 through treatment with UV/ozone and ODTS. These treatments facilitated the deposition of the pentacene film onto the ODTS-treated poly(4-vinyl phenol) insulator to prepare a single phase that showed better π-orbital overlap among the pentacene molecules. As a result, the field-effect mobility in the insulator increased by 209 %. These results demonstrated that adjusting the surface energy of a polymer insulator provided a suitable approach to enhancing the performances of OTFTs. Acknowledgments This study was supported by the R&D program of the Korea Research Council for Industrial Science and Technology of Republic of Korea (Grant 2015K000217/ 10052802/ KM3710/ NK186C/ SC1130/ MO5970/ NM8270).

Understanding the dependence of the ohmic drain-source leakage current on gold deposition rate in top-contact pentacene-based thin film transistors

We studied the influence of the gold deposition rate on the drain-source leakage current of top-contact pentacene-based thin film transistors (TFTs) with different channel lengths. It is demonstrated that the anomalous leakage current which occurs only in short-channel TFTs monotonically increases with increasing the gold deposition rate. For TFTs with channel length of 30μm, we also investigated the dependence of the drain-source leakage current on the pentacene grain size as well as the gold deposition rate. It is shown that the pentacene grain size influences the leakage current only in the case if high gold deposition rate is employed, whereas the anomalous leakage current can be avoided by reducing the gold deposition rate. Finally, due to the observed ohmic character of the anomalous leakage current, we propose that the origin of the current can be attributed to parasitic leakage paths on the surface of the pentacene layers formed by the lateral diffusion of gold clusters from drain/source edges into the channel region during gold deposition. Based on this hypothesis, the observed dependence of the anomalous leakage current on the gold deposition rate can be well explained.

Inkjet-printed copper electrodes using photonic sintering and their application to organic thin-film transistors

We report on copper (Cu) electrodes fabricated with inkjet-printed nanoparticle inks that are photonic sintered on a polymer dielectric layer and their application to source and drain electrodes in organic thin-film transistor (TFT). By using photonic sintering with a radiant energy density of 9J/cm2, printed Cu nanoparticle layers on a glass substrate showed very low electrical resistivity levels of 7μΩcm. By optimizing the sintering conditions on polymer dielectric, the pentacene-based TFT using these printed Cu electrodes showed good mobility levels of 0.13cm2/Vs and high on/off current ratios of about 106. In addition, we revealed that the crystal grain growth of pentacene near the printed Cu electrodes was inhibited by the thermal damage of polymer underlayer due to the high radiant energy density of the intense light.

Temperature-dependent ambipolar electrical characteristics of pentacene-based thin-film transistors: The impact of opposite-sign charge carriers

The temperature-dependent electrical and charge transport characteristics of pentacene-based ambipolar thin-film transistors (TFTs) were investigated at temperatures ranging from 77K to 300K. At room temperature (RT), the pentacene-based TFTs exhibit balanced and high charge mobility with electron (μe) and hole (μh) mobilities, both at about 1.6cm2/Vs. However, at lower temperatures, higher switch-on voltage of n-channel operations, almost absent n-channel characteristics, and strong temperature dependence of μe indicated that electrons were more difficult to release from opposite-signed carriers than that of holes. We observed that μe and μh both followed an Arrhenius-type temperature dependence and exhibited two regimes with a transition temperature at approximately 210–230K. At high temperatures, data were explained by a model in which charge transport was limited by a dual-carrier release and recombination process, which is an electric field-assisted thermal-activated procedure. At T<210K, the observed activation energy is in agreement with unipolar pentacene-based TFTs, suggesting a common multiple trapping and release process-dominated mechanism. Different temperature-induced characteristics between n- and p-channel operations are outlined, thereby providing important insights into the complexity of observing efficient electron transport in comparison with the hole of ambipolar TFTs.

Correlation between ambient air and continuous bending stress for the electrical reliability of flexible pentacene-based thin-film transistors

This study investigated how continuous bending stress affects the electrical characteristics of pentacene-based organic thin-film transistors (OTFTs) with poly(4-vinylphenol) (PVP) gate insulator in a vacuum and in ambient air. In tension mode, the strain direction of the fabricated devices was perpendicular to the device channel length. The OTFT devices that were bent in a vacuum exhibited a decreased on current because of cracking in the pentacene channel layer, which can obstruct the transport of charge carriers and deteriorate the on current of the OTFTs. The OTFT devices that were bent in ambient air exhibited a slightly decreased on current and considerably increased off current and subthreshold swing (SS). It was assumed that air moisture passed through the pentacene cracks into the interface between the PVP and pentacene layer, thereby yielding an increase in polar moisture traps, and leading to an increase in the conductivity of the pentacene, thus yielding a slightly decreased on current and considerably increased off current and SS.

Remarkable reduction in the threshold voltage of pentacene-based thin film transistors with pentacene/CuPc sandwich configuration

This study investigates the remarkable reduction in the threshold voltage (VT) of pentacene-based thin film transistors with pentacene/copper phthalocyanine (CuPc) sandwich configuration. This reduction is accompanied by increased mobility and lowered sub-threshold slope (S). Sandwich devices coated with a 5 nm layer of CuPc layer are compared with conventional top-contact devices, and results indicate that VT decreased significantly from −20.4 V to −0.2 V, that mobility increased from 0.18 cm2/Vs to 0.51 cm2/Vs, and that S was reduced from 4.1 V/dec to 2.9 V/dec. However, the on/off current ratio remains at 105. This enhanced performance could be attributed to the reduction in charge trap density by the incorporated CuPc layer. Results suggest that this method is simple and effectively generates pentacene-based organic thin film transistors with high mobility and low VT.

Low Electrode Contact Resistance in Pentacene-Based Thin-Film Transistors by Inserting F4-TCNQ between Pentacene and Au

Low Electrode Contact Resistance in Pentacene-Based Thin-Film Transistors by Inserting F4-TCNQ between Pentacene and Au

High-Mobility Pentacene-Based Thin-Film Transistors With Synthesized Strontium Zirconate Nickelate Gate Insulators

Strontium zirconate nickelate [(SZN); Sr0.69Ni0.47Zr0.085O3.75] was synthesized through a sol-gel method by adding nickel (II) acetylacetone instead of titanium isopropoxide, which can effectively make thin films smoother and further act as gate insulators applied in pentacene-based thin-film transistors. Sol-gel SZN thin films were investigated by X-ray photoelectron spectroscopy and atomic force microscopy to confirm the chemical composition and smooth surface roughness, and the latter property was found to be compatible for pentacene thin film growth. Thus, the electrical characteristics of pentacene-based transistors exhibited a high mobility of 10.04 cm2 V-1s-1 low threshold voltage of -1.51 V,, and low subthreshold swing slope of 350 mV/decade. To realize high mobility mechanisms, intermolecular coupling and reorganization energy of pentacene thin films were introduced. Another purpose of this introduction was to evaluate the higher hopping rate of carriers between the adjacent pentacene molecules on SZN derived from the March-Hush equation than other high-κ traditional sol-gel insulators.

Influence of grain size at first monolayer on bias-stress effect in pentacene-based thin film transistors

Threshold voltage shift under applied gate voltage is a key factor characterizing stability of organic thin-film transistors (OTFTs), while the physical mechanism is still controversial. In this study, we systematically examined the initial growth of pentacene polycrystalline films under different growth rates. Bias stress performance of the fabricated pentacene-based OTFTs was found to be highly related to the initial gain size of the pentacene films. Larger grain size at the first deposition layer led to smaller threshold voltage shift. The quantitative correlation can be described by a two-dimensional microscopic mobility model relating to the grains and grain boundaries.

Hydrophilic self-assembly monolayers for pentacene-based thin-film transistors

A series of hydrophilic alkanethiols, HS(CH2)nOH with n=3, 4, 6, 8, 9 and 11, have been self-assembled on gold electrodes of pentacene-based thin-film transistors. The multi-parametric and ultra-sensitive response of these devices allows us to characterize both charge–injection and electrical stability moving from vacuum to air. The decay exponent β of charge injection is found to be 0.7–1.1Å−1 in agreement with earlier measurements of charge tunneling done by electrochemistry and large-area molecular junctions. We find that the intermediate chain lengths (n=4 and 6) yield an optimum response as they represent the best compromise in terms of decrease of the contact-resistance and bias stress.

Gate field induced ordered electric dipoles in a polymer dielectric for low-voltage operating organic thin-film transistors

The development of low voltage-operating organic thin-film transistors requires high-dielectric constant (high-K) materials for the device's gate dielectrics. The surface properties of these high-K materials must match those of organic semiconductors. A modification material coated on high-K dielectric is needed, and polyimide (PI) is a promising modifier to reduce the surface energy and the interface trap states (in the level of 1010 cm−2 eV−1) of the high-K dielectrics. In this study, surface characteristics of the dielectrics were identified and interface analyses at the dielectric/organic semiconductor interface were conducted through combined electrical force microscopy and impedance–admittance investigation. When the organic semiconductor pentacene was grown on the PI-modified dielectrics, the atomic force microscopy images and X-ray diffraction analyses showed larger grain size and higher crystallinity than those on native high-K dielectrics. Using polyimide-modified high-K materials as the gate dielectric, high performances (SS < 1 V per decade, μ above 0.1 cm2 V−1 s−1, and on/off ratio > 105) and low voltage-operating (<5 V) pentacene-based thin-film transistors were achieved. Although the gate field was decreased by inserting a PI layer, the effective gate field was compensated by an electric dipole-induced dipole field embedded in the PI layer. The mechanism of carrier accumulation at the PI/pentacene interface was also clearly described.

Electric Bistability Induced by Incorporating Self-Assembled Monolayers/aggregated Clusters of Azobenzene Derivatives in Pentacene-Based Thin-Film Transistors

Composite films of pentacene and a series of azobenzene derivatives are prepared and used as the active channel material in top-contact, bottom-gate field-effect transistors. The transistors exhibit high field-effect mobility as well as large I-V hysteresis as a function of the gate bias history. The azobenzene moieties, incorporated either in the form of self-assembled monolayer or discrete multilayer clusters at the dielectric surface, result in electric bistability of the pentacene-based transistor either by photoexcitation or gate biasing. The direction of threshold voltage shifts, size of hysteresis, response time, and retention characteristics all strongly depend on the substituent on the benzene ring. The results show that introducing a monolayer of azobenzene moieties results in formation of charge carrier traps responsible for slower switching between the bistable states and longer retention time. With clusters of azobenzene moieties as the trap sites, the switching is faster but the retention is shorter. Detailed film structure analyses and correlation with the transistor/memory properties of these devices are provided.