Peak PAE Research Articles

A 28-47.5 GHz broadband power amplifier using improved MCR technique in 40-nm CMOS

This paper presents a broadband power amplifier (PA) implemented in 40-nm CMOS process for low power application. The PA cascades two stages of common-source differential transistors and adopts symmetrical magnetically coupled resonators (MCRs) for impedance matching and single-ended differential conversion. Theoretical analysis elucidates the effect of the resonator Q on the frequency response of the transformer, thus giving the distribution of the poles and their precise locations, and revealing the quantitative relationship between bandwidth and gain ripple. A method for efficiently balancing gain ripple and bandwidth in k, Q space under low-power conditions when the intrinsic Q of the source impedance is high is described in detail. Measurement results demonstrate a 51.6% 3-dB bandwidth from 28 to 47.5 GHz. The PA achieve 10.7 dBm Psat, 8.5 dBm OP1db and 23% peak PAE at 31 GHz.

A 23–29.5 GHz three‐stage mm‐wave GaN power amplifier using arbitrary two‐port complex‐impedance matching method

SummaryThis paper presents a broadband monolithic millimeter‐wave integrated circuit GaN power amplifier (PA) with arbitrary two‐port complex‐impedance matching method. The proposed matching topology has been applied to interstage matching network design by modifying traditional coupling matrix and synthesizing a desired network. The optimum load traction technique is introduced to provide some more suitable Zopts. After continuous‐wave test, the three‐stage MMIC PA achieves a peak PAE of 39.1% with a 34.9 dBm output power from 23 to 29.5 GHz and the measured S21 is 32.5 dB with a ±2.5 dB gain variation. When driven by a 400 MHz OFDM modulation signal with a PAPR of 8.5 dB, the measured ACPR is improved to −40.6/−40.7 dBc with DPD. In this case, the PA achieves an average PAE of 11.7% and a 26.7 dBm average output power.

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

This paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design's robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network.

Stacked Common-Base vs Common-Emitter mmWave PA Cells and 68–105 GHz Broadband Asymmetrical PA in 250nm InP HBT

In this paper, we perform a comparative analysis between stacked common-emitter (SCE) and stacked common-base topologies (SCB) for high efficiency and broadband millimeter-Wave (mmWave) power amplifiers (PAs) in 250 nm InP-based heterojunction bipolar transistor (HBT) technology. We propose an analytical approach to design stacked PA cells accounting for complex load impedance and intra-matching between stacked transistors to allow optimal loadpull operation of both the devices in the stack. We demonstrate how SCB cell can allow higher gain, mitigated power and efficiency trade-off and linearity, when compared to more well-established SCE cells at higher mmWave frequencies. The designed SCB and SCE cells achieve a measured gain of 11.8 dB/6dB gain, 33%/34% peak PAE, 16.8%/14.5% PAE at 6-dB back-off, and Psat of 18.7 dBm/19.6 dBm at 90 GHz. The SCB PA demonstrates superior linearity, and achieves an EVM of 2.38% at 11.8-dBm average power supporting 3 Gbps 64-QAM. The SCB PA achieves 17.9-18.9-dBm Psat across 80–110 GHz and is one of the highest efficiency, broadband and linear PAs in W-band using InP technology. Utilizing the PA cells, we demonstrate an asymmetrical broadband power combining circuit for high efficiency combining across a large relatively bandwidth. The PA operates across a 68–105 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{sat,3dB}$ </tex-math></inline-formula> bandwidth with 21.5 dBm peak saturation power and 24% peak PAE.

A 62-GHz High-Efficiency Power Amplifier With Modulation Capability via Back-Gate in 22-nm FD-SOI

This letter presents a feasibility study for a 62 GHz power amplifier (PA) in a 22 nm CMOS technology with integrated data modulation via the back-gate. The proposed PA consists of two pseudo-differential cascode stages, and provides a peak gain of 23.3 dB, a Psat of 13.6 dBm and a peak PAE of 28.3%. The PA consumes 96 mW from a 2 V VDD at its saturation. Thanks to the transistor back-gate, the PA can be dynamically switched on and off by increasing the threshold voltage through the back-gate. This avoids AC ground, gain and stability problems caused by conventional front-gate switching. In off-mode it draws 2.5% of its peak DC power. Rise-and fall-times of 1 ns were measured. The possibility of back-gate based modulation was experimentally demonstrated, showing that the PA can be used as a single device transmitter. Compared to previously reported works the PA shows one of the highest PAE and excellent linearity. To the best knowledge of the authors, this is the first investigation of a 60 GHz PA with data modulation via the back-gate.

A Sub-GHz multimode digital polar transmitter for 802.11ah and NB-IoT applications

This paper presents a sub-GHz multimode efficiency-enhanced digital polar transmitter for IoT applications. The Class-G technique and wideband matching network are introduced in the switched-capacitor digital power amplifier (DPA) to enhance the 6 dB back-off efficiency and achieve 550–950 MHz wide frequency coverage. The digital baseband processing module is flexibly reconfigurable to support both 802.11ah and NB-IoT protocols. Moreover, the canonic signed digit (CSD) coding and first-order hold (FOH) interpolation techniques are employed to reduce power consumption. Implemented in 55 nm CMOS technology, this digital transmitter (DTX) achieves 23.7dBm peak power, 44.6% peak PAE and 36.1% PAE at 6 dB power back-off at 800 MHz. The DTX obtains 16.7dBm average output power, 33.9% average PAE with −28.8 dB EVM for the 2 MHz 64QAM 802.11ah signal, and 18.6dBm average output power, 37.5% average PAE with −19.8 dB EVM for the 12-subcarrier 180 kHz NB-IoT signal.

Low Consumption Balanced Front-End Amplifiers Robust to Load Variations in 65nm PD-SOI CMOS Technology for 60 GHz Short-Range Wireless Applications

This brief presents two low consumption balanced front-end amplifiers designed in 65nm PD-SOI CMOS technology dedicated to low output power 60 GHz short-range wireless applications. For both designs, a resistive feedback neutralized common source differential pair architecture is used with 90° twisted hybrid couplers which allows power combining in addition to an improved robustness against load variations shown by load-pull experimental results. A specific design approach is used to reduce power consumption and limit the output power level. The one-stage amplifier exhibits a gain of 5.43 dB, an OCP1dB of 4.5 dBm, a saturated power superior to 6.33 dBm and a peak PAE of 8.6 % for a total power consumption of solely 14 mW and an active area of 0.17 mm2. The three-stage amplifier exhibits a gain of 21 dB, an OCP1dB of 3.7 dBm, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathbf {P}}_{\mathbf {sat}}$ </tex-math></inline-formula> of 7 dBm and a peak PAE of 8.4 % under a total power consumption of only 42 mW and an active area of 0.3 mm2. All the reported performances are obtained at 60 GHz from a 1V supply voltage.

A Novel Approach for Doherty PA Design Using a Compact L-C Combiner

In this brief, a new combiner analysis method for the design of Doherty Power Amplifiers (DPA) is proposed. A compact L-C combiner is used to validate the proposed method through both simulation and realization of a two-stage DPA in a 130nm RF-SOI process. Using a 2.3GHz CW signal, the PA achieves a measured peak PAE of 51% at 32dBm output power under 3.4V supply voltage. From 2.1GHz to 2.5GHz, the PA shows an average output power and PAE higher than 26.9dBm and 39% respectively at −35dBc E-UTRA ACLR when using a 10MHz-50RB QPSK LTE uplink signal with memoryless DPD. At 2.3GHz, the PA achieves a linear Pout and PAE of 28.85dBm and 42.8% respectively.

Deep Learning-Enabled Inverse Design of 30–94 GHz Psat,3dB SiGe PA Supporting Concurrent Multiband Operation at Multi-Gb/s

Deep learning and artificial intelligence, in general, is advancing scientific discovery and technological inventions through its ability to extract inherently hidden features and map it to output in a highly complex multi-dimensional space. Synthesis of electromagnetic (EM) structures with nearly arbitrary with desired functional properties is such an example of a high dimensional optimization space. In this article, we employ deep convolutional neural network (CNN) to allow robust and rapid prediction of scattering properties of nearly arbitrary planar electromagnetic structures on chip. Utilizing this, the work reports an mm-wave PA in 90-nm SiGe with a novel deep learning-enabled inverse design of low-loss, broadband output matching network that achieves a PAE of 16%–24.7%, a saturation power of 16.7–19.5 dBm across P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat, 3 dB</sub> bandwidth of 30–94 GHz (103.2%), while supporting both single-carrier high-speed modulation and concurrent multiband multi-Gb/s non-constant amplitude modulation. The P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat, 3 dB</sub> bandwidth covers from 5G band up to W-band and is higher than all reported mm-wave silicon PAs which have peak PAE > 20% and demonstrates for the first time concurrent multiband (triple-band) transmission with superior performance at multi-Gb/s.

Design of an Ultra-Compact 60-GHz Bi-Directional Amplifier in 65-nm CMOS

This letter presents an ultra-compact two-stage 60-GHz differential bi-directional amplifier (DBA) design in a 65-nm CMOS process. To satisfy the stability and gain requirements, a differential neutralized bi-directional common-source gain cell combined with the cross-coupled gm-boosting technique is proposed. In addition, a layout-symmetrical coupled line transformer is used as the inter-stage matching network to achieve broadband operation, reducing insertion loss and ensuring identical responses in both forward/backward modes. The proposed DBA achieves a peak gain of 16.1 dB with a 3-dB bandwidth of 15 GHz (52-67 GHz), maximum OP <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex> $_{{1 ,,dB}}$ </tex> </formula> of 5.1 dBm, <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex> $P_{{SAT}}$ </tex> </formula> of 9.6 dBm, a peak PAE of 11.5% at 62 GHz, respectively, consuming 70 mW from a power supply of 1.2 V. The circuit core occupies an ultra-compact area of only 0.0675 mm².

A Dual-Mode W-Band Eight-Way Parallel–Series Power-Combining PA With +18-dBm P sat and 15.1% PAE in 65-nm CMOS Technology

This letter presents the design of a Dual-mode W-band eight-way power-combining power amplifier (PA) implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology ( $f_{t}$ / $f_{{max}}$ : 210 GHz/240 GHz). A configurable parallel-series-based eight-way power combine technique is proposed to achieve high output power with high power efficiency near half of $f_{t}$ . The eight-way power-combiner is consisted of two transformer-based parallel two-way differential combiners and a coupled-line-based series combiner to achieve high passive efficiency and compact layout. The proposed PA achieves a measured peak gain of 30.9 dB with a bandwidth (BW) of 7.5 GHz. The PA has $P_{{sat}}$ of +18 dBm with an 1dB output compression point (OP1dB) of +13.8 dBm and a peak PAE of 15.1% in high-power mode. In the low-power mode (LPM), the measured $P_{{sat}}$ , OP1dB, and peak PAE are +13.6, +9.1 dBm, and 10.3%, respectively. The PAE is enhanced by 3.4% points at a 6-dB back-off in LPM. The core area of the proposed PA is 0.3 mm².

A Four-Element 5–6-GHz CMOS Quadrature Balanced Full-Duplex MIMO Transmitter With Wideband Digital Interference Cancellation

This work presents a 5-6 GHz full-duplex (FD) multiple-input and multiple-output (MIMO) transmitter front-end based on a quadrature balanced power amplifier (QBPA) topology and wideband digital interference cancellation. The proposed architecture benefits from low implementation complexity and is compatible with MIMO scaling with no additional hardware and power consumption penalties. The QBPA chip was fabricated in 180 nm CMOS and assembled on a four-element PCB MIMO array. The system was measured using a 320 MHz OFDM signal with 11 dB PAPR at 4 dBm TX power per element. 44 dB of combined self and cross-interference (XI) cancellation in the RF domain is demonstrated while requiring only -17 dBm of canceling signal power, along with -32 dB of TX EVM and 0.7 and 1.8 dB of TX and RX insertion losses (ILs), respectively. The standalone QBPA chip delivers P $_{sat}$ and peak PAE of >19.3 dBm and >31%, respectively, between 5 and 6 GHz.

Broadband Active Load-Modulation Power Amplification Using Coupled-Line Baluns: A Multifrequency Role-Exchange Coupler Doherty Amplifier Architecture

Broadband active load-modulation power amplifiers (PAs) are effective to enable multistandard wireless communication systems with high dynamic-range wideband signals and high energy efficiency. Traditional Doherty or outphasing PA architectures support their classic active load-modulation operations but, however, exhibit limited carrier bandwidth. We propose a broadband active load-modulation PA architecture with multifrequency role-exchange coupler-based Doherty amplifier (MF-CDA) operations to cover over-an-octave bandwidth. A proof-of-concept PA has been designed and fabricated in a 45-nm RF CMOS SOI process, which achieves a peak PAE of 41.88%–19.4% with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula> of over 22.66–19.53 dBm from 26 to 60 GHz. The PA also achieves a 33.75%–10.2% 6-dB PBO efficiency with its best 1.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> efficiency enhancement over an ideal Class-B PA. Using a single-carrier 64-QAM signal with 0.8–3 GSym/S (4.8–18 Gb/s), the PA supports an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {out}}$ </tex-math></inline-formula> of 15.8–11.3 dBm with an average PAE of 23.8%–8.5% at −23-dB rms EVM over the entire bandwidth. For a single-carrier 16-QAM signal with 1–2.5 GSym/S (4–10 Gb/s), the PA achieves an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {out}}$ </tex-math></inline-formula> of 18.7–15.6 dBm with an average PAE of 34%–14.8% at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;-$ </tex-math></inline-formula> 20-dB rms EVM over the bandwidth. The PA also supports 5G NR modulation using 5G new radio (NR) FR2 200 MHz 1-CC 64-QAM signals, achieving 16.54%–5.2% average PAE at 12.25–9.34 dBm and average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {out}}$ </tex-math></inline-formula> with an rms EVM of −24 dB over 26–60 GHz.

A Single-Ended Coupler-Based VSWR Resilient Joint mm-Wave True Power Detector and Impedance Sensor

This letter presents the design of a coupler-based VSWR-resilient mm-wave joint impedance/true-power detector integrated together with a wideband power amplifier (PA) in a 45-nm CMOS SOI process. At 38 GHz, the sensor measures the antenna impedance for up-to 3:1 VSWR with a maximum |Γ| and ∠Γ error of 0.238° and 28.9°, respectively. The coupler network also measures the real power delivered to the standard 50- Ω antenna load with an error within ±0.5 dB for a 16-dB dynamic range, as well as sensing the real power delivered to a complex antenna load (up-to 3:1 VSWR) with less than ±3.35-dB error. The PA testbed has a 3-dB bandwidth of 37.5% (26-38 GHz) and OP1dB bandwidth of 36.3% (27-39 GHz). The PA achieves a peak Psat of 17.29 dBm, OP1 dB of 16.33 dBm, and peak PAE of 29.77% at 37 GHz. The PA with a sensor occupies an area of 1.31×1.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , while the sensor takes an area of 0.47×0.971 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This work enables future built-in-self-testing (BiST) and in situ machine learning-based rapid performance optimization of mm-wave transmitter (TX) elements or TX arrays with element couplings.

80–110-GHz Broadband Linear PA With 33% Peak PAE and Comparison of Stacked Common Base and Common Emitter PA in InP

This work presents a high efficiency, compact 80-110-GHz InP power amplifier (PA) based on stacked common base (CB) topology and a counterpart design using conventional stacked common emitter (CE) topology. The comparison between the two exhibits that the former delivers higher power gain, superior-gain compression behavior (linearity), and higher back-off efficiency in W-band in 250-nm InP heterojunction bipolar transistor (HBT). At 90 GHz, the stacked CB/CE PA achieves 11.8 dB/6dB gain, 33%/34% peak PAE, 16.8%/14.5% PAE at 6-dB back-off, and Psat of 18.7 dBm/19.6 dBm. Modulation test exhibits an EVM of 2.38% at 11.8-dBm average power supporting 3 Gbps 64-QAM for the stacked CB PA. The stacked CB PA with 17.9-18.9-dBm Psat across 80-110 GHz demonstrates one of the highest efficiency, broadband and linear PAs in W-band using InP technology.

A 75–305-GHz Power Amplifier MMIC With 10–14.9-dBm Pout in a 35-nm InGaAs mHEMT Technology

The demonstration of a 75-305-GHz power amplifier (PA) monolithic microwave integrated circuit (MMIC) is presented in this letter. The PA is based on an eight-cell traveling-wave unit amplifier (UA). Each cell contains an RF cascode with two two-finger transistors with a gate width of 20 μm each. In the output stage, a balanced configuration combines two UAs with Lange couplers. In front, a third UA is used as a driver amplifier. The PA MMIC is fabricated in a 35-nm gate-length metamorphic high-electron-mobility transistor technology. From 75 to 305 GHz, the PA yields a minimum output power of 10 dBm with an average value of 12.8 dBm. At 200 GHz, a peak output power and PAE of 14.9 dBm and 6.6% is achieved, respectively. To the best of the authors' knowledge, this is the first PA MMIC with an octave-bandwidth that provides an output power of 10 dBm at 300 GHz.

A 65nm CMOS 60 GHz Class F-E Power Amplifier for WPAN Applications

This work presents a two-stage 60 GHz Power Amplifier designed in a 65nm CMOS technology dedicated to low cost Wireless Personal Area Network (WPAN) applications. In order to provide a high efficiency operation, the PA is based on a Class E power stage. A Class F driver stage is also designed to provide a square waveform signal to the Class-E power stage. To realize the output networks of both driver and power stage at 60 GHz, distributed elements are used instead of lumped elements. The post-layout simulation results show a saturated output power of 15 dBm with a peak PAE of 26% at 60 GHz. It achieves a gain of 15dB at 60 GHz.

A 24-GHz CMOS Power Amplifier With Dynamic Feedback and Adaptive Bias Controls

A 24-GHz power amplifier (PA) for 5G communication is implemented with a 65-nm bulk CMOS process, which adopts analog linearization techniques of dynamic feedback control (DFC) and an adaptive bias control (ADB). The DFC decreases feedbacks and the ADB increases a gate bias of common sources (CSs) with an increase of the input signal power so that the DFC improves gain flatness and peak efficiency, and the ADB increases high power gain, saturation power, and peak efficiency. These analog linearization techniques lower the IMD3 by improving the AM-AM and AM-phase modulation (PM) of the PA. The proposed PA shows a saturation power of 18.7 dBm, a 1-stage PA gain of 15.3 dB, and a peak PAE of 37.2% with the 24.29-GHz continuous wave signal measurement. It also shows a linear power of 12.9 dBm and a linear PAE of 14.8% with a two-tone signal measurement that has a center frequency of 24.49 GHz and a bandwidth of 80 MHz.

Distortion mitigation for 100 and 250 MHz discrete supply modulation of a three-stage K-band MMIC PA

AbstractThis paper presents a high-efficiency linear GaN K-band transmitter for broadband high peak-average power ratio (PAPR) signals. A GaN MMIC 18.5–24 GHz three-stage power amplifier with over 4 W peak output power, 20 dB saturated gain, and 40% peak PAE is supply-modulated with a four-level discrete dynamic supply GaN MMIC. For 100 MHz signals with ${\rm PAPR}\gt 10\, {\rm dB}$, we demonstrate an average efficiency improvement from 14 to 20% with a simultaneous linearity improvement in noise power ratio (NPR) from 23 to 26 dB through a shaping function focused on gain linearization. For 250 MHz signal bandwidth, there is no observed degradation in NPR and the efficiency is improved by 5 percentage points. For discrete supply modulation, the switching transients between levels are experimentally investigated for wideband signals.

A 120-GHz Bandwidth CMOS Distributed Power Amplifier With Multi-Drive Intra-Stack Coupling

This letter presents a distributed power amplifier (DPA) topology that improves both the power combining efficiency and the operation bandwidth. Multi-drive intra-stack coupling is introduced in the design of the gain cells to break the tradeoff between high output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> ) requirement and the achieved bandwidth. The proposed technique also compensates for the input transmission line (TL) loss to accommodate more stages and achieve flat gain and higher P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> . A prototype eightstage, 16-dB gain, 120-GHz bandwidth DPA is fabricated in 45-nm CMOS silicon-on-insulator (SOI) using elevated coplanar waveguide (CPW) TLs with a core area of 0.51 mm2. The amplifier maintains an output P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> higher than 18 and 20 dBm, respectively, up to 60 GHz and achieves a peak PAE of 19.7% at 15 GHz. A 64-quadrature-amplitude modulation (QAM) modulated signal with data rate 30 Gb/s (5 GBaud/s) is demonstrated at 55 GHz with a 13.5 dBm average POUT and 6.9% PAE while the error vector magnitude (EVM) is kept below 5%. To the authors' knowledge, the achieved 757-GHz gain-bandwidth product (GBW) is the highest among reported non-cascaded DPAs. The DPA has also the highest continuous-wave (CW) and modulated PAE compared to other reported distributed amplifiers (Das).