Peak Current Mode Research Articles

A Novel Improved Coordinate Rotated Algorithm for PWM Rectifier THD Reduction

In this paper, a novel algorithm with a rotating coordinate system is proposed to improve the total harmonic distortion (THD) of PWM rectifiers. Aiming at solving the disadvantages of poor dynamic response, unstable switching frequency, and a large calculation burden in some current control methods, the proposed method employs the rotating coordinate system to control the active current and reactive current separately while modifying the calculation error. The proposed method is verified through a single-phase PWM rectifier. Based on the measured results and compared with many other algorithms, such as the peak current mode control (PCMC), average current mode control (ACMC), one cycle control (OCC), and modulating duty ratio (MDR), the proposed method not only effectively reduces the intermediate variables during calculation, but also improves the THD and reliability of the circuit. The proposed method can be applied in single-phase PWM rectifiers applied in household-distributed energy storage systems.

GÜÇ FAKTÖRÜ VE FLICKERI DİKKATE ALAN BİR TEPE AKIM MODU KONTROLLÜ SEPİC LED SÜRÜCÜ TASARIMI

In this paper, a peak current mode controlled single ended primary inductor converter (SEPIC) LED driver is proposed to control the brightness of the LED. One string of 37 series connected LEDs is adopted as output of the circuit. The proposed control strategy is based on measuring MOSFET peak current value using a shunt resistor. When this voltage reaches peak threshold value, controller turns off MOSFET. The output current is adjusted to desired levels by changing this peak threshold value. The power factor in the AC power supply side is low because of the full wave bridge rectifier with capacitor filter at the input of the converter. The proposed control strategy is applied with power factor correction (PFC) circuit where input voltage is multiplied by control voltage to achieve high power factor. In PFC circuit, although the line current waveform is slightly distorted due to voltage limitations in integrated circuit (IC) chip used for the proposed control strategy, power factor is kept above 0.9 for operation region between 100mA-300mA. In addition, flicker on LED string is measured for operating current region and flicker limits are revealed. Adjustable output current levels, low flicker on LED string, MOSFET peak current control at each cycle, fast output dynamics, and high power factor are acquired by the proposed control strategy.

Chaos analysis of Buck converter with non-singular fractional derivative

This paper presents a time-domain mathematical model of the Buck converter using the non-singular fractional derivative that was proposed by Caputo and Fabrizio. The time-domain waveforms of the output voltage and current of the converter in different orders are obtained, and the correctness of the time-domain model has been verified. On this basis, the discrete iterative mapping model of the fractional-order Buck converter in peak current mode is established. The chaotic behaviors of the system are studied by numerical simulations, and the bifurcation diagrams at different fractional orders are investigated. The analog circuit implementation of the fractional-order Buck converter is established, and the results obtained via circuit simulations are consistent with the results of numerical simulations, which effectively validate the accuracy of the previous theoretical analysis.

Research on Double-loop Control Method of Voltage Drop DC-DC Converter Based on Peak Current Mode

This paper mainly studies the dual-loop control algorithm based on peak current mode. The working principle and system structure of the step-down switching power supply are introduced. The system uses PWM modulation and peak current mode to design the converter, and simulates its function in MTALAB/simulink. The result shows that the step-down circuit can basically realize the expected function, with high conversion efficiency and stable output voltage.

Digital Predictive Current-Mode Control for Asymmetrical Half-Bridge LED Constant-Current Driver

In this paper, we propose three advanced digital predictive current-mode control (DPCC) algorithms based on a simplified estimation method of duty cycle lost time for asymmetric half-bridge (AHB) LED constant-current driver. They are the digital predictive peak current mode control(DPPCC) algorithm based on leading-edge modulation, the digital predictive quasi-valley current mode control(DPqVCC) algorithm based on trailing-edge modulation, and the digital predictive quasi-average current mode control(DPqACC) algorithm based on double-edge modulation. Simulation and experimental results demonstrate that the three DPCC algorithms can effectively offset the effect of delay on digital control performance, which confirms the superiority of DPqACC. When the DPqACC is applied, the series-load-jump transition times are below 4.5 ms, the maximum load adjustment rate is 0.5%/ V, and the output current can be tuned continuously between 0.3 A and 4.5 A with the longest transition time of 1 ms. Moreover, the three DPCC algorithms are capable of compensating for low-frequency ripples due to the rapid regulation speed of the inner loop. With the electrolytic capacitance removed without additional ripple compensation, the maximum peak-to-peak value of the low-frequency secondary ripple is 0.1163 A (2.91%) when the input is 400 53sin(2ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>lin</i></sub> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> ) V and the output is 4 A. This approach provides an excellent solution for the digital design of low-ripple AC-DC LED constant-current drivers without electrolytic capacitance.

Design and Modelling of Buck Regulators Driving Loads With Complex Parasitics

Switching regulators improve power efficiency and reduce cost of electronic devices. Continued advances in the performance of components have outpaced the models used for their analysis and design. Physical limits of the parts and their arrangement introduce nonideal parasitic effects that can no longer be ignored. This article introduces an extensible frequency domain model of buck regulators that can capture parasitic effects of arbitrary complexity. Such models are derived for both continuous and discontinuous conduction modes of peak current mode controllers. The proposed models are shown to be accurate when compared to other methods, while having lower computational cost. Numerical optimization is applied to design systems using the increased complexity models. Cost functions are developed, and shown to produce improved designs when compared to existing published examples. Experimental measurement finds the models accurately predict the performance of implemented designs. Additional parasitic elements are added to the model, showing improved fit to measured results, demonstrating the extensibility and accuracy possible.

Digital peak current mode control of isolated current‐fed push‐pull DC‐DC converter with slope compensation

AbstractThe isolated current‐fed push‐pull dc‐dc converter has some practical advantages such as improved cross regulation characteristics, reduced output noise, and good overall efficiency. Although detailed insight on this converter is available in the literature, the use of digital peak current mode with slope compensation control methodology has not been explicitly presented. This paper discusses digital peak current mode control of a current‐fed push‐pull converter with a novel double digital pulse‐by‐pulse current limiting scheme. Push‐pull topology is implemented on the primary side of an isolation transformer in a dc‐dc bidirectional converter. Achieving this control solution of isolated push‐pull converter is attractive especially in controlling battery power flow in smart micro‐grids. By using a digitally controlled push‐pull converter, the ability to change controller parameters and the use of droop control methods for storage are easier. Furthermore, current mode control provides capability of equal current sharing between parallel converters and eliminates the transformer saturation problem that is common in push‐pull topology. Using continuous time model of the converter, a Type II compensator is designed and implemented in discrete time domain. Digital slope compensation is applied to eliminate the high frequency oscillations caused by current feedback loop. The control method and slope compensation are implemented on STM32F303 mixed‐signal microcontroller. On‐chip analog comparator disabled the PWM output if the sensed current exceeds the reference current until next PWM cycle. The digital controller performance is confirmed by 13 W hardware implementation including fast transient response and stable operation.

A Compensated Peak Current Mode Control PWM for Primary-Side Controlled Flyback Converters

In this paper, a feedback compensator (FBC) and a Feedforward compensator (FFC) are proposed to construct a novel compensated peak current mode control pulse width modulation (CPC-PWM) for primary-side controlled flyback converters. Using the proposed FBC, the PWM duty cycle of an abnormal operating flyback converter would be descended to limit the output current for reducing power dissipation. Using the proposed FFC, the effect of delay time would be descended to reduce the over-flow current for increasing the current accuracy. In this paper, the operating principle and mathematical model are described and analyzed. Then, the component values are well designed to satisfy the electrical specifications. Finally, a prototype is designed and realized to access system performance. The experimental results show that the proposed CPC-PWM can validate in a wide input voltage range and output short conditions, which also has good current accuracy and reduces power dissipation by about 68%.

Compensated Single Input Multiple Output Flyback Converter

A new single-input multiple-output (SIMO) converter is proposed in this work by incorporating flyback and buck converters in a master–slave configuration. The objective of this work is to address the cross regulation problem, achieve tight voltage regulation, improve the circuit form factor and attain a fast transient response for a SIMO flyback converter. The flyback converter maintains the output channels within 10% of their rated voltages and the SIMO buck converter is placed in series with the flyback converter such that it compensates for the output voltage deviation. Moreover, a time multiplexing switching scheme decouples output channel to eliminate the cross-regulation problem and remove the need for an additional winding transformer per each output channel. A type II compensator with a peak current mode controller was designed to achieve faster transient response which is critical for the proposed configuration. A thorough steady-state analysis was carried out on a triple output channel topology to obtain the design criteria and component values. MATLAB/Simscape modelling and simulation was used to validate the effectiveness of the proposed converter with the result yielding satisfactory transience even with load disturbance. Additionally, the result of the proposed converter is compared with previously published works.

A Scalable Multiphase Current-Mode Buck Controller With Sub-Milliohm DCR Current Sensing and Synchronized Overcurrent Protection

This article presents a scalable multiphase peak current-mode Buck controller with sub-milliohm direct current resistance (DCR) current sensing and synchronized overcurrent protection. Low DCR current sensing capability is critical in pursuing high efficiency and precise current balancing. For this purpose, a sub-milliohm DCR current sensing circuit is proposed. The low-frequency current signals from all the phases are amplified by a time-shared amplifier, and the outputs are combined with the exaggerated high-frequency signals, respectively, to rebuild the proportional current sensing signals. The small signal analysis and the design guidelines of the proposed sensing scheme are presented. The proposed current sensing scheme enhances the signal-to-noise ratio, improves the phase to phase current balancing, and dramatically reduces the silicon area of the sensing circuit. A latch-up problem of hiccup mode over current protection in the multi-chip parallel system is addressed in this article. A synchronized hiccup mode over current protection scheme is designed to solve the issue without adding extra communication bus to the system. The proposed controller is fabricated using a 0.6- μm BiCMOS process, and the experimental results prove the effectiveness of the current sensing circuit and protection scheme.

Dynamic analysis and chaos control of the switched‐inductor boost converter with the memristive load

SummaryThis paper investigates dynamic behaviors and the time‐delay feedback control method for a peak current mode (PCM) controlled switched‐inductor boost converter with a memristive load. The research contents include the following: (1) The state equations are constructed for the PCM switched‐inductor boost converter with the memristive load. (2) The bifurcation and chaos behaviors of the boost converter are analyzed by the MATLAB numerical simulation. (3) The Power Simulation (PSIM) circuit simulation of the switched‐inductor boost converter is illustrated the correctness of the MATLAB numerical simulation. (4) The time‐delay feedback control is adopted to suppress the bifurcation and chaos behaviors of the boost converter and is verified being effective.

Investigation of ultra-lift Luo-converter with peak, average and hysteresis current-mode control

The Renewable energy system, electric vehicle, and telecommunication applications require relatively stable power converters with a high gain and enhanced noise immunity. A study of three different types of current-mode controllers for high-gain ultra-lift Luo-converter (ULC) is discussed in this paper. The stability of a constant frequency peak current-mode controller (PCM), an average current-mode controller (ACM) and a variable frequency hysteresis current-mode controller (HCM) are analyzed based on small-signal characteristics. Using mathematical modeling of the controllers, the closed-loop transfer functions such as control voltage to output voltage, current loop gain, inductor current to control voltage, and audio susceptibility are obtained. These transfer functions along with MATLAB simulation results for PCM, ACM and HCM controllers are compared. Then, the component losses of the ULC converter using PCM, ACM and HCM controllers are calculated and an efficiency comparison of different control techniques is done. Investigations of the voltage and current stresses of the switch and diodes are also carried out. Finally, a prototype is fabricated to validate the performance of the converter.

Chaos suppression for a Buck converter with the memristive load

The memristor is a nonlinear device with a particular memory function and is widely used in various circuit researches. This work studies the peak current mode controlled (PCMC) buck converter with the memristive load at the continuous current mode (CCM). Firstly, a state equation for a buck converter with the memristive load is derived and a generic voltage-controlled memristor simulator is constructed by using a nonlinear function model; Secondly, facing the system chaos caused by changing bifurcation parameters, we introduce ramp compensation to stabilize the system at period-1. The chaos is effectively suppressed, this provides a guide for parameters choosing in buck converters with nonlinear loads in practical applications. The simulation is implemented by using MATLAB and PSIM.

Implementation of Soft-Switching Auxiliary Current Control for Faster Load Transient Response

A control circuit for the auxiliary buck/boost converter was designed and implemented to improve the load transient response of the buck converter. The circuit shapes the auxiliary inductor current in the critical conduction mode through peak current mode control. The soft-switching operation of the auxiliary switches minimizes the power loss and thus increases the efficiency of the auxiliary converter. Along with the design guidelines and estimated power loss to improve the performance of the proposed control technique, the implementation of the control circuit is explained in detail. Simple analog ICs such as operational amplifiers and comparators, and a couple of logic gates suffices the realization of the proposed control. A prototype buck converter whose input voltage, output voltage, and switching frequency were 15 V, 3.3 V, and 200 kHz, respectively were tested with the implemented control circuit to verify the performance of the proposed control technique.

A Fast Switching Current Controlled DC/DC Converter for Automotive Applications

Automotive industry requires integrated circuits with both low cost, to maintain product competitiveness, and high efficiency, moving towards solutions as green as possible. Each electronic device within the car needs for a regulator to provide a steady supply to ensure correct and safe operation. Among all regulator, DC/DC Converters are the most valid solution to achieve a high efficiency-price ratio. The DC/DC Converter needs for a control loop to monitor the load operation. The basic control loop topologies are well known in the state-of-the-art. The paper presents a DC/DC Buck Converter for automotive applications designed in low cost technology with an upgraded version of the Peak Current Mode Control which uses a constant off-time. For chip area reduction, an n-channel power-DMOS is chosen as power transistor. The design of each block composing the circuit is presented. To guarantee DC-DC Buck converters high-efficiency and low cost (in terms of external components) increasing switching frequency is mandatory. A  1.5 MHz switching frequency has been chosen to reduce external components size. The device is optimized by design to be able to achieve 94.4% efficiency using a 3V  3A load. The post-layout simulations of the system are shown, confirming the expected circuit behavior also including the presence of wiring parasites. A PCB is also designed to test the packaged die to ultimately demonstrate the chip’s robustness and suitability in a real automotive application.

A Novel Digital Control Method of Primary-Side Regulated Flyback With Active Clamping Technique

Because of the different working principles between conventional flyback and active-clamped flyback (ACF), the existing primary-side regulation (PSR) technology cannot be applied to ACF. And in order to achieve PSR of ACF, a low-cost digital sampling method based on the auxiliary winding of the transformer is proposed. In the conventional peak current mode (PCM) controlled ACF, the sampling resistor of primary current may introduce additional power loss, and high-frequency oscillations during sampling may reduce system's stability. Therefore, a digital feedback-feedforward control (FFC) method is proposed to eliminate the sampling resistor. The stability of the proposed control method and its influence on the dynamic response are studied. In addition, since GaN device has higher power loss during reverse conduction than its Si counterpart, design considerations of reverse conduction time of power switches are also discussed in this paper. All control methods and design considerations are verified on a GaN-based 12V-3A ACF, and the proposed control strategy is implemented by FPGA.

Z-domain modeling of peak current mode control for full-bridge DC-DC buck converters

Traditional local-averaged state-space modeling for peak current mode (PCM) controls fails to explain the subharmonic oscillation phenomenon when the spectrum is higher than half of the switching frequency. To address this problem, this paper presents a small-signal modeling method in the z-domain, and builds a discrete linear model for the current loop of a full-bridge DC-DC converter. This discrete model is converted into a second-order continuous model that is able to represent the system performance with a wider frequency range. A frequency-domain analysis shows that this model can be used to explain the subharmonic oscillations and unstable characteristics. This provides an engineering guideline for the practical design of slope compensation. The effectiveness of the proposed modeling method has been verified by simulation and experimental results with a prototype working in the Buck mode.

Sampled-Data Modeling for PCM and ZVS Controlled Critical Conduction Mode (CrCM) Active Clamp Flyback (ACF) Converter at Variable Switching Frequency

Critical conduction mode (CrCM) active clamp flyback (ACF) converter is regarded as a good candidate for low power adaptor applications. However, the most adopted control strategy of variable-frequency peak current mode (VF-PCM) and discrete zero voltage switch (ZVS) control makes it difficult to get the accurate small signal model. Therefore, by using sampled-data modeling method, this paper proposes an exact small signal model of CrCM ACF converter for the first time. In the modeling process, the influence of discrete-ZVS control is firstly considered. The conduction time of power switch is regarded as the control signal, which is different from constant-frequency converter. The total current close-loop transfer function is simplified by the linear combination of single VF-PCM and discrete-ZVS control model. After considering the sampling effect and the modulator gain from the derived sampled-data model respectively, the control-to-output transfer function of CrCM ACF converter is developed. The analytical results are analyzed by comparing with single VF-PCM and the widely used average model. Finally, to validate the accuracy of the proposed model, a 65W 20V output CrCM ACF converter is simulated and measured. The verification shown that the proposed sampled-data model is basically agreement with the simulation and experimental results.

Digital Predictive Current-Mode Control of Three-Level Flying Capacitor Buck Converters

This article investigates the use of digital predictive current-mode control (DPCMC) in dc-dc three-level flying capacitor (3LFC) buck converters. In particular, stability and flying capacitor (FC) balancing properties of predictive peak, average, and valley current-mode controllers are studied when operated in single- and multisampled modes. A variant of the multisampled DPCMC obtained through a fast-update of the duty cycle command is also disclosed and analyzed. Results indicate that single-sampled DPCMC is always stable, and that fast-update approaches can strongly improve the converter dynamic response. Multisampled controllers are also shown to be inherently more robust than single-sampled ones against timing mismatches in the control signals, resulting in a smaller FC voltage imbalance. The analysis is validated in simulation and experimentally on a 500 kHz, 12-1.5 V, 500 mA 3LFC buck case study.

Asymmetric slope compensation for digital hybrid current mode control of a three-level flying capacitor buck converter

The three-level flying capacitor (3LFC) buck converter has the potential to provide better efficiency and higher power density as compared to the traditional buck converter. However, due to the flying capacitor?s instability issues, control is challenging. In this paper, the digital hybrid current mode (DHCM) control method, which combines the average and peak current mode control techniques, is modified and implemented to a 3LFC buck converter. For flying capacitor (FC) voltage balancing, a novel asymmetric slope compensation (ASC) technique is presented. The proposed ASC technique achieves FC voltage balancing by adjusting the slope compensation of the two switching pairs asymmetrically, and therefore is applicable to any type of digital peak current mode control (PCM) method. The ASC technique for DHCM control of the 3LFC buck converter is verified in simulations and experimentally with an ARMbased mixed-signal microcontroller on a 250-kHz, 24-V input, and 35-W/4-A output prototype. The overall control method enables the implementation of the 3LFC buck converter for accurate and fast current regulation, and therefore is especially advantageous for LED and laser diode driver applications.