PD SOI Research Articles

Investigation of the Gate Length and Drain Bias Dependence of the ZTC Biasing Point Instability of N- and P-Channel PD SOI MOSFETs

This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures (from room temperature up to 573K). The study takes into account temperature dependent model parameters such as threshold voltage and channel mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplifications used for the VZTC model as a function of temperature in the linear and the saturation regime.

A Study on Hot Carrier Reliability of Radiation Hardened H-gate PD SOI NMOSFET after Gamma Radiation

A Study on Hot Carrier Reliability of Radiation Hardened H-gate PD SOI NMOSFET after Gamma Radiation

High-performance RF Switch in 0.13 μm RF SOI process

A high-performance single-pole single-throw (SPST) RF switch for mobile phone RF front-end modules (FEMs) was designed and characterized in a 0.13 μm partially depleted silicon-on-insulator (PD SOI) process. In this paper, the traditional series-shunt configuration design was improved by introducing a suitably large DC bias resistor and leakage-preventing PMOS, together with the floating body technique. The performance of the RF switch is greatly improved. Furthermore, a new Ron × Coff testing method is also proposed. The size of this SPST RF switch is 0.2 mm2. This switch can be widely used for present 4G and forthcoming 5G mobile phone FEMs.

SNN Pattern Recognition Using Amorphous Carbon Oxide Based Synapse and Fully-Depleted Strained Silicon-on-Insulator n-Mosfet Neuron

Artificial neural networks imitating human brain has been greatly improved performance of artificial intelligence used for image-voice recognition, data analysis and other variety of fields. Recently, AlphaGo, based on deep learning algorithm created by Google DeepMind, defeated a human professional player in Go game. Despite this remarkable performance, there is a limit to the artificial intelligence that works in the conventional Von Neumann structure. For example, AlphaGo requires a high integration area of neurons and synapses and the operation power of about 1 MW, that is about four orders of magnitude higher than that of a human brain consuming about 20 W of power. In order to overcome these drawbacks, recent researches have been carried out to implement the functions of neurons and synapses, which are core components of neural networks, with electrical devices such as memristor, resistance random-access-memory (ReRAM), Mott transistor, partially-depleted silicon-on-insulator nMOSFET (PD SOI n-MOSFET), and spin-torque-transfer magnetic-random-access-memory (STT MRAM). In particular, ReRAM has intensively researched as a synapse because of a behavior of memristor, a simple device structure (i.e., top electrode/ReRAM material/bottom electrode), a fast write/erase speed of several tens of n sec., and a possibility of tera-bit integration. Many researches on ReRAM based synapses have remarkably studied to achieve a good linearity and symmetry of potentiation and depression. In this works, we proposed amorphous carbon oxide (α-COx) based synapse, showing synapse characteristic such as potentiation/depression as shown in Fig. 1. (a) and (b). For the more, it has been reported that a conventional neuron has been operated by a circuit using several C-MOSFETs, capacitor, and resistance, generating a high operation power and a heavy burden of neuron integration area. In our study, we proposed a novel neuron using a strained fully-depleted strained silicon-on-insulator (FD ε-SOI) n-MOSFET having leaky integration (LI) function as shown in Fig. 2. (a) and (b). Moreover, several neural networks have been researched; i.e., SNN, deep-neural-network (DNN), convolutional-neural-network (CNN), and Recurrent-neural-network (RNN). In particular, SNN has been intensively attracted since it demonstrated a lower power consumption and a possibility of real-time proceed event although its showed a lower accuracy of the pattern recognition. In our study, we tested the accuracy of the SNN pattern recognition for our proposed α-COx synapse and FD ε-SOI n-MOSFET neuron as shown in Fig. 3. (a) and (b). * This research was supported by Nano·Material Technology Development Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Science, ICT and Future Planning(grant number. 2016910249) * This material is based upon work supported by the Ministry of Trade, Industry & Energy(MOTIE, Korea) under Industrial Technology Innovation Program (1006855). * The EDA tool was supported by the IC Design Education Center(IDEC), Korea. Figure 1

Enhanced radiation-induced narrow channel effects in 0.13- PDSOI nMOSFETs with shallow trench isolation**Project supported by the Weapon Equipment Pre-Research Foundation of China (Grant No. 9140A11020114ZK34147) and the Shanghai Municipal Natural Science Foundation, China (Grant No. 15ZR1447100).

Total ionizing dose responses of different transistor geometries after being irradiated by 60Co γ-rays, in 0.13- partially-depleted silicon-on-insulator (PD SOI) technology are investigated. The negative threshold voltage shift in an n-type metal-oxide semiconductor field effect transistor (nMOSFET) is inversely proportional to the channel width due to radiation-induced charges trapped in trench oxide, which is called the radiation-induced narrow channel effect (RINCE). The analysis based on a charge sharing model and three-dimensional technology computer aided design (TCAD) simulations demonstrate that phenomenon. The radiation-induced leakage currents under different drain biases are also discussed in detail.

Steep subthreshold slope characteristics of body tied to gate NMOSFET in partially depleted SOI

A new body tied to gate (BTG) n-channel metal-oxide-semiconductor field-effect-transistor (NMOSFET) with a diode in partially depleted SOI (PD SOI) is proposed and investigated. We first compare the transfer and output characteristics between the regular and BTG NMOSFETs with grounded body and floating body. The steep subthreshold slope (<6mV/dec) and low OFF current (∼0.01pA/μm) of the BTG NMOSFET with floating body are observed at VD=3.3V. Mechanisms of the floating body effect (FBE) and the diode are analyzed to explain the outstanding performance. The hysteresis characteristics of BTG NMOSFETs are also presented in comparison to regular ones. Finally, the steep subthreshold characteristics of the BTG NMOSFET with floating body at low drain voltage are studied for ultralow power application.

Ultra-low temperature radio-frequency performance of partially depleted silicon-on-insulator n-type metal–oxide–semiconductor field-effect transistors with tunnel diode body contact structures

Radio-frequency (RF) characteristics under ultra-low temperature of multi-finger partially depleted silicon-on-insulator (PD SOI) n-type metal–oxide–semiconductor field-effect transistors (nMOSFETs) with tunnel diode body-contact (TDBC) structure and T-gate body-contact (TB) structure are investigated in this paper. When operating at 77 K, TDBC device suppresses floating-body effect (FBE) as well as the TB device. For TB device and TDBC device, cut-off frequency (fT) improves as the temperature decreases to liquid-helium temperature (77 K) while that of the maximum oscillation frequency (fMAX) is opposite due to the decrease of the unilateral power gain. While operating under 77 K, fT and fMAX of TDBC device reach to 125 GHz and 77 GHz, representing 8% and 15% improvements compared with those of TB device, respectively, which is mainly due to the lower parasitic resistances and capacitances. The results indicate that TDBC SOI MOSFETs could be considered as promising candidates for analog and RF applications over a wide range of temperatures and there is immense potential for the development of RF CMOS integrated circuits for cryogenic applications.

Effects of back gate bias on radio-frequency performance in partially depleted silicon-on-inslator nMOSFETs

The effects of back gate bias (BGEs) on radio-frequency (RF) performances in PD SOI nMOSFETs are presented in this paper. Floating body (FB) device, T-gate body-contact (TB) device, and tunnel diode body-contact (TDBC) device, of which the supply voltages are all 1.2 V, are compared under different back gate biases by different figures of merit, such as cut-off frequency (fT), maximum frequency of oscillation (fmax), etc. Because of the lack of a back gate conducting channel, the drain conductance (gd) of TDBC transistor shows a smaller degradation than those of the others, and the trans-conductance (gm) of TDBC is almost independent of back gate bias. The values of fT of TDBC are also kept nearly constant under different back gate biases. However, RF performances of FB and TB each show a significant degradation when the back gate bias is larger than ∼20 V. The results indicate that TDBC structures could effectively improve the back gate bias in RF performance.

Simulations of Transient Behavior and Parasitic Effects for 20 nm Gate Length of PD SOI nMOSFET

In this paper, we report the possible transient behavior for 20nm partially depleted silicon-on-insulator (PD SOI) n-channel MOSFET studied using Synopsys TCAD program. Tunnelling model is set at Si/SiO2 interface by varying front gate oxide. Parasitic floating body effects also have been observed in the device behavior for both linear and saturation regions, the magnitude of these effects depends on the front gate oxide thickness. For 4nm gate oxide thickness, the parasitic floating body effect is dominant at low drain voltage.

Influence of channel length on PD SOI PMOS devices under total dose irradiation

This paper mainly investigates the total dose irradiation effects on 0.8 μm PD SOI PMOS devices which are exposed to 60Co γ-rays at a dose rate of 50 rad(Si)/s. The channel length dependence of SOI PMOS devices at total dose irradiation is investigated. The result shows that the threshold voltage shift is only a little larger for shorter channel devices at the same total dose. However, the degradation of maximum transconductance for shorter channel devices is more significant. We found that the oxide-trapped charge is the main factor impacting the threshold drift. We may conclude that a short channel device can produce more interface trapped charges by using the subthreshold separation technology.

Improvement of RF Performance by Using Tunnel Diode Body Contact Structure in PD SOI nMOSFETs

Radio-frequency (RF) performance of multi-finger partially depleted silicon-on-insulator (SoI) nMOSFETs with tunnel diode body contact (TDBC) structure is investigated in this letter. The TDBC structure suppresses floating-body effect and body instability significantly and shows less drain conductance degradation with respect to FB and TB devices. The peak cutoff frequency (fT) and maximum oscillation frequency (fMAX) of TDBC devices are 96.4 and 132.8 GHz, respectively. Due to lower parasitic resistances and capacitances, the device with TDBC structures represents an improvement of 10% for the fT and of 90% for the fMAX compared with conventional T-gate body-contact devices. The investigation results indicate that TDBC SoI MOSFETs are a good candidate for analog and RF applications.

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

Full adder is one of the most important digital components for which many improvements have been made to improve its architecture. In this paper, we present two new symmetric designs for Low-Power full adder cells featuring GDI (Gate-Diffusion Input) structure and hybrid CMOS logic style. The main design objectives for these adder modules are not only providing Low-Power dissipation and high speed but also full-voltage swing.In the first design, hybrid logic style is employed. The hybrid logic style utilizes different logic styles in order to create new full adders with desired performance. This provides the designer with a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second design is based on a different new approach which eliminates the need of XOR/XNOR gates for designing full adder cell and also by utilizing GDI (Gate-Diffusion-Input) technique in its structure, it provides Ultra Low-Power and high speed digital component as well as a full voltage swing circuit.Many of the previously reported adders in literature suffered from the problems of low-swing and high noise when operated at low supply voltages. These two new designs successfully operate at low voltages with tremendous signal integrity and driving capability. In order to evaluate the performance of the two new full adders in a real environment, we incorporated two 16-bit ripple carry adders (RCA). The studied circuits are optimized for energy efficiency at 0.13µm and 90nm PD SOI CMOS process technology. The comparison between these two novel circuits with standard full adder cells shows excessive improvement in terms of Power, Area, Delay and Power-Delay-Product (PDP).

Impact of strain on gate-induced floating body effect for partially depleted silicon-on-insulator p-type metal–oxide–semiconductor-field-effect-transistors

This work investigates impact of mechanical strain on gate-induced-floating-body-effect (GIFBE) for partially depleted silicon-on-insulator p-type metal–oxide–semiconductor field effect transistors (PD SOI p-MOSFETs). First part, the original mechanism of GIFBE on PD SOI p-MOSFETs is studied. The experimental results indicate that GIFBE causes a reduction in oxide electric field (Eox), resulting in an underestimate of negative-bias temperature instability (NBTI) degradation. This can be attributed to the electrons tunneling from the process-induced partial n+ poly gate and anode electron injection (AEI) model, rather than the electron valence band tunneling (EVB) widely accepted as the mechanism for n-MOSFETs. And then, the second part shows that the strained FB device has less NBTI degradation than the unstrained devices. This behavior can be attributed to the fact that more electron accumulation was induced by strain-induced band gap narrowing, reducing NBTI significantly.

The Impact of Mechanical Strain on Reliability Issue for PD SOI MOSFETs

This work studies the impact of mechanical strain on reliability issue for partial depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors (PD SOI p-MOSFETs), including negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-MOSFETs and n-MOSFETs, respectively. Based on AEI model, the mechanical compressive strain was introduced into the SOI p-MOSFET under NBT stress. It shows the strained FB device exhibits a much less NBTI degradation, since significant accumulation of electron induced by strain-induced band gap narrowing, reducing the EOX during NBT stress. Additionally, the degradation of HCS on SOI n-MOSFETs is also studied. It can be seen that the FB device shows worse degradation than GB device due to FBEs. However, the impact of mechanical strain results more serious degradation on HCS for GB device. Therefore, based on the lucky electron mode, we found that strain-induced band gap narrowing dominates the increase in impact ionization rate, aggravating HCS.

Investigation of Random Telegraph Signal with PD SOI MOSFETs

A novel method, called random telegraphy signal (RTS), was constructed to characterize the gate oxide quality and reliability of metal-oxide-semiconductor field-effect-transistors (MOSFETs). With the aggressive scaling of device size, drain current RTS (ID-RTS) become a critical role in carrier transport of MOSFETs. Besides, RTS in gate leakage current (I¬G-RTS) was denoted as the other new method to understand property of gate oxide. Recently, the study of RTS has also been made in MOSFETs with metal gate and high dielectric constant (metal gate/high-k). However, the RTS in partial depleted silicon-on-insulator MOSFETs (PD SOI MOSFETs) has not comprehensively been studied yet. This paper investigates RTS characteristics in PD SOI MOSFETs.

Impact of Mechanical Strain on GIFBE in PD SOI p-MOSFETs as Indicated From NBTI Degradation

This letter investigates the impact of mechanical strain on gate-induced floating-body effect in partially depleted silicon-on-insulator p-channel metal-oxide-semiconductor field-effect transistors. The strained FB device has less NBTI degradation than unstrained devices. This behavior can be attributed to the fact that more electron accumulation induced by strain effect reduces the electric oxide field significantly during NBTI stress. Analysis of the body current under source/drain grounded and floating operation indicates an increase in the anode electron injection and electron tunneling from conduction band which occur at the partial poly-Si gate and Si substrate, respectively. This phenomenon can be attributed to the bandgap narrowing which has been induced by the strain effect.

Investigation of Random Telegraph Signal with PD SOI MOSFETs

not Available.

Investigation of Mechanisms and Random Telegraph Signals in Static and Dynamic BTI Stress on PD SOI MOSFETs

not Available.

The Impact of Mechanical Strain on Reliability Issue for PD SOI MOSFETs

not Available.

Function of the parasitic bipolar transistor in the 40 nm PD SOI NMOS device considering the floating body effect

This paper reports the function of the parasitic bipolar device in the 40nm PD SOI NMOS device with the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during DC and transient operations could be modelled. During the turn-on transient by imposing a step voltage from 0V to 2V on the gate, the case with the a slower rise time shows a relatively faster turn-on in the drain current due to a stronger function of the parasitic bipolar device from smaller displacement currents through the gate oxide, as reflected in the current gain, as verified by the experimentally measured result.