PCI Express Interface Research Articles

A 500 × 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

In this article, we report on SwissSPAD3 (SS3), a 500 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gates, guaranteed by the circuit architecture to be nonoverlapping and covering the totality of the sensor’s exposure period. The gates can be adjusted with a temporal resolution of 17.9 ps, and the minimum measured gate width is 0.99 ns; to our knowledge, the shortest reported to date among large-format SPAD imagers. In the dual-channel mode, the burst frame rate is 49.8 and 97.7 kframes/s in the single-channel mode. A 2690-MB/s PCI express (PCIe) interface has been added to the data acquisition framework, enabling continuous operation at approximately 44 and 88 kframes/s. Due to optimizations of the gate-signal tree, we achieved a significant reduction to gate skew and gate width variation, which is negligible with respect to the SPAD temporal jitter. These improvements, along with sub-10-cps dark count rate (DCR) per pixel and 50% maximum photon detection probability (PDP), result in a sensor particularly well suited for fast acquisition fluorescence lifetime imaging microscopy (FLIM) experiments, for which we demonstrate reduced dispersion versus a single-gated sensor.

Beam Scanning Controller for Proton-Beam Writing

A scanning control system of the ion beam of MeV energies has been developed for the nuclear scanning microprobe and proton-beam writing channel as a part of accelerator-analytical complex based on the Sokol electrostatic accelerator of the Institute of Applied Physics of the National Academy of Sciences of Ukraine. The system was put into operation to replace the obsolete one based on microcontrollers. The scanning control system is based on a National Instruments reconfigurable module with a Field Programmable Gate Array. The module operates in real time and is connected to a personal computer by a high-speed PCI-Express interface with data buffering. The system provides two main modes of operation: exposure of sample areas with a given profile and raster secondary electrons imaging of the sample or a calibration grid. Profile exposure is possible both in raster and functional scanning modes. Automatic calibration of the profile scale and scan raster is also implemented. Using of reconfigurable logic makes it possible to quickly adjust the system to the conditions of a particular experiment and the available equipment. The hardware capabilities of the scanning control system allows in the future to connect up to 4 spectrometric ADC for mapping the elemental composition of samples using Proton Induced X-ray Emission and Proton Backscattering. The first experiments on the irradiation of polymethylmethacrylate have been carried out; images of the obtained microstructures taken with a scanning electron microscope are shown. The aim of this work is to develop a control system for scanning a high-energy focused beam in proton beam writing technique to create small-sized structures for special purposes, as well as to demonstrate the efficiency of the developed system.

A High-Performance and Hardware-Efficient PCIe Transmission for a Multi-Channel Video Using Command Caching and Dynamic Splicing on FPGA

With the increasing requirements of transmitting larger amounts of diverse video and image data, the PCI express (PCIe) interface has been extensively used in high-speed digital systems for multimedia processing and communication. However, the existing PCIe transmission methods are not efficient to transmit multi-channel videos on FPGA processors, as they waste PCIe bandwidth and hardware resources. In this paper, an efficient PCIe transmission method for multi-channel video is presented on an FPGA processor. First, to reduce the programmed I/O (PIO) write latency, the command caching method is adopted. The traditional DMA descriptors are transformed into DMA commands, which are smaller, and the command buffer is used to store these commands. Second, a dynamic splicing mechanism is proposed for data transmission and commands the scheduling separately. The multi-type data is transmitted concurrently in this dynamic splicing mechanism. Moreover, the adjacent commands are spliced into one command, which reduces the DMA initiation times. Finally, the direct kernel memory access technique and timer self-feedback monitor technique are applied to improve the transmission efficiency and enhance the system reliability. The experimental results show that the transmission efficiency of the proposed method is increased by nearly 30% compared with other conventional methods, and the highest measured transfer rate is 1631 Mbytes/s on write and 1582 Mbytes/s on read, which reaches 84.4% of the theoretical maximum.

1 Gbit/s UDP/IP Offload Engine IP Core with PCIe Interface

A significant amount of processor power is required to handle packet processing in high speed data networks and taking it to the hardware helps processor to save its energy for other processes. In this study, an Offload Engine IP core that provides the hardware acceleration of UDP/IP protocol stack together with a few other network protocols is introduced. Furthermore, the IP core is equipped with PCI Express (PCIe) interface so as to communicate with applications running on a host PC. Consequently, a processor core deals with only the data processing, while the IP core takes care of the packet processing as per the protocol. The design and implementation of the IP core are verified and tested on an FPGA board; its area utilization and supported features are compared against several competitive designs from the literature. According to these results, the IP core is proved to be a useful one for those network applications that require a hardware-accelerated network protocol stack.

Efficient PCIe transmission for Multi-Channel video using dynamic splicing and conditional prefetching

PCI Express (PCIe) interface has been extensively used in high-speed digital systems for multimedia communication. With the migration of the video processing algorithms from host to embedded hardware, multi-channel video capturing systems will produce not only different channels of raw video data but also different types of auxiliary data, such as analyzed data and compressed stream. In order to display multi-channel video in real-time and explore the auxiliary data, conventional transmission strategies are no longer applicable, due to the fact that heterogeneous data will cause frequent interactions and lead to the waste of PCIe bandwidth. In this paper, an efficient PCIe transmission method for multi-channel video is presented. Firstly, for the transmission of multi-type video data, a dynamic splicing mechanism is proposed to combine the video analyzed data and the compressed stream with the raw video to avoid the individual transmission of the auxiliary data. Secondly, as the spliced data are from different channels, a conditional prefetching mechanism is employed to determine whether there exists any entire video frame in other channel buffers, so that multi-channel video data can be transmitted possibly at one time. Finally, in the host-side driver, direct kernel buffer access technique is used to improve the application I/O request packet (IRP) performance. And to ensure the transmission efficiency of the conditional prefetching, DMA circular queue buffer and timer self-feedback monitor techniques are designed to avoid the possible visit bursts and abnormal interruptions. Experimental results demonstrate that compared with the conventional methods, the proposed method reduces the interrupt interactions by 60%, increases the transmission channel number by 94%, and also increases the application IRP number by 54%. The peak transmission speed of PCIe is up to 155 MB/s, which can meet 7 channels 704 × 576 YUV raw video and its auxiliary data transmission requirements using one 1-lane PCIe endpoint.

A Feasible Architecture for ARM-Based Microserver Systems Considering Energy Efficiency

In this paper, we propose the architecture of the ARM-based server system and physically build the ARM-based server cluster board (SCB). Based on a real implementation, the efficiency of the microserver is evaluated to verify the benefits of the proposed scheme. In experiments, every SCB is equipped with four server-grade ARM quad-core processors for enterprise-class applications. The major difference between our work and other studies is that this paper tests the performance of the server-grade processors, whereas previous works use the cluster system formed by the embedded processors. The experiment results show that the SCB-based systems perform with lower power-consumption than the x86 systems. Since various types of cluster systems can be built with the SCB through either the PCI Express (PCIe) interface or gigabit Ethernet interface, the proposed design of the ARM server board and the systems can, therefore, be extensively applied. This physical implementation and measurement show that the proposed architecture can work well. The proposed energy-saving (i.e., green) server designs with low-power processors are suitable for relative applications in the coming era of Industry 4.0 and the Internet of Things.

Development and Practical Application of a Multifunctional Test Bench for Experimental Research of Precise Mechatronic Systems

Objectives: The aim of the project is to develop an experimental laboratory test bench for comprehensive practical research of various types of selective-invariant electromechanical systems as a part of their engineering design. Method: The experimental laboratory test bench implements the Rapid Control Prototyping technology permitting the creation and testing of new control algorithms in a short time. This technology makes it possible to rapidly check theoretical results and develop innovative technical solutions prepared for practical implementation in real production equipment. Findings: The developed test bench is implemented by using a personal computer with Windows operating system and MATLAB software package with Simulink simulation environment and a real-time library. It contains complete controlledvelocity electric drive with information signal sensors and a mechanical oscillation source of load torque on the electric drive shaft. Computer and electric drive are coordinated by means of a NI PCIe-6343 input-output circuit board with PCI Express interface. The application of a test bench for experimental research of adaptive-invariant mechatronic systems under close to real operating conditions is shown. To a large extent the results of the test bench research of mechatronic systems confirmed earlier results obtained by simulation and computing experiment methods. Improvements: The experimental laboratory test bench enables rapid modification of control devices structure and parameters, intensity and spectrum of load torque oscillations, composition of the electric drive being tested.

Ultrafast Streaming Camera Platform for Scientific Applications

X-ray computer tomography is a powerful method for nondestructive investigations in many fields. Three-dimensional images of internal structure are reconstructed from a sequence of two-dimensional projections. The polychromatic high density photon flux of modern synchrotron light sources offer hard X-ray imaging with spatio-temporal resolution up to the micrometer and micrometers range. Existing indirect X-ray image detection systems can be adapted for fast image acquisition by high-speed visible-light cameras. In this paper, we present a platform for custom high-speed CMOS cameras with embedded field-programmable gate array (FPGA) processing. This modular system is characterized by a high-throughput PCI Express (PCIe) interface and efficient communication blocks. It has been used to develop a novel architecture for a self-event trigger that increases the effective image frame rate and reduces the amount of received data. Thanks to a low-noise design, high frame rates in the kilohertz range, and high-throughput data transfer, this camera is well suited for ultrafast synchrotron-based X-ray radiography and tomography. The camera setup is accomplished by high-throughput Linux drivers and a seamless integration in our GPU computing framework.

Design of Data Transfer System Based on PCI Express Interface Applied in High-Speed Railway

To improve data transmission performance of the data acquisition card, a design of high-speed data transmission system is proposed in the thesis. Using FPGA of programmable logic devices, adopting Verilog HDL of hardware description language, the design of modularization and DMA transmission method is implemented in FPGA. Eventually the design implements the data transmission with high-speed through PCI Express interface. Through simulation and verification based on hardware system, this design is proved to be feasible and can satisfy the performance requirements of data transmission in the high-speed data acquisition card applied in high-speed railway communication. The design also has some value of application and reference for a universal data acquisition card.

HPP controller: a system controller for high performance computing

This paper introduces the design of a hyper parallel processing (HPP) controller, which is a system controller used in heterogeneous high performance computing systems. It connects several heterogeneous processors via HyperTransport (HT) interfaces, a commercial Infiniband HCA card with PCI-express interface, and a customized global synchronization network with self-defined high-speed interface. To accelerate intra-node communication and synchronization, global address space is supported and some dedicated hardware is integrated in the HPP controller to enable intra-node memory and shared I/O resources. On the prototype system with the HPP controller, evaluation results show that the proposed design achieves high communication efficiency, and obvious acceleration to synchronization operations.

ATCA Control System Hardware for the Plasma Vertical Stabilization in the JET Tokamak

A multi-input-multi-output controller for the plasma vertical stabilization was implemented and installed on the Joint European Torus tokamak. The system can attain a control-cycle time of approximately 30 ¿s using ×86 multi-core processors but targets 10 ¿s via Field Programmable Gate Array (FPGA) based processing. The hardware, complying with the Advanced Telecommunications Computing Architecture (ATCA) standard, was in-house designed and implemented to achieve the required performance and consists of: A total of 6 synchronized ATCA control boards, each one with 32 analog input channels which provide up to 192 galvanically-isolated channels, used mainly for magnetic measurements. Each board contains an FPGA, which performs digital signal processing and includes a PCI Express communications interface; An ATCA rear transition module, which comprises up to 8 galvanically-isolated analog output channels to control the fast radial field amplifier (±10 kV, ±2.5 kA). An optical link to digitally control the enhanced radial field amplifier (±12 kV, ±5 kA). Up to 8 EIA-485 digital inputs for timing and monitoring information; An ATCA processor blade with a quad-core processor, where the control algorithm is presently running, connected to the 6 ATCA control boards through the PCI Express interface. All FPGAs are interconnected by low-latency links via the ATCA full-mesh backplane, allowing all channel data to be available on each FPGA running an upcoming distributed control algorithm.

The Reconfigurable Hardware Accelerator for Searching Genome Patterns

The presented work concerns application of modern, complex programmable hardware devices in computation biology. The Xilinx Virtex 5 with PCI-Express interface has been used to implement the searching algorithm based on the dynamic programming idea. This algorithm works on very long chains of symbols, which come from reference pattern of the genome and we try to find some query sequences within those chains. The software solutions in the field are very limited and they need large time and space resources, so we have decided to implement the entire system on the reconfigurable hardware platform. We have investigated some variants of the implementation taking into account available resources, properties of the hardware and possibilities of parallel processing and increasing the overall system performance. The results we have obtained are very promising and show the dominance of the dedicated platforms over the general purpose PC-based systems.

A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> An 802.11n-draft-compliant 2<formula formulatype="inline"><tex Notation="TeX">$\,\times\,$</tex> </formula>2, 2-stream MIMO radio SoC, incorporating two dual-band RF transceivers, analog baseband filters, data converters, digital PHY and MAC, and a PCI Express interface, has been integrated in a standard 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu$</tex></formula>m digital CMOS technology with a die area of 36 mm<formula formulatype="inline"><tex Notation="TeX">$^{2}$</tex> </formula>. The receiver achieves noise figures of 4 dB and 6 dB, respectively, at 2.4 GHz and 5 GHz. The transmitter EVM for a 2-stream, 40-MHz-bandwidth 64-QAM OFDM signal is <formula formulatype="inline"><tex Notation="TeX">${-}$</tex> </formula>31 dBc at 2.4 GHz and <formula formulatype="inline"><tex Notation="TeX">${-}$</tex> </formula>8 dBm output power and <formula formulatype="inline"><tex Notation="TeX">${-}$</tex> </formula>31.5 dBc at 5 GHz and <formula formulatype="inline"><tex Notation="TeX">${-}$</tex> </formula>4 dBm output power. </para>

Parallel lines [co-processor chips

This paper deals with a design of hardware co-processor chips that can give computer architectures an extra boost to overcome CPU bottlenecks. Grid computing and other approaches are being tried in a bid to throw multiple processors at a growing range of standard IT challenges. PC vendors like Dell are shipping multi-processor with dual-core boxes. Chip maker AMD provide hardware co-processors based on FPGA which is a type of programmable logic device. FPGA cosists of three principal components such as registers, function generators (also known as look up tables or LUTS) and the FPGA clock. Each function generator contains of a set of logic gates. An FPGA can be configured as multiple virtual processors capable of functioning in parallel. In order to incorporate parallelism of hardware in a software application using FPGAs, the developer must partition the design between those tasks that will remain on the CPU and those that will run in hardware. To accelerate the system, the developer moves portions of the implementation to hardware connected to the CPU, such as an FPGA situated on a PCI, HyperTransport or PCI Express interface board.