PCB Image Research Articles

A method of PCB image registration based on the feature extraction of the Mark hole

A method of PCB image registration based on the feature extraction of the Mark hole

Image Recognition for PCB Soldering Platform Controlled by Embedded Microchip Based on Hopfield Neural Network

In the study, embedded BASIC Stamp 2 (BS2) microchip controller is used to design with Hopfield neural network (HNN) as the foundation of sample training, which applies for a soldering platform of mechanical vision and accomplishes PCB soldering positioning technology. The proposed system design method in this paper can be divided into two parts: 1) the control rules of RC servo motor is designed by BASIC, and 2) human-machine interface is established to acquire images for pre-processing via C++ Builder. For the method of system image recognition, HNN is employed to do PCB soldering recognition positioning. The system is verified by MATLAB and Simulink to set up the simulation of PCB image soldering positioning. The experiment proves that the proposed method improves the traditional low efficiency of PCB soldering technology, and to achieve the feasibility of PCB image positioning and promote the soldering quality.

Automated inspection of PCB components using a genetic algorithm template-matching approach

Automated inspection of surface mount PCB boards is a requirement to assure quality and to reduce manufacturing scrap costs and rework. This paper investigates methodologies for locating and identifying multiple objects in images used for surface mount device inspection. One of the main challenges for surface mount device inspection is component placement inspection. Component placement errors such as missing, misaligned or incorrectly rotated components are a major cause of defects and need to be detected before and after the solder reflow process. This paper focuses on automated object-recognition techniques for locating multiple objects using grey-model fitting for producing a generalised template for a set of components. The work uses the normalised cross correlation (NCC) template-matching approach and examines a method for constraining the search space to reduce computational calculations. The search for template positions has been performed exhaustively and by using a genetic algorithm. Experimental results using a typical PCB image are reported.

A Subpattern Level Inspection System for Printed Circuit Boards

The existing inspection systems are algorithmically slow and suffer from many drawbacks in meeting the inspection requirements of printed circuit board fabrication. The system presented in this paper can handle all of the defects simultaneously with the same approach and is significantly faster compared to the existing approaches. The system consists of three major phases: the first step is the segmentation of the golden PCB image into basic subpatterns, the second step is the learning phase, and the third and final step is the verification/inspection phase. The system presented here introduces the application of neural networks and fuzzy logic in printed circuit board inspection. The method is highly parallel and works at the subpattern level. Experimental results which demonstrate the effectiveness of the proposed algorithms are given.

A method for automatic inspection of printed circuit boards

An algorithm for automatic inspection of printed circuits is discussed which includes elements of the reference-comparison and the design-rule methods. First a directed graph, called the segment graph, is created from the image of the PCB. Construction of this graph involves comparison of adjacent rows, and hence each pixel is examined only twice in this construction. Feature points, including wire intersections, wire ends, and circuit defects, which uniquely represent the PCB image are extracted from the segment graph. In this way a very compact representation of the image is extracted. The feature points of the board being tested are then matched against the feature points from a reference board. Simultaneous with feature point extraction, the design-rule checking algorithm performs wire width and spacing inspection, and marks the unsatisfactory regions. Results of the algorithm implementation are demonstrated.