PCB Fabrication Research Articles

Integrated MEMS in package

PurposeThe purpose of this paper is to present the utilities of packaging and PCB fabrication processes for manufacturing micro electromechanical systems (MEMS) and its package for sensing and actuation applications.Design/methodology/approachA broad array of manufacturing approaches available in the packaging industry, including lamination, lithography, etching, electroforming, machining, bonding, etc. and a large number of available functional materials such as polymers, ceramics, metals, etc. were explored for producing functional microdevices with greater design freedom.FindingsGood quality MEMS devices can be manufactured using packaging style fabrication, particularly using stacks of laminates. Furthermore, such microdevices can be built with a high degree of integration, pre‐packaged, and at low cost.Research limitations/implicationsFurther manufacturing research work should be undertaken in collaboration with the PCB and packaging industries, which stand to benefit greatly by expanding their offerings beyond serving the semiconductor industry and developing their own integrated MEMS products.Originality/valueThe paper presents examples of basic packaging fabrication processes for producing 3‐D structures and free‐standing structures, and a new MEMS manufacturing paradigm to build micro‐electromechanical (MEMS) for biomedical, optical, and RF communication applications.

IPC technology trends study reveals changes in store for PCB fabricators and suppliers

IPC technology trends study reveals changes in store for PCB fabricators and suppliers

Nickel‐gold plating of copper PCB traces and signal losses

PurposeThe purpose of this paper is to discuss nickel gold plating of PCB traces and its adverse effects on signal integrity, and to explore the other key drivers in optimising yields and controlling PCB processes that impinge on signal integrity.Design/methodology/approachThe paper is a response to requests from PCB fabricators to explain why the losses on impedance controlled traces on PCBs were sometimes higher than expected.FindingsWhile nickel is acceptable on short lengths of pad to accommodate gold plating, plating the whole trace length is generally not good practice from a digital signal integrity perspective. In addition, with the fastest serial transmission rates in the 10 to 20 GHz region and long serial words in some situations designers may need to consider both the associated high and low frequency performance.Originality/valueWith the development of ultra high speed digital bus architectures, PCB fabricators will appreciate the need to add an understanding of the drivers of insertion loss (base material loss tangent data, foil roughness and copper cross sectional areas) to their existing experience of architectures with minimal losses.

The Planar Ultrawideband Modular Antenna (PUMA) Array

A fully planar ultrawideband phased array with wide scan and low cross-polarization performance is introduced. The array is based on Munk's implementation of the current sheet concept, but it employs a novel feeding scheme for the tightly coupled horizontal dipoles that enables simple PCB fabrication. This feeding eliminates the need for “cable organizers” and external baluns, and when combined with dual-offset dual-polarized lattice arrangements the array can be implemented in a modular, tile-based fashion. Simple physical explanations and circuit models are derived to explain the array's operation and guide the design process. The theory and insights are subsequently used to design an exemplary dual-polarized infinite array with 5:1 bandwidth and VSWR <; 2.1 at broadside, and cross-polarization ≈ -15 dB out to θ = 45° in the D- plane.

A current-matrix model for metallic and dielectric postwall waveguides

Waveguide structure integration in planar substrates for use in microwave components has received considerable attention in recent years. Waveguides with side walls consisting of cylindrical posts (postwall waveguides or PWWGs) are of interest, since they are compatible with standard PCB fabrication technology and exhibit low loss. In this paper we present an electromagnetic model for PWWG building blocks, whose characteristics are described entirely in terms of equivalent electric and magnetic surface currents at predefined port interfaces consistent with Lorentz’s reciprocity theorem. Introducing input and output surface currents, we determine the response of a block for a given port excitation. The expansion of the currents in terms of suitable bases results in a matrix that relates input and output currents. The scattering parameters of a building block are determined by expressing waveguide modes in terms of these bases. This facilitates the future integration of PWWG components in a microwave circuit simulator. We validate our model by comparing the results for simulated and measured uniform PWWGs implemented with metallic and dielectric posts.

AC Dielectrophoresis Using Elliptic Electrode Geometry

This paper presents negative AC dielectrophoretic investigations using elliptic electrode geometry. Simulations of the electric field gradient variation using various ratios of the semimajor and the semiminor axis were carried out to determine the optimum elliptic geometry for the dielectrophoretic electrokinetics of specimen in an assay with laminar (low Reynolds number) fluid flow. Experimental setup of the elliptic electrode assembly using PCB fabrication and electrokinetic accumulation of specimen in a dielectrophoretic cage is also being reported. Using an actuating signal between 1 kHz and 1 MHz, successful trapping of 45 μm polystyrene beads suspended in distilled water was demonstrated due to negative dielectrophoresis near 100 kHz using the novel elliptic electrode.

Next Generation High Dk, Low Df Organic Laminate for RF Modules and High Frequency Applications

In this paper, we present a novel high density high performance ultra-thin organic laminate, X-R-1, with low cost standard PCB fabrication processes for RF and high frequency applications. The X-R-1 substrate, developed at Zeon Corporation is a new generation halogen-free high dielectric constant (Dk) and low loss tangent (Df) dielectric laminate material. Its dielectric constant is 6.5–6.7 in the range of 1–20GHz, similar to typical LTCC substrates but larger than most organic materials such as LCP, PTFE and Epoxy based materials. Its dielectric loss tangent is 0.003, similar to that of LTCC, LCP and PTFE but much lower than epoxy based materials. The thicknesses of the core used in this study are 50um. The clad copper on both sides is a 12um thick profile-free copper foil which provides extremely smooth surface. Microminiaturization of RF devices can be achieved by the combination of high Dk and ultra-thin substrate. The combination of low Df and smooth surface leads to RF and high frequency signals having minimum propagation loss. The material is suitable for mechanical and laser through hole drilling and fully compatible with the low cost standard PCB facilities and processes. Because of the smooth surface, 25um very fine copper lines and spaces were achieved by wet etching process. Copper filled through holes with 40um diameter drilled by CO2 laser have been demonstrated. Panel size of 6″×6″ test vehicles with RF filters and transmission lines was fabricated and measured. Test data on the filters at 2.4GHz and 5GHz has been presented in this paper. This high Dk and low Df laminate with standard PCB processes provides a low cost organic platform for RF and high frequency circuit applications.

REACH: implications of Europe's new chemicals policy for PCB fabricators

Purpose – The aim of the paper is to provide PCB fabricators with a top‐level understanding of the EC regulation for the registration, evaluation, restriction and authorization of chemicals (REACH) and to detail the implications for the sector now, and in the years ahead.

Substrate Integrated Waveguides (SIWs) in a Flexible Printed Circuit Board for Millimeter-Wave Applications

Substrate integrated waveguides (SIWs) are presented and demonstrated in a flexible printed circuit board (flex PCB) for application in the 77-81 GHz range. The vertical walls of the SIWs presented in this paper consist of multiple electrodeposited metallic wires. The diameters of these wires and the spacing between them are on the order of hundreds of nanometers. Hence, the walls can be seen as continuous metallic walls, and the leakage losses through them become negligible. In turn, the SIWs presented in this paper can operate at higher frequencies compared with previously presented structures that are realized with PCB fabrication processes. The attenuation of the SIWs is comparable to that of microstrip lines on the same sample. The SIWs are successfully demonstrated in a SIW-based slot antenna. The antenna gain along the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">z</i> -axis (normal-to-plane) was found to be around 2.8 dBi at 78 GHz which is in agreement with the simulated values. [2008-0047]

Half Mode Substrate Integrated Waveguide (HMSIW) Directional Filter

A double-loop directional filter is described and realized in this work by using a novel guided-wave structure called half mode substrate integrated waveguide (HMSIW), which retains the attractive performances of substrate integrated waveguide (SIW) with a nearly half reduction in size compared to the original SIW version. The demonstrated filter is designed at 12 GHz with less than 3.2 dB insertion loss for a 250-MHz bandwidth, and the minimum insertion loss is 1.5 dB. It presents low insertion loss, high power capacity in planar compact configuration with a standard PCB fabrication process.

The influence of temperature on the efficiency of electroplating from various ionic liquids

PurposeTo study the influence of temperature on the electroplating efficiency of various metals from ionic liquids.Design/methodology/approachCopper, silver, nickel and tin, in the form of metal chlorides, were dissolved in a number of ionic liquids. After using cyclic voltammetry to establish an optimum current density to electroplate each metal, basic electroplating processes were carried out at varying temperatures onto stainless steel. The mass deposited was used to calculate the efficiency of the process.FindingsIt was found that, generally, temperature influences the efficiency of electroplating from ionic solutions. While some solutions showed continuing improvements in plating efficiency as the temperature increased, others exhibited an optimum plating temperature. One solution examined showed the need for a certain temperature to be reached in order to induce the formation of a different metal complex before electroplating was achievable.Research limitations/implicationsThe low currents used in the electroplating experiments have a large influence on the errors in the efficiency, especially at lower temperatures.Originality/valueConsideration of the use of ionic liquids in electroplating for printed circuit board manufacturing is relatively new. Knowledge of the strengths and weaknesses of metals in various ionic liquids will allow potential plating solutions to be better understood in terms of their suitability for PCB fabrication.

ＩＴとソフトマテリアル ソルダーレジストの構成と要求特性

A recent trend of increasing circuit density and functions of PCB diversifies demands for a solder resist mask. When the solder resist mask was introduced, its demanded property was simply to prevent solder bridge on PCB. However, a photo-imageable solder resist mask, which correspond to high circuit density PCB design was developed to overcome the limitation of the solder resist mask's resolution made by silkscreen printing method. Now days, the photo-imageable solder resist mask that is contact UV exposure and alkaline develop type is a most common solder resist mask for PCB fabrication. The photo-imageable solder resist mask is used in various PCBs e. g. motherboards on PC or TV, IC package (BGA and CSP) substrates, flexible PCBs, and etc. Since these PCBs are made for specialized purposes and functions, demands for solder resist mask for these PCBs become more specific in features and performances.In this paper, basic composition of the photo-imageable solder resist mask and its curing system, features and performance to cope with environmental issues that are halogen free and lead free, UV exposure types, and difference of liquid type and dry film type solder masks are discussed.

SAVIA, an advanced multi‐layer parallel lamination technique for high density, high performance printed circuit boards

PurposeTo review a newly developed PCB fabrication process based on a parallel lamination technique.Design/methodology/approachThis paper has been written to introduce the SAVIA process, a new parallel lamination technique for PCB fabrication. The basic concept of the SAVIA process has been described along with the individual process steps and the reliability issues. The advantages of SAVIA process have been also discussed in both economical and technological aspects.FindingsIt was found that the parallel lamination technique, a key process for SAVIA, was not only highly flexible and reliable but also a cost‐effective fabrication method for high performance PCB. With the SAVIA process, manufacturing lead‐times can be substantially reduced due to the nature of the parallel processing. It was also confirmed that a highly reliable metal alloy interconnection was created between the core and the adhesive layers during the lamination process. The formed metal alloy contacts showed excellent electrical and physical characteristics. The between layers was precise.Originality/valueThe value of this paper is to introduce a novel PCB fabrication process based on a parallel lamination technique that is superior to conventional build‐up processes from both technological and economical viewpoints. By applying a parallel lamination technique, it is expected that fabrication costs can be lowered due to reductions in manufacturing lead‐time.

Characterization of PCB plated‐through‐hole reliability using statistical analysis

Various test methods are used to characterize PCB plated‐through‐hole reliability. One such method is the interconnect stress test. The results from this test are often used to qualify PCB materials and/or fabricators. This paper will discuss how certain statistical analysis techniques may be used to decipher the results, and predict capabilities of PCB materials and/or processes.

An introduction to high performance laminates and the importance of using optimised chemical processes in PCB fabrication

With the ever increasing demands for high performance electronic devices there is a need for circuit board laminates that have enhanced properties when compared to conventional materials such as the widely used epoxide‐based FR4 laminates. Equipment manufacturers require boards with better mechanical stability and improved electrical characteristics. At the same time, new environmental legislation is set to drive electronics assembly temperatures much higher as manufacturers start to use lead‐free soldering processes. The legislation is also raising questions about the long‐term viability of brominated resins as the basis for imparting flame retardancy to laminates. Fortunately, laminate manufacturers have responded to these challenges by developing and introducing a wide range of new laminates that address these issues. This paper describes some of these challenges and gives an introduction to the new high performance laminates that are finding increasing use. It also highlights the need for chemical processes used in the manufacture of interconnects with laminates to be specifically optimised for the chosen substrate material.

Sustainable technologies for the regeneration of acidic tin stripping solutions used in PCB fabrication

Electroplated tin deposits are used as etch resists during the processing of printed circuit boards. The tin coating protects the copper tracks during etching but is subsequently removed (stripped) to expose the defined copper circuitry. The commonly used stripping solutions are based on nitric acid and after use they represent a very acidic waste product with a high metal content. The disposal of these spent strippers is typically via off‐site neutralisation and precipitation followed by subsequent landfill. This is clearly a non‐sustainable waste of valuable resources and a practice that is increasingly undesirable as environmental legislation becomes more stringent. This paper outlines the results of a scoping study carried out into current industry practices for tin stripping and details of components of a potential integrated treatment system for these stripping solutions. Individual technologies for such an integrated system incorporate the recovery of the tin oxide by filtration, the concentration and reuse of nitric acid solutions by diffusion dialysis and the reclamation of other metals, i.e. copper by electrowinning.

Frontline announces industry-first integrated engineering suite for PCB fabrication

Frontline announces industry-first integrated engineering suite for PCB fabrication

Multek expands PCB fabrication capabilities in Guadalajara, Mexico

Multek expands PCB fabrication capabilities in Guadalajara, Mexico

Study of Ni3P growth due to solder reaction-assisted crystallization of electroless Ni-P metallization

Nickel (Ni) has been widely used for advanced electronic applications to replace Cu or act as a diffusionbarrier layer in the conventional Au/Cu metallization because of a slower intermetallic compound (IMC) formation rate [1] and a relatively low diffusion rate through Au and Cu [2, 3]. Amorphous electroless nickel-phosphorus (Ni-P) has attracted much interest and widespread uses in the PCB fabrication and UBM for flip chip technology because it offers a lower cost alternative to a more expensive physical Ni deposition methods, good corrosion resistivity, strong adhesion, and good solder wetting [4–6]. It has been found that the amorphous Ni-P alloy will only undergo a selfcrystalline transformation to Ni and Ni3P at temperature above 300 ◦C [7]. Recently, Jang et al. [5] have found that the solder reaction will assist crystallization of electroless Ni-P UBM in flip chip packages even if the reflow temperature is well below the self-crystallization temperature. However, the details of the Ni3P growth in electroless Ni-P are still unclear. In this letter, some results of Ni3P growth in electroless Ni-P with chemical composition of Ni77P23 are presented and then compared with those results obtained in Ref. [5] in which the electroless Ni-P has a composition of Ni85P15. Electroless Ni-P was deposited on Cu pad substrate and a gold (Au) flash was deposited on the top of that electroless Ni-P in order to avoid oxidation of nickel surface. Eutectic Pb-Sn solder balls were placed on the prefluxed Au/Ni-P/Cu pad substrates and reflowed at temperature of 220 ◦C for different annealing time from 0.5 to 90 min. For interfacial microstructural examination, samples were mounted in epoxy and then sectioned using a slow speed diamond saw. The crosssectioned samples were ground, polished and etched with 10% conc. HCl+ 90% water. The chemical composition of electroless Ni-P was found to be Ni77P23 by using Philips XL 40 FEG scanning electron microscope (SEM) equipped with energy dispersive X-ray analysis (EDX). The structure of electroless Ni-P was confirmed to be amorphous by X-ray diffraction (XRD). Fig. 1 shows the SEM image of cross-sectioned sample after reflow at 220 ◦C for 0.5 min. The IMC layer is confirmed to be Ni3Sn4 by XRD and EDX analyses. It is found that both chunky-type and needle-type Ni3Sn4 IMCs are present. It is interesting to note that there is a thin dark layer between the Ni3Sn4 IMC and the electroless Ni-P. This dark layer is confirmed to be Ni3P, which is consistent with the findings of Jang et al. [5]. Fig. 2 shows the relationship between the thickness of Ni3P and the annealing time at 220 ◦C. During the first 15 min of annealing, the Ni3P grows rapidly due to the solder reaction-assisted crystallization of electroless Ni-P. It is found that the thickness of Ni3P is linearly proportional to the square root of the annealing time during the first 15 min. This means that the Ni3P growth is controlled by a diffusion process during the first 15 min of annealing. However, it is interesting to note that the growth of Ni3P is stopped or even dropped after the first 15 min of annealing. For the sake of comparison, Fig. 2 also shows the results of Ni3P thickness growth in electroless Ni85P15 [5]. It shows that the Ni3P layer in electroless Ni85P15 continued to grow throughout the entire annealing range from 0 to 40 min. If we assume all the Ni and P elements in electroless Ni-P react into Ni3P and Ni3Sn4 without any loss into the solder, a general solder reaction-assisted crystallization equation in electroless NiaPb will be as follows:

North American comments; a difficult year for PCB fabricators

North American comments; a difficult year for PCB fabricators