Pb-free Solder Bumps Research Articles

Size Effect on the Electromigration Characteristics of Flip Chip Pb-free Solder Bumps

Size Effect on the Electromigration Characteristics of Flip Chip Pb-free Solder Bumps

Analysis of continuous recrystallization (sub)grain rotation behavior in Pb-free solder bumps under a 0.1 µm/s shear rate

Localized recrystallization occurs in Pb-free solder joints under thermomechanical fatigue stress (thermal fatigue). Scanning electronic microscopy and electron backscattered diffraction were used to obtain the microstructures and grain orientations, respectively, of Sn3.5Ag solder bumps after shear testing. At room temperature, recovery and continuous recrystallization tend to occur at the near-pad interface and near-shear edge regions of the solder bumps under shear stress. A (sub)grain rotation mechanism dominates the recrystallized (sub)grains, distinguishing them from the initial orientations. Additionally, the rotation axis and angle were investigated to further elucidate the recrystallized (sub)grain rotation behavior of Pb-free solder bumps. The results show the formation of a single rotation axis between a (sub)grain and its neighboring (sub)grain during recrystallization, indicating a relationship between continuous recrystallization and the Sn slip systems in Pb-free solder alloys.

Effects of PCB surface finishes on the Mechanical and Electrical Reliabilities of Sn-0.7Cu Pb-free Solder Bump

Effects of PCB surface finishes on the Mechanical and Electrical Reliabilities of Sn-0.7Cu Pb-free Solder Bump

Simulation and measurement of the flip chip solder bumps with a Cu-plated plastic core

With the aim to miniaturize and to reduce the cost, the increasing demand, regarding to advanced 3D-packages as well as high performance applications, accelerates the development of 3D-silicon integrated circuits. The trend to smaller and lighter electronics has highlighted many efforts towards size reduction and increased performance in electronic products. The radio frequency (RF) performances are limited by parasitic effects due to the resistor–inductor–capacitor (RLC) network, between the wire bond connections from the dies to the lead frame. The use of flip-chip bonding technology for very fine pitch packaging allows high integration and limits parasitic inductances. Electromigration (EM) and thermomigration (TM) may have serious reliability issues for fine-pitch Pb-free solder bumps in the flip-chip technology used in consumer electronic products. A possibility to extend the reliability is the use of plastic ball in the solder bumps. Bumps containing a plastic solder balls have an excellent reliability. Using a plastic ball with a low Young modulus, the solder hardness is moderated and the stress on a ball is relaxed. Due to this, the stress does not concentrate on the solder joint which prolongs the lifetime. In this investigation, the thermal–electrical–mechanical coupling of electromigration on bumps containing a plastic solder is studied.

Electromigration kinetics and critical current of Pb-free interconnects

Electromigration kinetics of Pb-free solder bump interconnects have been studied using a single bump parameter sweep technique. By removing bump to bump variations in structure, texture, and composition, the single bump sweep technique has provided both activation energy and power exponents that reflect atomic migration and interface reactions with fewer samples, shorter stress time, and better statistics than standard failure testing procedures. Contact metallurgies based on Cu and Ni have been studied. Critical current, which corresponds to the Blech limit, was found to exist in the Ni metallurgy, but not in the Cu metallurgy. A temperature dependence of critical current was also observed.

Effects of PCB ENIG and OSP Surface Finishes on the Electromigration Reliability and Shear Strength of Sn-3.5Ag PB-Free Solder Bump

The effects of printed circuit board electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) surface finishes on the electromigration reliability and shear strength of Sn-3.5Ag Pb-free solder bump were systematically investigated. In-situ annealing tests were performed in a scanning electron microscope chamber at 130, 150, and <TEX>$170^{\circ}C$</TEX> in order to investigate the growth kinetics of intermetallic compound (IMC). Electromigration lifetime and failure modes were investigated at <TEX>$150^{\circ}C$</TEX> and <TEX>$1.5{\times}10^5A/cm^2$</TEX>, while ball shear tests and failure mode analysis were conducted under the high-speed conditions from 10 mm/s to 3000 mm/s. The activation energy of ENIG and OSP surface finishes during annealing were evaluated as 0.84 eV and 0.94 eV, respectively. The solder bumps with ENIG surface finish showed longer electromigration lifetime than OSP surface finish. Shear strengths between ENIG and OSP were similar, and the shear energies decreased with increasing shear speed. Failure analysis showed that electrical and mechanical reliabilities were very closely related to the interfacial IMC stabilities.

Package Technology Selection of 28nm High Power FPGA with Pb-Free Solder Bumps: Flip Chip Molded BGA (FCMBGA) versus Traditional Flip Chip Bare Die Package

Selecting the optimal flip-chip package technology for the next generation 28nm FPGA is critical not only to meet reliability benchmarks for Pb-free bumps, but also in meeting the field-use environment requirements for high power devices. Component level reliability testing was conducted on three separate package types: Bare die flip chip BGA (FCBGA), flip chip molded BGA with capillary underfill (FCMBGA w/CUF), and flip chip molded BGA with molded underfill. (FCMBGA). Testing was conducted independently at two separate sites. Testing included moisture resistance testing (MRT), temperature cycle (JESD22-A104 Condition Level B), and a hybrid test combining 100 hours of unbiased HAST (JESD22-A118A) with temperature cycling. Reliability monitoring was conducted through multiple means including electrical testing for circuit continuity, CSAM imaging at frequent read points to monitor silicon integrity and underfill adhesion performance, cross-sections for the inspection of bump crack propagation, and FIB analysis of the UBM structure after test completion. In addition to reliability testing of three flip chip BGA platforms, other usage factors were considered. These include package specific design rule flexibility for passive placement and future generation packaging requirements. The results of the evaluation demonstrated that bump integrity remained strong for all three package types – showing no cracks after 1,500 temperature cycles, hybrid testing, or MRT. Ultimately, the FCMBGA with molded underfill was selected based on the quality of the bumps after testing, the design rule flexibility for capacitor placement, and improved component protection from mechanical damage.

Formation Mechanisms of Sn Oxide Films on Probe Pins Contacted with Pb-Free Solder Bumps

In semiconductor manufacturing, the circuit integrity of packaged BGA devices is tested by measuring electrical resistance using test sockets. Test sockets have been reported to often fail earlier than the expected life-time due to high contact resistance. This has been attributed to the formation of Sn oxide films on the Au coating layer of the probe pins loaded on the socket. Similar to contact failure, and known as "fretting", this process widely occurs between two conductive surfaces due to the continual rupture and accumulation of oxide films. However, the failure mechanism at the probe pin differs from fretting. In this study, the microstructural processes and formation mechanisms of Sn oxide films developed on the probe pin surface were investigated. Failure analysis was conducted mainly by FIB-FESEM observations, along with EDX, AES, and XRD analyses. Soft and fresh Sn was found to be transferred repeatedly from the solder bump to the Au surface of the probe pins; it was then instantly oxidized to SnO. The <TEX>$SnO_2$</TEX> phase is a more stable natural oxide, but SnO has been proved to grow on Sn thin film at low temperature (< <TEX>$150^{\circ}C$</TEX>). Further oxidation to <TEX>$SnO_2$</TEX> is thought to be limited to 30%. The SnO film grew layer by layer up to 571 nm after testing of 50,500 cycles (1 nm/100 cycle). This resulted in the increase of contact resistance and thus of signal delay between the probe pin and the solder bump.

Estimation and visualization of the fatigue life of Pb-free SAC solder bump joints under thermal cycling

A method for estimating the fatigue life of Pb-free solder (Sn–3.0Ag–0.5Cu) bump joints under thermal cycling is described. The test specimens were 4, 6 and 8mm chip size packages mounted on printed circuit boards. To develop a semi-analytical model for estimating the thermal fatigue life, thermal cycle tests were carried out on the test specimens and the thermal fatigue life obtained experimentally was compared with the corresponding result from nonlinear, elastic–plastic finite element analysis. It was found that the chip size affected the thermal fatigue life and the strain accumulated in the solder bumps during thermal cycling. This was due to the difference in mechanical boundary conditions around the Si chip. Based on the Coffin–Manson law, an equation for estimating the thermal fatigue life was derived and the predicted fatigue life for various chip sizes and under different rises in temperature were found to be in good agreement with the experimental results. Moreover, a measurable parameter that correlates with the accumulated strain in the solder bumps was introduced for estimating the thermal fatigue life of the test specimens.

Effect of Interfacial Microstructures on the Bonding Strength of Sn–3.0Ag–0.5Cu Pb-Free Solder Bump

The effect of interfacial microstructures on the bonding strength of Sn–3.0Ag–0.5Cu Pb-free solder bumps with respect to the loading speed, annealing time, and surface finish was investigated. The shear strength increased and the ductility decreased with increasing shear speed, primarily because of the time-independent plastic hardening and time-dependent strain-rate sensitivity of the solder alloy. The shear strength and toughness decreased for all surface finishes under the high-speed shear test of 500 mm/s as a result of increasing intermetallic compound (IMC) growth and pad interface weakness associated with increased annealing time. The immersion Sn and organic solderability preservative (OSP) finishes showed lower shear strength compared to the electroless nickel immersion gold (ENIG) finish. With increasing annealing time, the ENIG finish exhibited the pad open fracture mode, whereas the immersion Sn and OSP finishes exhibited the brittle fracture mode. In addition, the shear strength of the solder joints was correlated with each fracture mode.

Effect of Interfacial Microstructures on the Bonding Strength of Sn–3.0Ag–0.5Cu Pb-Free Solder Bump

Effect of Interfacial Microstructures on the Bonding Strength of Sn–3.0Ag–0.5Cu Pb-Free Solder Bump

Process and Reliability of Embedded Micro-Wafer-Level Package (EMWLP) Using Low Cure Temperature Dielectric Material

In this paper, we present the evaluation results of low cure temperature (less than 200°C) dielectric materials (LCTDMs) in terms of processability and adhesion to silicon nitride and mold compound substrates. The results showed that the LCTDMs have good adhesion to the above substrates. Integration of thin-film passives such as inductors, capacitors, and band-pass filters were also demonstrated on mold compound wafer platform using electroplated copper (Cu) and LCTDM. Thin-film passives fabricated on the mold compound platform using LCTDM showed better performance by two times when compared to the passives fabricated on a high-resistivity silicon wafer. Reliability test vehicles of multichip embedded micro-wafer-level package (EMWLP) were fabricated using Cu redistribution line (RDL), LCTDM, and electroplated Cu under bump metallization with lead-free (Pb-free) solder bump interconnects. Test vehicles were subjected to various package-level and board-level reliability tests as per the JEDEC standards, and failure analysis was carried out after reliability tests. EMWLP with LCTDM passed package-level reliability tests such as unbiased highly accelerated stress test, thermal cycling (TC), and moisture sensitivity test level 3. Test vehicles with underfill passed board-level TC and drop tests. A complete description of dielectric material evaluation for EMWLP, process development of thin-film passives fabrication, and multilayer RDL integration on reconfigured mold compound wafer and its reliability results are discussed.

205 車載用電子部品に用いられる鉛フリーはんだ接合部の熱疲労寿命予測と延命手法(学生賞I,一般講演)

205 車載用電子部品に用いられる鉛フリーはんだ接合部の熱疲労寿命予測と延命手法(学生賞I,一般講演)

Development of Large Die Fine-Pitch Cu/Low-$k$ FCBGA Package With Through Silicon via (TSV) Interposer

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> test chip on flip chip ball grid array (FCBGA) package. The Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

Electromigration and Thermomigration in Pb-Free Flip-Chip Solder Joints

Pb-free solders have replaced Pb-containing SnPb solders in the electronic packaging industry due to environmental concerns. Both electromigration (EM) and thermomigration (TM) have serious reliability issues for fine-pitch Pb-free solder bumps in the flip-chip technology used in consumer electronic products. We review the unique features of EM and TM in flip-chip solder bumps, emphasizing the effects of current crowding and Joule heating. In addition, the challenges to a better understanding of EM and TM in Pb-free solders are discussed. For example, the anisotropic nature of Sn microstructure in Pb-free solders can enhance the dissolution rates of Ni and Cu in solders driven by EM and TM.

Solder Bump Electromigration and CPI Challenges in Low-k Devices

Understanding and managing both chip-to-package interaction (CPI) and solder bump electromigration (EM) in new designs is becoming an increasing challenge for flip chip plastic ball grid array (FCPBGA) packaging. Requirements for state-of-the-art device technologies drive smaller features, higher power and RoHS compliance (Pb-free product). It will be shown that the optimal attributes for Pb-free solder bump EM performance often are diametrically opposed to the design parameters that improve CPI robustness in structures comprised of low-k dielectric materials.

Reliability Evalution for Copper/Low-k-Structures Based on Experimental and Numerical Methods

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Bump shear is widely used to characterize the interfacial strength of Cu/low-<formula formulatype="inline"> <tex Notation="TeX">$k$</tex></formula> structures. In this paper, the blanket low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex> </formula> structure was used to evaluate the reliability and strength of Cu/low-<formula formulatype="inline"><tex Notation="TeX"> $k$</tex></formula> structures based on experiment and finite-element modeling technique. The objectives of this paper are to determine the critical stress parameters for low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> interfaces with different low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structures, to understand the failure mechanism, and to improve low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structure reliability by optimizing some parameters. In this paper, a comprehensive parametric study was carried out. Such parameters include the effect of three different low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structures, high-Pb solder bump versus Pb-free solder bump, different underbump metallization (UBM) thicknesses, barrier-layer material elastic modulus, and shear ram height on low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structure reliability. The simulation findings can be summarized as follows. The critical stress decreases with the number of layers of low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structure. An Sn–Ag solder bump results in a higher shear force and stress than a high-Pb solder bump. Reducing the UBM thickness can help improve the low- <formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structure reliability. </para>

Reliability Evaluation for Copper/Low-$k$ Structures Based on Experimental and Numerical Methods

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Bump shear is widely used to characterize the interfacial strength of Cu/low-<formula formulatype="inline"> <tex Notation="TeX">$k$</tex></formula> structures. In this paper, the blanket low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex> </formula> structure was used to evaluate the reliability and strength of Cu/low-<formula formulatype="inline"><tex Notation="TeX"> $k$</tex></formula> structures based on experiment and finite-element modeling technique. The objectives of this paper are to determine the critical stress parameters for low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> interfaces with different low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structures, to understand the failure mechanism, and to improve low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structure reliability by optimizing some parameters. In this paper, a comprehensive parametric study was carried out. Such parameters include the effect of three different low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structures, high-Pb solder bump versus Pb-free solder bump, different underbump metallization (UBM) thicknesses, barrier-layer material elastic modulus, and shear ram height on low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structure reliability. The simulation findings can be summarized as follows. The critical stress decreases with the number of layers of low-<formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structure. An Sn–Ag solder bump results in a higher shear force and stress than a high-Pb solder bump. Reducing the UBM thickness can help improve the low- <formula formulatype="inline"><tex Notation="TeX">$k$</tex></formula> structure reliability. </para>

Precise Quantitative Evaluation of Nano-Ordered Intermetallic Compounds in Sn-3.0Ag-0.5Cu Lead-Free Solder Bump by Using TEM

The growth behaviour of the intermetallic compounds (IMCs) in Pb-free solder bump is investigated. The Pb-free micro-bump, Sn-50%Bi, was fabricated by binary electroplating for flip-chip bond. The diameter of the bump is about 506m and the height is about 60 6m. In order to increase the reliability of the bonding, it is necessary to protect the growth of the IMCs in interface between Cu pad and the solder bump. For control of IMCs growth, SiC particles were distributed in the micro-solder bump during electroplating. The thickness of the IMCs in the interface was estimated by FE-SEM, EDS, XRF and TEM. From the results, The IMCs were found as Cu6Sn5 and Cu3Sn. The thickness of the IMCs decreases with increase the amount of SiC particles until 4 g/cm2. The one candidate of the reasons is that the SiC particles could decrease the area which be reacted between the solder and Cu layer. And another candidate is that the particle can make to difficult inter-diffusion within the interface.

Study of the undercooling of Pb-free, flip-chip solder bumps and in situ observation of solidification process

The undercooling of flip-chip Pb-free solder bumps was investigated by differential scanning calorimetry (DSC) to understand the effects of solder composition and volume, with and without the presence of an under bump metallurgy (UBM). A large amount of the undercooling (as large as 90 °C) was observed with Sn-rich, flip-chip size solder bumps sitting in a glass mold, while the corresponding undercooling was significantly reduced in the presence of a wettable UBM surface. In addition, the solidification of an array of individual solder bumps was monitored in situ by a video imaging technique during both heating-up and cooling-down cycles. Data obtained by the optical imaging method were used to complement the DSC thermal measurements. A random solidification of the array of bumps was demonstrated during cooling, which also spans a wide temperature range of 40–80 °C. In contrast, an almost simultaneous melting of the bumps was observed during heating.