Processor For Pattern Recognition Research Articles

Quantum face recognition protocol with ghost imaging

Face recognition is one of the most ubiquitous examples of pattern recognition in machine learning, with numerous applications in security, access control, and law enforcement, among many others. Pattern recognition with classical algorithms requires significant computational resources, especially when dealing with high-resolution images in an extensive database. Quantum algorithms have been shown to improve the efficiency and speed of many computational tasks, and as such, they could also potentially improve the complexity of the face recognition process. Here, we propose a quantum machine learning algorithm for pattern recognition based on quantum principal component analysis, and quantum independent component analysis. A novel quantum algorithm for finding dissimilarity in the faces based on the computation of trace and determinant of a matrix (image) is also proposed. The overall complexity of our pattern recognition algorithm is O(N,log N)—N is the image dimension. As an input to these pattern recognition algorithms, we consider experimental images obtained from quantum imaging techniques with correlated photons, e.g. “interaction-free” imaging or “ghost” imaging. Interfacing these imaging techniques with our quantum pattern recognition processor provides input images that possess a better signal-to-noise ratio, lower exposures, and higher resolution, thus speeding up the machine learning process further. Our fully quantum pattern recognition system with quantum algorithm and quantum inputs promises a much-improved image acquisition and identification system with potential applications extending beyond face recognition, e.g., in medical imaging for diagnosing sensitive tissues or biology for protein identification.

A design of EEGNet‐based inference processor for pattern recognition of EEG using FPGA

AbstractIn recent years, brain‐machine interface (BMI) is attracting attention. BMI is a technology that enables machine operation using biological signals such as EEG. For further advancement of BMI technology, there is a need for advanced BMI devices. Therefore, the purpose of this study is development of BMI hardware specialized for handling EEG as an interface for human adaptive mechatronics (HAM) that know human's state and operate according to the state. As one of the examinations, we are constructing a pattern recognition processor for EEG in real time on Field Programmable Gate Array (FPGA), which is an LSI that can reconfigure the processor. This paper reports on the designed EEGNet processor and the result of logic circuit simulation and implementation.

A Design of EEGNet based Inference Processor for Pattern Recognition of EEG using FPGA

A Design of EEGNet based Inference Processor for Pattern Recognition of EEG using FPGA

Performance Evaluation of FPGA based Processor for Pattern Recognition of EEG

Performance Evaluation of FPGA based Processor for Pattern Recognition of EEG

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called “pattern”. Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

A VLSI Processor for Fast Track Finding Based on Content Addressable Memories

The authors describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, searching for matches on 96-bit wide patterns, in just a few 40-MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at the Collider Detector experiment at Fermilab (CDF) using a standard-cell VLSI design methodology. This approach provides excellent pattern density, while sparing many of the complexities and risks associated to a full-custom design. The cost/performance ratio is better by well more than one order of magnitude than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. They look forward to sharing this technology

Optimal χ^2 filtering method and application to targets and backgrounds with random correlated gray levels

We describe a pattern recognition processor based on a new optimal x(2) filtering method that is designed to localize a target with unknown gray levels appearing on a random background. This processor consists of preprocessing of the analyzed image followed by correlations with binary masks.

Optimal detection of a target with random gray levels on a spatially disjoint background noise

We describe a pattern-recognition processor that is optimal for detection and location of a target with white Gaussian random gray levels on a white random spatially disjoint background. We show that this algorithm consists of correlations of the silhouette of the reference object with preprocessed versions of the scene image. This result can provide a theoretical basis for pattern-recognition techniques that use nonlinear preprocessing of images before correlation.

Basic properties of nonlinear global filtering techniques and optimal discriminant solutions

The basic properties of nonlinear global filtering techniques are analyzed. A nonlinear processor for pattern recognition that is optimum in terms of discrimination and that is tolerant of variations of the object to be recognized is presented. We compare this processor with power-law and nonlinear joint transform correlators.

Nonlinear joint-transform correlation: an optimal solution for adaptive image discrimination and input noise robustness

We develop a processor for pattern recognition that is optimum in terms of discrimination and is tolerant to variations of the object to be recognized. This optimum processor is found to be adaptive nonlinear joint-transform correlator.

Artificial Neural Networks and Their Application to Weapons

ABSTRACTComplex processing algorithms associated with requirements for real‐time target detection, acquisition and recognition have far outdistanced our ability to package the necessary processing power into real‐time weapon‐sized hardware. Weapon developers need new, radically different, approaches to solve these difficult weapon signal processing problems. Artificial neural networks (ANN) is one of the new, radically different, signal processing approaches that is currently receiving much attention for weapon applications. The human brain is a powerful image and pattern recognition processor whose basic processing element is the neuron. Synapses are the weighted interconnections between neurons that permit learning and communication between the neurons. Artificial neural network technology attempts to mathematically and/or electrically model neurons and synapses and then interconnect these models in architectures suitable for signal processing tasks.ANN technology is particularly applicable to pattern recognition, speech recognition, machine vision, robotics, and optimization signal processing tasks. Specific military applications include missile seekers, missile fuzing, sonar target discrimination, automatic target recognition, and autopilots. Two unique characteristics of ANN processors are that they are non‐linear processors and that they are trained, not programmed, to accomplish processing tasks in a manner analogous to the way the human brain learns. Learning is achieved by modifying the synaptic weights of each artificial neuron until the final desired system processing response is achieved.Several years ago the Naval Weapons Center (NavWpnCen) identified ANN technology as a high risk‐high payoff approach to missile signal processing requirements and initiated several research and development efforts in this area. One result of this work is the new 80170NW ANN analog VLSI chip produced by Intel Inc. Another is the current Missileborne Integrated Neural Network Demonstration (MINND) Advanced Technology Demonstration (ATD) project to develop a hybrid analog/digital artificial neural computer for real‐time processing of data from imaging missile seekers. The neural computer will use several Intel chips interconnected in a flexible architecture, which is loosely based on the operation of the human retina, to demonstrate desired target/background discrimination and target detection and tracking processing capabilities. This paper provides an introduction to artificial neural network technology and discusses some of the results that have been achieved by applying ANN technology to weapon system problems at the Naval Weapons Center.

Distributed processing of finite state grammars for connected word speech recognition

An algorithm is presented for performing real‐time connected word speech recognition under the constraint of a finite‐state grammar, and executed in a multiprocessor pattern recognition computer. Each processing element of the computer consists of a 40‐MIP one‐chip pattern recognition processor and its associated local memory. [S. Glinski et al., “The Graph Search Machine (GSM): A VLSI Architecture for Connected Speech Recognition and Other Applications,” Proc. IEEE 75 (9), 1172–1184 (1987)] Aspects of the algorithm discussed include: the choice of models for speech sound units, words, and grammars; the problems of partitioning the models across processing elements; and the problem of removing redundancy in the finite state grammar. Extensions of the algorithm to more powerful grammars is also discussed. The capacity of the recognizer (i.e., vocabulary size) as a function of grammatical complexity is presented. Results indicate that high‐accuracy medium vocabulary speaker‐trained connected word recognition is readily attainable.

Hybrid optical processor for pattern recognition and classification using a generalized set of pattern functions

A pattern recognition and classification system has been studied which computes the inner products of an input pattern with a generalized set of pattern functions. The system utilizes a filter whose impulse response consists of an amplitude superposition of a set of generalized pattern functions in phase-coded form and has a space-bandwidth product the same as that of a matched filter for one pattern function. Each pattern function in the general set may correspond to a different variation (e.g., scale or rotation) of the object to be detected. Because the amplitude superposition of the phase-coded pattern functions takes place in the digital computer, and the filter is created as a computer-generated hologram, the biasing problem of conventional, multiple exposure (intensity superposition) holograms is significantly reduced. This makes it possible to encode many more pattern functions than was previously possible using multiple exposure techniques. Furthermore, the use of computer-generated holograms eliminates the need to generate a transparency for each pattern function and complex phase code. To facilitate real-time operation a hybrid system was constructed consisting of a liquid crystal light valve for incoherent-to-coherent image conversion, a TV camera and image digitizer for image analysis, and a laser scanner to produce the computer-generated holograms. Both the TV camera/digitizer and the laser scanner systems were interfaced to a digital computer for automatic operation. Experimental results using the hybrid system are presented for pattern recognition of rotated and scaled objects and pattern classification. In the second half of the paper we provide an analysis on the SNR of the processor employing the coded-phase technique, on the diffraction efficiencies of computer-generated filters (amplitude superposition) vs conventional filters (intensity superposition), and on the number of pattern functions required for a certain recognition task.

A potential discrete analog processor for pattern recognition

A pattern recognition system is described which employs normalized cross-correlation as a measure of similarity. A potential implementation is presented which is based on existing or feasibile charge-coupled device discrete analog structures. Estimates of processing times are given.

Pattern recognition processor and its application to straight line reconstruction of spark chamber data

A general purpose hardware processor is described for use in conjunction with a digital computer to speed up reconstruction of straight line tracks from data generated in wire spark chamber experiments. The processor receives both data and operating instructions from the computer. With a 50 ns cycle time it executes a search algorithm which simultaneously tests many possible combinations of data. It quickly sorts out the points that are likely candidates for straight lines; the computer makes the final decision. 100 spark chamber events taken at the Argonne National Laboratory were analyzed using a pure software approach and compared with an analysis using responses from the Pattern Recognition Processor as simulated by a separate program. For equivalent operations the latter performed approximately four times as fast. The expectation that the Pattern Recognition Processor will do even better as the complexity of the events increases is discussed.