Abstract

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called “pattern”. Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

Highlights

  • This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in high energy physics experiments

  • The AM06 integrates serializer/deserializer IP blocks at 2 Gbit/s for input/output communication, to avoid routing congestion at the board level

  • It has been designed in 65 nm CMOS, combining full-custom memory arrays, standard logic cells and IP blocks

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Summary

Prepared for submission to JINST a INFN

– Laboratori Nazionali di Frascati, Via E. Fermi 40, 00044 Frascati, Italy c Laboratoire de Physique Nucléaire et de Hautes Energies (LPNHE), 4 place Jussieu, 75252 Paris, France d INFN – Sezione di Milano, Via G. Celoria 16, 20133 Milano, Italy e Università degli Studi di Milano, Via G. Celoria 16, 20133 Milano, Italy b INFN

The FTK architecture
The AM system
AM working principle
SER Unit data
Clock LVDS
Package and current consumption
Findings
Conclusion

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