Path Delay Test Generation Research Articles

Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation

Nanoscale VLSI systems are subject to increasingly significant performance variability. Accurate timing analysis and effective silicon-based performance verification techniques are critical to successful nanoscale VLSI design. The state-of-the-art statistical static timing analysis (SSTA) techniques cannot capture performance variability due to primary inputs and sequential element states which, however, is critical to path delay test generation. In this paper, we present the first dynamic statistical timing analysis-based VLSI path delay test pattern generation technique. We observe that VLSI timing analysis and power estimation target the same signal toggling activity. By leveraging the existing power estimation techniques, we have developed signal-probability-based statistical timing analysis (SPSTA), and SPSTA-based VLSI delay test pattern generation (SPSTA-DTPG) techniques. Our experimental results based on ISCAS’89 benchmark circuits show that the state-of-the-art statistical static timing analysis-based delay test pattern generation (SSTA-DTPG) achieves an average of 47.32%, 45.14%, and 57.98%, SPSTA-DTPG achieves an average of 57.41%, 61.43%, and 68.05%, while signal probability-based statistical timing analysis-based delay test pattern generation with (test pattern) compaction (SPSTA-DTPG-C) achieves an average of 83.09%, 87.48% and 90.30% coverage of the top 50, 100, and 200 timing-critical paths, respectively.

Path delay test generation at functional level

The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.

Path Delay Test Generation Toward Activation of Worst Case Coupling Effects

As the feature size scales down, crosstalk noise on circuit timing becomes increasingly significant. In this paper, we propose a path delay test generation method toward activation of worst case crosstalk effects, in order to decrease the test escape of delay testing. The proposed method performs transition-map-based timing analysis to identify crosstalk-sensitive critical paths, followed by a deterministic test generation process. Using the transition map instead of the timing window to manage the timing information, the proposed method can identify many false coupling sites and thus reduce the pessimism in crosstalk-induced fault collection caused by inaccurate timing analysis. It can also efficiently calculate the accumulative crosstalk-induced delay, and find the sub-paths which cause worst case crosstalk effects during test generation. By converting the timing constraints of coupling lines into logic constraints, complex timing processing for crosstalk effect activation is avoided during test generation. In addition, the tradeoff between accuracy and efficiency can be explored by varying the size of timescale used in the transition map.

Efficient Path Delay Test Generation for Custom Designs

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

Deriving logic systems for path delay test generation

We present an algorithm to derive logic systems for various classes of path delay test problems. In these logic systems, the value of a signal represents the relevant conditions that occur during a set of consecutively applied vectors. Starting from a set of basic values for valid signals at primary inputs, a state transition graph is constructed to enumerate all possible signal states relevant to path activation that are reachable by Boolean operations. These states include all incompletely specified states, composed as combinations of basic values. A distinguishability analysis then finds all state-pairs that need to be distinguished during test generation. The final step minimizes the number of states. For forward and backward implications of test generation in combinational or sequential circuits, the procedure provides optimal logic systems. We define optimality as the smallest set of logic states that provides the least possible ambiguity in implications. Thus, an optimal set of logic states will minimize the number of backtracks in test generation. A 10-valued logic described in the literature is found to be optimal for generating tests for single path delay faults. Other problems addressed in this paper include compact test generation through activation of many single path delay faults, test generation for rated-clock test application, and test generation for multiple path delay faults. The limitations and capabilities of various logic systems are illustrated by examples.