Passive Thermal Cycling Research Articles

Critical solder joint in insulated gate bipolar transistors (IGBT) power module for improved mechanical reliability

This investigation identifies the critical solder joint in a typical Insulated Gate Bipolar Transistor (IGBT) module and provided new knowledge on how operating thermal loads degrade IGBT-attach, Diode-attach, and Substrate solder joints in the device. SolidWorks software is used to create three realistic 3-D Finite Element (FE) models of the typical IGBT module used in this investigation. In-service operating power and IEC 60068–2-14 thermal cycles are implemented in ANSYS mechanical package to simulate the response of the three solder joints in the FE models to the load cycles. The solder in the joints is lead-free alloy of 96.5% tin, 3% silver, and 0.5% copper (SAC305) composition. The SAC305 material properties are modelled as time and temperature dependent with Anand's visco-plastic model employed as the constitutive model. Results show that the key degradation mechanism of solder joints in IGBT module are stress, plastic strain, and strain energy magnitudes. Accumulated plastic strain in the joints is found the predominant damage factor. Critical solder joint in the module depends on the load cycle the device experiences. IGBT-attach solder joint is critical in active power load cycle. Substrate solder joint degraded most in passive thermal cum combined passive thermal and active power load cycles.

Advantages of the extended finite element method for the analysis of crack propagation in power modules

• XFEM and Level set methods with submodelling has been implemented in this study. • Method easily allows inclusion of crack growth in IGBT wire bond reliability analysis • Bond wire diameter and loop height significantly affect IGBT wire bond reliability. • Wire bond degradation parameter values decrease with increasing crack length. • For similar load density, smaller wire diameter produces longer wire bond lifetime. The techniques of extended finite element method, level set method and the submodelling approach are implemented in this study to model crack and crack growth in ultrasonically bonded thick aluminium wire for the IGBT power electronics modules under different loading conditions for the purpose of lifetime prediction and reliability assessment during design and manufacturing stages. The crack growth and lifetime prediction were performed under cyclic fatigue passive thermal cycling and active power cycling for the bond wire lift-off failure mechanism while the J-integral for different heel crack lengths are predicted under mechanical loads. The analyses showed that the techniques implemented in this paper are effective for modelling such complex geometries and loading conditions and can easily be integrated in a virtual design platform for power electronics. The accuracy of the technique is evaluated by comparing with trends in the published experimental tests and simulation results as well as the standard finite element method which are all in a good agreement. The wire bond crack growth rate under cyclic loading is strongly influenced by the bond thickness and loading conditions.

Reliability Analysis of Large-Area, Low-Pressure-Assisted Silver Sintering for Medium-Voltage Power Modules

Multi-layer insulating ceramic substrates can enable medium-voltage (MV) power modules with reduced peak electric field. This benefit is particularly important for MV silicon carbide (SiC) MOSFETs due to their higher operating voltages. Large-area, low-pressure-assisted silver sintering is a potential solution for bonding substrates to create a multi-layer structure. The voiding content and defect density of the bond used to create the multi-layer substrate stack-up are critical to the reliability of the power module and thermal performance, as this bond is in the primary path for heat dissipation in the power module structure. Samples of two-layer direct bonded aluminum (DBA) stacks have been fabricated and subjected to thermal cycling to analyze their reliability. Passive thermal cycling from −40 °C to 200 °C was performed. Cross sections were cut at pre-determined intervals and imaged with scanning electron microscopy (SEM). After 1000 thermal cycles, adhesive failures are observed between the sintered silver and DBA surface. Cross sections were cut and imaged via optical microscope and SEM. Thermal analyzer measurements are recorded on a 10-kV SiC power module using the sintered DBA substrate stacks.

Prognostics and Health Management Features for Large Circuit Boards to Be Implemented Into Electric Drivetrain Applications

Abstract Canary structures being used as early warning indicators represent an important tool for condition and health monitoring of electronic components and systems. In this paper, printed circuit boards (PCBs) with canary structures based on surface mounted device (SMD)-2512 ceramic chip resistors with reduced solder pad sizes were studied. Focus of these investigations was set on thermomechanical and mechanical stresses caused by passive thermal cycling as well as by vibrational loads. For this purpose, experimental methods such as deformation analysis and accelerated aging tests as well as finite element (FE) based methods were applied. In addition, an outlook on the implementation of these canary structures into dual inverter electronic control boards for electrical powertrain applications will be given.

Reliability study of PCB-embedded power dies using solderless pressed metal foam

This paper presents a reliability study of an innovative process of embedding power dies in PCBs. Firstly, a description of this solderless package is given. Secondly, experimental tests of thermal ageing for the proposed package are performed through passive thermal cycling in the range of PCB standards. Thirdly, a 2D finite element model of the package is built using material properties obtained from previous thermomechanical characterizations. Numerical simulations of a passive thermal cycling of the package are carried out. The analysis of the strain-stress fields allows to highlight the time-space areas where they are critical and compromise the reliability.

Comparative Analysis of IGBT Parameters Variation Under Different Accelerated Aging Tests

Power semiconductor devices are vulnerable to thermomechanical fatigue due to temperature cycling caused by system load profile and external climatic conditions. As the reliability performance of power semiconductor devices in power converter systems is determined by this temperature stress, accelerated power or thermal cycling test are used in this article to emulate the temperature stress. The failure mechanisms due to temperature stress can be studied, and it also helps to develop the lifetime estimation model for power semiconductor devices. In the past, active power cycling and passive thermal cycling tests are investigated separately to develop the failure mechanism model based on the device’s electrical parameter changes and scanning electron microscopic (SEM) analysis. However, there is no detailed report on, how different temperature stresses emulated by dc, pulsewidth modulation (PWM) power cycling, and thermal cycling affects the device physically, and how much changes it introduces in the device’s electrical parameters. Therefore, this article presents an experimental investigation of active dc, PWM power cycling and passive thermal cycling approaches on 1.2-kV 50-A fast trench insulated gate bipolar junction transistor (IGBT) devices. The device electrical parameters, such as ON-state voltage, threshold voltage, gate current, gate voltage, and thermal resistance, were monitored during the study to classify the effects of temperature stress produced by dc, PWM power cycling, and thermal cycling on these electrical parameters.

Investigation of Active Power Cycling Combined With Passive Thermal Cycles on Discrete Power Electronic Devices

Active power cycling (APC) is a standardized and well-established method for reliability assessment and product qualification in power electronics (PEs) technologies. Repetitive pulses of load current are applied to cause cyclic thermal swings in the p–n junction and in the whole semiconductor device. They induce thermo-mechanical stresses, which ultimately leads to the typical interconnect failure in the “devices under test.” However, these tests are insensitive with respect to new automotive system architectures, in which PEs devices are exposed to additional loads besides the intrinsic thermal swings. The trends in PEs toward miniaturization, higher power density, heterogeneous system integration, and the deployment of PEs in harsher environments combined with longer lifetime and higher uptime requirements strongly increase the reliability demands in general and the need for more improved reliability assessment methodologies in particular. The new testing methods shall be more comprehensive and more efficient, i.e., they shall simultaneously cover the real service conditions better and reduce testing time. One promising approach is the combination of loading factors—such as the superposition of active power cycling by passive thermal cycles (TC). Both loading factors are well known to cause most relevant failure mechanisms in PEs. In reality, the PE devices are exposed to both factors simultaneously. Hence, this load case should also be replicated in the test. The paper will report a systematic investigation of such superimposed test schemes, which cover the case of self-heating and passive heating (from neighboring elements) of the PEs devices under real service conditions. Typical discrete PEs components in TO-200 packages are selected as test vehicles as they are likewise relevant for the domains of consumer or automotive electronics. The paper details the test concept and discusses the quantitative and qualitative test results.

Power electronics thermal solutions using thermally conductive polyimide films

Increased adoption of hybrid and electrical vehicles as well as renewable energy systems are driving the innovation in power module packaging. Thermal substrate, one of the major components of power modules, is not an exception, and technological advancements are necessary to meet increased reliability requirements. DuPont has developed a thermally conductive polymer film that provides very low thermal resistance and very high insulation. The film can be bonded to conductive and thick metallic layers and this polymer equivalent of DBC shows very high reliability in addition to high performance characteristics. Electrically insulating layers within a power electronics module are critical for separating circuitry from thermal management layers. Electrical insulating substrates typically used in power electronics modules utilize a ceramic layer, comprised most commonly of either Al2O3, AlN, or Si3N4. Thin Cu layers are bonded to either side of the substrate using a direct bond Cu (DBC) or active metal brazing (AMB) process. These processes involve bonding metallization layers to both sides of the ceramic at a high temperature as bonding to only one side would cause deformation during the cooling phase. Typical metal thickness bonded to either side of the ceramic is about 0.3–0.6 mm as the high temperature manufacturing process does not allow very thick metals to be bonded and this limits the heat spreading capability of the thermal substrate. DuPont's new Temprion™ Organic Direct Bond Copper (ODBC) address aforementioned problems, increasing thermal durability and reliability as well as enabling system layer suppression. Temprion™ ODBC's dielectric layer will absorb thermo-mechanical stress from the metals due to CTE mismatch, dramatically improving durability of the system. In addition, various kinds of metals including Cu and Al can be easily bonded to Temprion™ DB films through simple process. There are no thickness limitations on bonding metal sheets and metal attached at the bottom can be used as an integrated heat sink/baseplate. Al2O3 and Si3N4-based substrates were utilized as a baseline for reliability comparison with the DuPont substrates. The industry-standard substrates in used in this study have a thickness of 0.3 and 0.8 mm for the Cu metallization layers and 0.38 and 0.32 mm for the insulating layer respectively for Al2O3 an Si3N4 insulators. DuPont ODBC substrates were fabricated by attaching a polyimide layer to a layer of 0.8-mm-thick Cu. The polyimide and bottom Cu layer cross-sectional footprints are both 50.8 mm × 50.8 mm. The corners of both layers were filleted with various radii (0.5, 1.0, 2.0, and reversed 2.0 mm) to explore the impact of different stress concentrations between the metallization and insulating layers. The top Cu metallization was inset 2.0 mm from the perimeter of the electrically-insulating substrate and bottom Cu metallization.10 samples each of the DuPont ODBC and industry Al2O3 substrates were placed in a thermal shock chamber and cycled between temperature extremes of −40°C and 200°C. Substrates were inspected every 1000 cycles. After 5000 cycles, the ODBC substrates experienced no hipot failures, but preliminary edge delamination was visually observed. Al2O3 substrates all failed after 50 thermal cycles.Five DuPont ODBC samples were placed in a thermal chamber and subjected to an elevated temperature of 175°C. After 2000 hours, no hipot failures were observed, but edge delamination was again observed.Five DuPont ODBC samples were attached to a cold plate with Kapton tape. Heater cartridges were attached to the top of the substrates with Kapton tape and thermocouples were placed in several locations through the package. The heater cartridges were alternated between on and off states to allow for the substrates to cycle between −40°C and +200°C. While the change between the maximum and minimum temperatures is smaller for the power cycling test compared to the thermal cycling test, the heater cartridge and cold plate create a thermal gradient within the samples that is not possible with passive thermal cycling. After 2000 hrs cycles of testing, no hipot failures or edge delamination have been observed. Herein we show that the DuPont ODBC substrate design is a promising alternative to traditional industry substrates based on ceramic insulators. The reliability of the substrate design has been demonstrated under several thermomechanical accelerated tests and the electrical and thermal performance has been measured. Future work will include reliability comparisons to other industry substrates, including thermal shock testing of substrates with HPS, AlN, and Si3N4 ceramic layers. Thermal models will correlate thermal resistance values measured by the transient thermal tester and compare the ODBC substrate performance to industry substrates within a commercialized power electronics module. The modeling will also optimize the thickness of the metallization layers within the ODBC substrates to minimize the junction temperature of the switching devices.

Comparative Study of Al Metallization Degradation in Power Diodes Under Passive and Active Thermal Cycling

Degradation of Al metallization on Si-based semiconductor chips under operation is a reliability problem known for many years, but the mechanisms of this phenomenon are not fully understood. To quantify contributions of different possible effects, a passive thermal cycling setup has been developed allowing for accelerated tests by varying the device temperature on a short-time scale without applying electrical power. The setup is also capable of testing devices in different atmospheres. The results obtained by the thermal tests of diode chips are compared to those from power cycled diodes with a focus on the degradation of the top metallization layer. The data on the structural and electrical characterization of the samples show that the passive thermal cycling induces metallization degradation very similar to that found for the power-cycled devices. Thus, it can be concluded that the thermal-induced stresses are the dominating mechanisms for the metallization fatigue and the following failure. The role of oxidation and corrosion effects is also studied in the experiments on passive thermal cycling using different environmental conditions. It is suggested that the formation of self-passivating aluminum oxide under ordinary atmospheric conditions can play a positive role in limiting the structural and electrical degradation of the metallization layers. The obtained results represent a considerable contribution to an understanding of major failure mechanisms related to metallization fatigue and reconstruction.

Thermo-mechanically induced texture evolution and micro-structural change of aluminum metallization

During operation of high power electronic chips the topside metallization is subjected to cyclic compressive and tensile stresses leading to unwanted thermo-mechanical fatigue of the metallization layer. The stress is caused by the difference in the thermal expansion coefficients of the metallization and the semiconductor underneath that can lead to a severe structural degradation of the layer changing the electrical characteristics of the electronic chips, finally causing a failure. Although this problem is well-known, the underlying physical mechanisms governing this fatigue phenomenon are not yet fully understood. In this work, we investigate the microstructural evolution of an Al metallization on high power diode chips subjected to passive thermal cycling between $$20$$ and $$100\,^{ \circ } {\text{C}}$$ . The texture of the Al film is analyzed ex-situ by a combination of electron backscatter diffraction and X-ray diffraction. It is found that the initial dominating (111) orientation of Al grains in the film changes towards a (311) texture as the number of cycles increases. A simple model explaining the driving mechanism behind the crystallographic re-orientation is proposed. Also, large orientation gradients within individual grains are found to arise during thermal cycling, which results in sub-grain formation. These processes are the dominant mechanism for the degradation of the Al layer structure leading to the formation of voids and significant increase of the surface roughness.

Wire bond degradation under thermo- and pure mechanical loading

This paper presents a fundamental study on degradation of heavy Al bond wires typically used in high power modules. Customized samples are designed to only consist of Al bond wires on standard Si diodes. These samples are subjected to pure mechanical and passive thermal cycling to investigate the bond degradation behavior on a simple system as well as compare these two test methods. Although an appreciable difference in fracture behavior is observed between these two methods, both provide correlation between the number of cycles and degree of degradation, especially in the case of the passive thermal test. To enable investigation of degradation rate a large number of bond interfaces is analyzed and they are found to follow conventional accepted fracture laws like Paris-Erdogan. With additional work this could enable the possibility of obtaining empirical parameters to be used in actual physics based lifetime laws.

Advanced wire bonding for high reliability and high temperature applications

Abstract The next generation of switches for power electronic will be based on white band gap (WBG) semiconductor GaN or SiC. This materials supports higher switching current and high frequency. White band gap semiconductors enables higher application temperature. Certainly, high temperature capability is also to discuss in combination with high number of thermal cycles. For a frame module concept shows these paper a comparison of different joining techniques with the focus on the reliability issue on wire and ribbon bonding. Beside to the 1000 passive thermal cycles from −40°C to +125°C there are active thermals cycles for technology qualification required [3]. Depending on the application and mission profile a high thermal cycling capability is necessary. For this reason, new high temperature joining techniques for die attach, e.g. Silver sintering or diffusion soldering, were developed in the recent past [4]. All of this new joining techniques focusing on higher electrical, thermal and thermo-mechanical performance of power modules. By using an optimized metallization system for the WBG the numbers of thermal cycles can be increased and the maximum operating temperature advanced up to 300°C. In these new temperature regions silicon semiconductors will be substituted by WBG semiconductors. The present work shows an active power cycling capability of different wire and ribbon bonds and the failure mechanism will be discussed. A calculation model explained the reliability for the different wire diameter and the impact of bonding materials. This reliability calculation explain the thermo-mechanical effects and based on materials and geometry data and is not optimized for evidence. Through these physical background understanding more than 1.000.000 thermal cycles with a 150 K temperature swing from +30°C to +180°C are now possible. These is a the basic knowledge for a design for reliability based on current, mission profile and reliability optimization for future high end applications with wire or ribbon bonding technique.

Mechanisms of metallization degradation in high power diodes

Under operation the topside metallization of power electronic chips is commonly observed to degrade and thereby affecta device's electrical characteristics. However, the mechanisms of the degradation process and the role of environmental factors are not yet fully understood. In this work, we investigate the metallization degradation by passive thermal cycling of unpackaged high-power diode chips in different controlled atmospheres. The electrical degradation of the metallization is characterized by sheet resistance measurements, while the microstructural damage is investigated by scanning electron microscopy (SEM) and X-ray diffraction (XRD). To study the evolution of the chemical composition of the metallization, energy dispersive X-ray spectroscopy (EDX) is also applied. Since the degradation depends on the initial microstructure of the metallization, the film texture and grain size distribution is determined using electron backscatter diffraction (EBSD). The obtained data show that the type of atmosphere plays a minor role in the degradation process, with a slight tendency that cycling in dry nitrogen atmosphere accelerates the degradation compared to the experiments in ambient atmosphere with a controlled relative humidity of 50 and 95%.

A thermal cycling reliability study of ultrasonically bonded copper wires

In this work we report on a reliability investigation regarding heavy copper wires ultrasonically bonded onto active braze copper substrates. The results obtained from both a non-destructive approach using 3D X-ray tomography and shear tests showed no discernible degradation or wear out from initial conditions to 2900 passive thermal cycles from −55 to 125°C. Instead, an apparent increase in shear strength is observed as the number of thermal cycles increases. Nanoindentation hardness investigations suggest the occurrence of cyclic hardening. Microstructural investigations of the interfacial morphologies before and after cycling and after shear testing are also presented and discussed.

Effects of thermal cycling on aluminum metallization of power diodes

Reconstruction of aluminum metallization on top of power electronic chips is a well-known wear out phenomenon under power cycling conditions. However, the origins of reconstruction are still under discussion. In the current study, a method for carrying out passive thermal cycling of power diodes in a controlled environment is developed, thus eliminating possible contribution to degradation from electric current and humidity. The focus is centered on the structural changes in the top Al metallization layer of the power diodes, correlated with the change of sheet resistance. Since the atmosphere is controlled and the device is not subjected to a current load the observed degradation of metallization and corresponding increase of resistance is purely induced by thermo-mechanical stress. A correlation between number of cycles, micro-structural evolution, and sheet resistance is found and conclusions on the dominant role of thermo-mechanical stresses are achieved. Additionally, proposals are made on how the current thermal test setup can be further developed to study the role of corrosion.

Reliability of thick Al wire: A study of the effects of wire bonding parameters on thermal cycling degradation rate using non-destructive methods

The effect of bonding parameters on the reliability of thick Al wire bond is investigated. Samples were prepared with 25 different designs with 5 different bonding parameters such as time, ultrasonic power, begin-force, end-force and touch-down steps (pre-compression) with 5 levels. The bond signals of ultrasonic generator were collected during bonding in order to obtain prior quality information of bonded wires. 3D X-ray tomography was then used to evaluate bond quality during passive thermal cycling between −55°C and 125°C. Tomography datasets were obtained from the as-bonded condition and during cycling. The results clearly show ultrasonic power, appropriate levels of begin-force and touch-down steps are all important for achieving a well attached and reliable bond. Analysis of the virtual cross-sections indicates a good correlation between the bond signal (i.e. the initial bond quality) and wire bond damage/degradation rate. An improved understanding of the wire bonding process was achieved by observing the effect of the complex interaction of bonding parameters on the ultrasonic generator signals and degradation rate under thermal cycling.

Loss Density Distribution and Power Module Failure Modes of IGBT

The major cause of IGBT devices failure is heat. There is a need of higher power densities and decreased packaging solutions in the industries commercial applications. In order to meet the through-life reliability targets for power modules, it is critical to understand the response of typical wear- out mechanisms, for example wire-bond lifting and solder degradation So the concentration is on the tools that need to take into account detailed device structures and different physical phenomena / parameters that take place inside the semiconductor structure during operation and also to present the effect of power cycling frequency, load current and mean temperature on temperature variations within the power module structure and its impact on the life consumption for two common wear-out mechanisms (the bond wire and the substrate-solder). It is shown that bond wire degradation is the dominant failure mechanism for all power cycling conditions whereas substrate solder failure dominates for externally applied (ambient or passive) thermal cycling.

Application of coupled electro-thermal and physics-of-failure-based analysis to the design of accelerated life tests for power modules

In the reliability theme a central activity is to investigate, characterize and understand the contributory wear-out and overstress mechanisms to meet through-life reliability targets. For power modules, it is critical to understand the response of typical wear-out mechanisms, for example wire-bond lifting and solder degradation, to in-service environmental and load-induced thermal cycling. This paper presents the use of a reduced-order thermal model coupled with physics-of-failure-based life models to quantify the wear-out rates and life consumption for the dominant failure mechanisms under prospective in-service and qualification test conditions. When applied in the design of accelerated life and qualification tests it can be used to design tests that separate the failure mechanisms (e.g. wire-bond and substrate-solder) and provide predictions of conditions that yield a minimum elapsed test time. The combined approach provides a useful tool for reliability assessment and estimation of remaining useful life which can be used at the design stage or in-service. An example case study shows that it is possible to determine the actual power cycling frequency for which failure occurs in the shortest elapsed time. The results demonstrate that bond-wire degradation is the dominant failure mechanism for all power cycling conditions whereas substrate-solder failure dominates for externally applied (ambient or passive) thermal cycling.

A Novel High-Temperature Planar Package for SiC Multichip Phase-Leg Power Module

This paper presents the design, development, and testing of a phase-leg power module packaged by a novel planar packaging technique for high-temperature (250°C) operation. The nanosilver paste is chosen as the die-attach material as well as playing the key functions of electrically connecting the devices' pads. The electrical characteristics of the SiC-based power semiconductors, SiC JFETs, and SiC Schottky diodes have been measured and compared before and after packaging. No significant changes (<;5%) are found in the characteristics of all the devices. Prototype module is fabricated and operated up to 400 V, 1.4 kW at junction temperature of 250°C in the continuous power test. Thermomechanical robustness has also been investigated by passive thermal cycling of the module from -55°C to 250°C. Electrical and mechanical performances of the packaged module are characterized and considered to be reliable for at least 200 cycles.

Unusual Observations in the Wear-Out of High-Purity Aluminum Wire Bonds Under Extended Range Passive Thermal Cycling

This paper reports on the reliability of ultrasonically wedge-bonded 99.99% (4N) and 99.999% (5N) pure aluminum wires under different passive thermal cycling ranges, namely, -40°C to 190°C, -60°C to 170°C, -35°C to 145 °C, and -55°C to 125°C. The rate of bond strength degradation during cycling was found to be more rapid in the wire bonds subjected to lower peak temperatures (Tjmax) and lower temperature ranges (ΔT) for both wire types. This observed effect of ΔT cannot be described by the commonly accepted empirical relationships based on damage accumulation, such as the Coffin-Manson law. In addition, the 4N wire bonds were found to degrade more rapidly than the 5N bonds under the cycling ranges investigated. Microstructural characterization and nanoindentation of the bond interfaces indicated differences in microstructural restoration in wires subjected to the different cycling ranges. These differences have been attributed to annealing phenomena occurring in the wires during the high-temperature phase of cycling, which are believed to remove some of the damage accumulated during the low-temperature phase. A model is proposed for the prediction of wire bond wear-out rate, which incorporates both damage accumulation and damage removal mechanisms. We conclude that the rate of annealing during cycling varies exponentially with temperature; the annealing effects which occur can reduce damage accumulation and therefore influence wire bond reliability.