Passive RC Research Articles

A Compact and Ultra-Low-Power Low-Pass Filter Based on Band-to-Band Tunneling Effect

Continuous-time filters with low-frequency cutoff are crucial building blocks in analog signal processing circuits for speech processing and biomedical applications. The design of an integrated continuous-time filter with a cutoff frequency spanning from sub-Hz to a few kHz is constrained by the ultra-low power and area minimization requirement. In this article, we have experimentally demonstrated a low pass filter response using only a single partially depleted (PD) silicon on insulator (SOI) transistor. The proposed novel filter is based on band to band tunnelling (BTBT). This low pass filter is on-chip tunable to provide a wide cutoff frequency ranging from 2 Hz to 20 kHz, with a silicon footprint of 9 μm2 and the maximum power consumption of 0.6 nW in Global Foundries’ (GF) 45 nm RFSOI technology. The proposed tunneling-based filter is less prone to process variations and mismatches as compared to traditional integrated analog filters. The proposed BTBT-based passive RC filter with spurious free dynamic range (SFDR) of 29 dbc, outperforms previously reported filters in the literature in terms of power consumption and area. The ultra-low power consumption and area efficiency make this proposed low pass filter suitable for the multichannel analog front-end low-frequency filters for noise-tolerant neural network-based applications such as speech recognition and electrophysiological signal recognition.

A 13-Level SC DAC Achieving High Linearity With a Simple DEM for Wideband CT DSMs

Wideband continuous-time (CT) Delta-Sigma modulators (DSMs) generally demand multi-level digital-to-analog converters (DACs), which require a linearization technique to overcome the problem of component mismatches. Dynamic element matching (DEM) is a popular DAC linearization approach but can be challenging to implement in a wideband DSM, particularly when there are many DAC elements. In this manuscript, we introduce a 13-level switched-capacitor (SC) DAC achieving high linearity with a simple DEM that rotates three unit elements only and does not incur excess loop delay. In a traditional CT DSM, a DAC of the SC type increases the amplifier settling requirements and damages the alias rejection. Earlier works have shown that these problems can be solved if the CT DSM adopts a passive RC frontend. A 10-MHz bandwidth CT DSM is designed in the 65-nm CMOS technology to validate the proposed DAC. Simulations show that the DAC enables a spurious-free dynamic range greater than 87.7 dB and a signal-to-noise pulse distortion ratio greater than 80.5 dB under a 1% capacitor mismatch, a 2% reference voltage error, and process variations.

Realization of the TOW-THOMAS Biquad Active Filter

The Tow-Thomas Biquad Circuit provides the filter designers with a valuable building block for building higher order active filters. It is a flexible circuit structure in which the transfer function properties are easily manipulated by modifying the passive RC elements that connect the operational amplifiers. It can be easily defined in its low-pass and bandpass operations. Above all, we can easily fabricate the possible filters inside a single chip with very slight modification of the standard Tow-Thomas Circuit.

A Low Phase Noise Frequency Synthesizer with a Fourth-Order RLC Loop Filter

The current work employs the HMC830 phase-locked loop chip to design a frequency synthesizer operating in the L-band. The frequency synthesizer can provide a local oscillation signal for the RF receiver front end. This article employs the phase-locked synthesis technique to describe the design scheme. Due to the advantages of the passive loop filters, such as simplicity, low cost, and low phase noise, a passive fourth-order RLC loop filter is proposed to improve the output signal quality and reduce phase noise. The performance of this loop filter is compared with the passive fourth-order RC loop filter. The effects of these two loop filters on phase noise, loop capture time, and spur suppression are analyzed. Subsequently, the design scheme, simulation analysis, and test results of the frequency synthesizer are presented under these two loop filters. The test results indicate that the passive fourth-order RLC loop filter outperforms the passive fourth-order RC loop filter; its output signal phase noise is higher than −100 dBc/Hz@1 kHz, loop capture time is less than 100 us, and spur suppression is better than 60 dBc. This frequency synthesizer can provide high-performance local oscillation signals for wireless communication equipment such as transmitters and receivers. It meets the application requirements of many radio communication circuit structures and has good application prospects.

Electro-acoustic analogies between thermoelastic component of the photoacoustic signal and low-pass RC filter

This paper presents a new approach to the thermal characterization of aluminum, based on the electro-acoustic analogy between the thermoelastic component of the photoacoustic signal and the passive RC low-pass filter. The analogies were used to calculate the characteristic thermoelastic cut-off frequencies of the photoacoustic component and obtain their relationship with the thickness of the aluminum samples. Detailed numerical analysis showed that the required relationship is linear in the loglog scale and can serve as a reference curve for the given material. The results of the numerical analysis were also confirmed experimentally.

Revisiting passive RC networks with over unity gain

Revisiting passive RC networks with over unity gain

A Multi-Frequency Focused Impedance Measurement System Based on Analogue Synchronous Peak Detection

Monitoring of anatomical structures and physiological processes by electrical impedance has attracted scientists as it is noninvasive, nonionizing and the instrumentation is relatively simple. Focused Impedance Method (FIM) is attractive in this context, as it has enhanced sensitivity at the central region directly beneath the electrode configuration minimizing contribution from neighboring regions. FIM essentially adds or averages two concentric and orthogonal combinations of conventional Tetrapolar Impedance Measurements (TPIM) and has three versions with 4, 6, and 8 electrodes. This paper describes the design and testing of a multi-frequency FIM (MFFIM) system capable of measuring all three versions of FIM at 8 frequencies in the range 10 kHz—1 MHz. A microcontroller based multi-frequency signal generator and a balanced Howland current source with high output impedance (476 kΩ at 10 kHz and 58.3 kΩ at 1 MHz) were implemented for driving currents into biological tissues with an error <1%. The measurements were carried out at each frequency sequentially. The peak values of the amplified voltage signals were measured using a novel analogue synchronous peak detection technique from which the transfer impedances were obtained. The developed system was tested using TPIM measurements on a passive RC Cole network placed between two RC networks, the latter representing skin-electrode contact impedances. Overall accuracy of the measurement was very good (error <4% at all frequencies except 1 MHz, with error 6%) and the resolution was 0.1 Ω. The designed MFFIM system had a sampling rate of >45 frames per second which was deemed adequate for noninvasive real-time impedance measurements on biological tissues.

Analysis, design and experimentation of high-pass negative group delay lumped circuit

PurposeThe purpose of this paper is to introduce an innovative theoretical, numerical and experimental investigations on the HP NGD function. The identified HP NGD topology under study is constituted by first order passive RC-network. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about -1 ns and cut-off frequencies of about 20 MHz are obtained.Design/methodology/approachThe identified HP NGD topology understudy is constituted by a first-order passive Resistor-capacitor RC network. An innovative approach to HP NGD analysis is developed. The analytical investigation from the voltage transfer function showing the meaning of HP properties is established.FindingsThis paper introduces innovative theoretical, numerical and experimental investigations on the HP NGD function.Originality/valueThe NGD characterization as a function of the resistance and capacitance parameters is investigated. The feasibility of the HP NGD function is verified with proofs of concept constituted of lumped surface mounted components on printed circuit boards. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about −1 ns and cut-off frequencies of about 20 MHz are obtained.

A 170 MHz to 330 MHz Wideband 90 nm CMOS RC–CR Phase Shifter with Integrated On-Line Amplitude Locked Loop Calibration for Hartley Image Rejection Transceiver

A 160 MHz bandwidth 90° active RC–CR phase shifter with integrated on-line amplitude locked loop (ALL) calibration targeted to 802.11ac 5 GHz wireless local area network (WLAN) applications is presented in this paper. The quadrature phase shifter is a key component for transceivers employing the Hartley image rejection architecture. The passive RC–CR phase shifter generates the required two quadrature outputs with an accurate 90° phase shift over the required bandwidth but lack the required accuracy in amplitude matching. A 90 nm CMOS microelectronic implementation of an RC–CR phase shifter is proposed with active resistors that are adjusted by an integrated on-line ALL calibration system to maintain matching amplitudes of the quadrature outputs over the required bandwidth. The on-line ALL calibration system employs peak detectors, comparators, digital logic control, and charge pump to incrementally adjust the active resistors while converging to matched amplitudes similar to the operation of phase-locked loop with a phase-frequency detector and charge pump. The resulting 90 nm implementation supports − 40db to − 70db image rejection ratios (IMMRs) over the IF 170 MHz to 330 MHz bandwidth. The 90 nm CMOS implementation is fully functional considering process variations based on 200 Monte Carlo simulations.

Polydimethylsiloxane‐based capacitive motion sensor and its read‐out circuit

SummaryA capacitive motion sensor that can detect human walking and motions up to a certain distance was designed using polydimethylsiloxane (PDMS) as the primary sensor material. A read‐out circuit was designed to detect capacitive coupling with the sensor material caused by the motion in the surrounding. The read‐out circuit consists of sensing, filtering, and amplifying stages. A high‐pass filter was used to avoid DC components, and to eliminate adverse impacts of 50Hz noise in the sensing signal, a sixth‐order low‐pass filter consisting of active Sallen–Key and passive RC filters was utilized. The signals obtained from the complete read‐out circuit revealed that the sensor system could accurately detect human movements up to 2 m away. Also, different signal patterns were obtained from the output of the sensor system for various human motions.

Dual feedback IRC ring for chaotic waveform generation

The authors have proposed an inverter resistor capacitor (IRC)-based simple chaotic ring oscillator with dual feedback for the generation of the chaotic waveform. The proposed chaotic system uses three coupled autonomous first-order differential equations and it can be electrically demonstrated using the complementary metal oxide semiconductor (CMOS) inverters with few passive RC elements for the generation of the high-frequency strange attractor. The basic dynamical characteristics and multistability property with complex bifurcation pattern in a wide range of parameters are well observed through theoretical as well as numerical simulation analysis using scaled inverse tangent function. In addition, a simple IRC chaotic model design is investigated using 0.18μm MOS transistor parameters with grounded capacitors and an equivalent CMOS-based scaled inverse tangent function. Moreover, the Cadence post layout simulation gives useful information about the circuit sustainability for IC design with high frequency (MHz), low power dissipation (940 μW) and small chip area (826.3 μm2).

Performance Limits of Generalized Sampling Based 2-Channel Analog-to-Digital Converter

This brief proposes an analog-to-digital converter (ADC) based on Generalized Sampling Theorem and derives a closed form expression of its performance, viz., signal-to-quantization noise ratio (SQNR) and alias-suppression (AS). The ADCs in the 2-channels sample the signal and its filtered version, respectively, at half the Nyquist rate. The outputs of the two ADCs are upsampled by a factor of 2, passed through appropriate reconstruction filters, and then added to give an effective sample-rate which is double that of the sample-rate of each channel ADC. Performance of the proposed ADC has been summarized for simple filters like differentiator, integrator, passive RC low-pass filter, and passive CR high-pass filters. The proposed ADC could therefore be used as an alternative to other popular ADC structures like time-interleaved, frequency-interleaved, and filter-bank ADCs, to achieve high sample-rate with minimal analog circuit overhead.

Analog Modeling of Fractional-Order Elements: A Classical Circuit Theory Approach

In this paper a comprehensive procedure for the analog modeling of Fractional-Order Elements (FOEs) is presented. Unlike most already proposed techniques, a standard approach from classical circuit theory is applied. It includes the realization of a system function by a mathematical approximation of the desired phase response, and the synthesis procedure for the realization of basic fractional-order (FO) one-port models as passive RC Cauer- and Foster-form canonical circuits. Based on the presented one-ports, simple realizations of two-port differentiator and integrator models are derived. Beside the description of the design procedure, illustrative examples, circuit diagrams, simulation results and practical realizations are presented.

Pass-Band Gain Improvement Technique for Passive RC Polyphase Filter in Bluetooth Low-IF Receiver Using Two RC Band-Stop Filters

This paper proposes a method to design a flat pass-band gain with two RC band-stop filters for a 4-stage passive RC polyphase filter in a Bluetooth receiver. Based on the superposition principle, the transfer function of the poplyphase filter is derived. However, the pass-band gain of this filter is not flat on the positive frequency domain. There are two local maximum values when the input signals are the wanted signals. Therefore, two RC band-stop filters are used to improve the pass-band gain of these local maximum values. As a result, a flat pass-band gain passive RC poly-phase filter is designed for a Bluetooth low-IF receiver which image rejection ratio is-36dB, and ripple gain is 0.47dB.

Fractional-Order Chaotic Memory with Wideband Constant Phase Elements.

This paper provides readers with three partial results that are mutually connected. Firstly, the gallery of the so-called constant phase elements (CPE) dedicated for the wideband applications is presented. CPEs are calculated for 9° (decimal orders) and 10° phase steps including ¼, ½, and ¾ orders, which are the most used mathematical orders between zero and one in practice. For each phase shift, all necessary numerical values to design fully passive RC ladder two-terminal circuits are provided. Individual CPEs are easily distinguishable because of a very high accuracy; maximal phase error is less than 1.5° in wide frequency range beginning with 3 Hz and ending with 1 MHz. Secondly, dynamics of ternary memory composed by a series connection of two resonant tunneling diodes is investigated and, consequently, a robust chaotic behavior is discovered and reported. Finally, CPEs are directly used for realization of fractional-order (FO) ternary memory as lumped chaotic oscillator. Existence of structurally stable strange attractors for different orders is proved, both by numerical analyzed and experimental measurement.

Accurate Constant Phase Elements Dedicated for Audio Signal Processing

This review paper introduces real-valued two-terminal fully passive RC ladder structures of the so-called constant phase elements (CPEs). These lumped electronic circuits can be understood as two-terminal elements described by fractional-order (FO) dynamics, i.e., current–voltage relation described by non-integer-order integration or derivation. Since CPEs that behave almost ideally are still not available as off-the-shelf components, the correct behavior must be approximated in the frequency domain and is valid only in the predefined operational frequency interval. In this study, an audio frequency range starting with 20 Hz and ending with 20 kHz has been chosen. CPEs are designed and values tabularized for predefined phase shifts that are commonly used in practice. If constructed carefully, a maximum phase error less than 0.5° can be achieved. Several examples of direct utilization of designed CPEs in signal processing applications are provided.

A novel active AC coupled input stage of instrumentation amplifier for bioelectrical applications

For recording bioelectrical signals using Instrumentation Amplifiers (INA), capacitive AC coupling of the differential inputs is necessary for two major reasons, providing DC electrical isolation of the subject to avoid hazards of tissue burn, and to block DC or very low frequency skin-electrode contact potentials. The latter, when met, allows high admissible differential gain of the INA, which in turn, is expected to give a desirable high Common Mode Rejection Ratio (CMRR). However, the use of conventional passive RC high pass filters at the input greatly reduces CMRR. This work intends to design an improved AC coupled input circuitry for INA giving high CMRR and high input impedance. A differential RC high-pass input circuit has been developed using an active element. It creates an effective high resistance for the common mode current but provides a low resistance path to input bias currents for normal operation of the INA. Between 1 Hz and 100 Hz, CMRR of the DC coupled INA (LT1167) was 115 dB, using a well matched traditional RC coupling, 55 to 95 dB, while it was 110 dB using the improved active AC coupled circuit. This improvement was practically demonstrated through Electrocardiogram measurements from a human subject. A novel active AC coupling circuitry has been proposed and developed giving high CMRR, very close to the maximum of an INA, which is non-varying within the frequency band of interest of Bioelectrical amplifiers. The developed input circuit will improve all bioelectrical measurements in the future.

A 170.7-dB FoM-DR 0.45/0.6-V Inverter-Based Continuous-Time Sigma–Delta Modulator

This brief presents a low-voltage inverter-based continuous-time sigma-delta modulator (CT-SDM). The inverter-based amplifiers are single-stage and their operating point is provided by a bulk-based current mirror. To improve the power-efficiency, a passive RC path is used to assist the amplifier of the first integrator. The proposed modulator was fabricated in a 180-nm CMOS process with an active area of $0.36~\mathrm {mm}^{2}$ . The modulator loop filter operates with a supply voltage of 0.45 V while the digital circuitry operates at 0.6 V. The modulator total power consumption is $28.72~\mu \text{W}$ . For a 50-kHz signal bandwidth, the measured peak SNR/SNDR is 71.24/70.64 dB and the achieved DR is 78.3 dB, leading to a Schreier figure-of-merit of 170.70 dB.

Techniques for Sigma Delta ADC Design using CMOS Technology for CODEC

This paper presents the careful study of sigma-delta analog to digital convertor. The operations, characterizing parameters and totally different structures projected square measure conferred in basic type. the varied techniques and strategies for the design of a CMOS 3rd order Continuous Time (CT) Sigma Delta (SD) Modulator, where in to enhance the gain of the loop filter and to avoid the loading effect of the succeeding stage, facile differential pairs square measure enclosed between the passive RC integrators. then the ADC are optimized victimization Genetic Algorithms so as to realize the nice exchange between RC variations and loop stability.This makes SD-ADC more advantageous compared to conventional converters, that makes possible to use this SD-ADC in bio-medical applications

Ultralow power voltage reference circuit for implantable devices in standard CMOS technology

SummaryAn ultralow power CMOS voltage reference for body implantable devices is presented in this paper. The circuit core consists of only regular threshold voltage PMOS transistors, thus leading to a very reduced output voltage dispersion, defined as σ/μ, and extremely low power consumption. A mathematical model of the generated reference voltage was obtained by solving circuit equations, and its numerical solution has been validated by extensive electrical simulations using a commercial circuit simulator. The proposed solution incorporates a passive RC low‐pass filter, to enhance power supply rejection (PSR) over a wide frequency range, and a speed‐up section, to accelerate the switching‐on of the circuit. The prototype was implemented in 0.18 μm standard CMOS technology and is able to operate with supply voltages ranging from 0.7 to 1.8 V providing a measured output voltage value of 584.2 mV at the target temperature of 36° C. The measured σ/μ dispersion of the reference voltage generated is 0.65% without the need of trimming. At the minimum supply of 0.7 V, the experimental power consumption is 64.5 pW, while the measured PSR is kept below –60 dB from DC up to the MHz frequency range.