Passive RC Research Articles

Design and Assessment of a 6 ps-Resolution Time-to-Digital Converter With 5 MGy Gamma-Dose Tolerance for LIDAR Application

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. A novel multi-stage noise-shaping (MASH) delta-sigma $(\Delta\Sigma)$ TDC structure is proposed for applications in continuous-time pulsed time-of-flight (TOF) rangefinders for nuclear reactor remote sensing, which requires both high resolution and multi MGy gamma-dose radiation tolerance. The converter, implemented in 0.13 $\mu{\rm m}$ , achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the oversampling ratio (OSR) is 250. The TDC core consumes only 1.7 mW and occupies an area of 0.11 ${\rm mm}^{2}$ . Owing to the usage of circuit level radiation hardened-by-design techniques, such as passive RC oscillators and constant- $g_{m}$ biasing, the TDC exhibits enhanced radiation tolerance. At a low dose rate of 1.2 kGy/h, the frequency of the counting clock in the TDC remains constant up to at least 160 kGy. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the TDC still achieves a time resolution of 10.5 ps with an OSR of 250.

DESIGN OF -1/2n ORDER ANALOG FRACTANCE APPROXIMATION CIRCUIT USING CONTINUED FRACTIONS DECOMPOSITION

In order to solve the most important problem of the fractional calculus (FC) application, the realization of analog circuit of fractance, continued fraction theory is applied to design the -1/2n order analog fractance approximation circuit. The author presents a network function of ideal fractance and decomposes it in continued fractions (CFs) form to obtain the corresponding analog fractance approximation circuit. The new circuit consists of ordinary passive RC component through network synthesis method. Simulations are performed for the verification of the new circuit. Experimental evidence has proved that the performance of novel -1/2n order analog fractance approximation circuit is good in both amplitude-frequency response and phase-frequency response.

A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology

In this paper, a 48-200 MHz CMOS hybrid tracking low-pass filter with low power and high dynamic range is presented to solve a local oscillator harmonic-mixing problem for Advanced Television Systems Committee terrestrial digital TV tuner integrated circuits. For low power consumption, the first-order passive RC filter and the second-order transconductor-C filter are combined to implement the third-order Chebyshev tracking low-pass filter. A transconductor linearization technique based on a method of multiple gated transistors is adopted to achieve high dynamic range. Fabricated in a 0.18 μm CMOS process, it achieves a maximum in-band input-referred noise density of 5.1 nV/√Hz and maximum in-band output-referred third-order intercept point of 17.3 dBm, while dissipating 23.4 mW with 1.8 V. The total chip area is 0.6 mm × 0.4 mm.

A NON-CONSERVATIVE MODEL OF SECOND-ORDER RC SINUSOIDAL OSCILLATORS

In this work we derive a general non-conservative model for any RC sinusoidal oscillator independent of its particular passive topology or the employed active devices. We consider an arbitrary unknown second-order passive RC network terminated at one port by a negative resistor and proceed to impose oscillation start-up and frequency constraints on a derived state-matrix.

Debye Model Fitting for Time-Domain Modeling of Lossy Dielectrics

In this paper, we will show a systematic procedure for fitting a Debye model to tabulated data of dielectric constant and loss tangent at discrete frequency points. Our approach is based on generation of a guaranteed passive RC macromodel, satisfying Kronig-Kramers relations for complex permittivity. We present for the first time an RC vector fitting method.

RF Oscillator Based on a Passive RC Bandpass Filter

A passive RC bandpass filter (BPF) based voltage-controlled-oscillator (VCO) operating at 2.5 GHz is presented. In GHz frequency range, a preferred type of an oscillator is either an LC oscillator or a ring oscillator. An LC oscillator exhibits an excellent phase noise performance while its fabrication cost is expensive due to the inductors. On the other hand, a ring oscillator can be built with standard CMOS devices resulting in a cheap fabrication cost. However, it has a poor phase noise and jitter performance and is sensitive to power supply noise. This paper proposes a RC BPF-based oscillator. Its property is closer to a LC oscillator rather than a ring oscillator and, as a result, improves the jitter performance due to power supply noise. Also, it can be fabricated in a standard CMOS process since there is no inductor. To prove the proposed concept, a RC BPF-based oscillator was designed and fabricated in a standard 0.13-mum CMOS technology. An operating frequency of 2.5 GHz and phase noise of - 95.4 dBc/Hz at 1 MHz offset was measured. Power consumption was 2.86 mW from a 1.3 V supply voltage.

Analysis and Design of Passive Polyphase Filters

Passive RC polyphase filters (PPFs) are analyzed in detail in this paper. First, a method to calculate the output signals of an n-stage PPF is presented. As a result, all relevant properties of PPFs, such as amplitude and phase imbalance and loss, are calculated. The rules for optimal pole frequency planning to maximize the image-reject ratio provided by a PPF are given. The loss of PPF is divided into two factors, namely the intrinsic loss caused by the PPF itself and the loss caused by termination impedances. Termination impedances known a priori can be used to derive such component values, which minimize the overall loss. The effect of parasitic capacitance and component value deviation are analyzed and discussed. The method of feeding the input signal to the first PPF stage affects the mechanisms of the whole PPF. As a result, two slightly different PPF topologies can be distinguished, and they are separately analyzed and compared throughout this paper. A design example is given to demonstrate the developed design procedure.

Impedance spectroscopy using maximum length sequences: Application to single cell analysis

A maximum length sequence (MLS) is used to perform broadband impedance spectroscopy on a dielectric sample. The method has a number of advantages over other pulse-based or frequency sweep techniques. It requires the application of a very short sequence of voltage steps in the microsecond range and therefore allows the measurement of time-dependent impedance of a sample with high temporal resolution over a large bandwidth. The technique is demonstrated using a time-invariant passive RC network. The impedance of single biological cell flowing in a microfluidic channel is also measured, showing that MLS is an ideal method for high speed impedance analysis.

Application of the Thermal Quadrupole Method in the Characterization of Thermoelectric Modules

AbstractMeasurements of assembled thermoelectric (TE) modules commonly include investigations of the module output power versus load resistance. Using an AC electrical measurement for TE modules, a model of equivalent passive RC circuit has been developed and tested for both the thermal and electrical characteristics of the module. In this work we present and analyze data of a commercially available module, using equivalent passive RC circuit, to examine, explain and model the electro-thermal activity in the module. In addition data we analyzed by thermal quadrupole theory. Measurements were taken over the frequency range of 0,5mHz to 50 Hz and the device performance (ZT) was evaluated from measured data.

A polyphase filter based on CMOS inverters

A new idea for generation of quadrature signals on chip is presented. The topology is based on a passive RC polyphase filter, where the resistive parts are made active by using inverters. The activ...

Canonical forms of one-port Passive Distributed thermal networks

In this paper, it is shown that, one-port passive distributed thermal networks admit four canonical representations which generalize the four canonical forms of one-port passive lumped RC networks: Foster I and II canonical forms, Cauer I and Cauer II canonical forms. Insights on the physical significance of these four generalized canonical representations are given.

Printed polymeric passive RC filters and degradation characteristics

Ink-jet printed thin films of conductive polymers such as polyaniline (PANI), poly(3,4-ethylenedioxythiophene) (PEDOT) doped with poly(styrene sulfonate) and polymer dielectric material poly(4-vinylphenol) (PVP) were used to make RC filters. Both high-pass and low-pass filters were tested. The fabrication process and device characteristics of the RC filters have been demonstrated. Degradation of the ink-jet printed RC filters has been investigated, and the results indicate that PEDOT/PSS RC filters are more stable than those made from PANI.

Robust technique for on-chip DC current measurements

A robust and highly scalable technique for measuring DC currents is described. The circuit consists largely of digital electronics except for a comparator and a passive RC filter. This simple structure is able to force a voltage at a circuit node while measuring the current that flows into it. The technique has been successfully demonstrated using a prototype constructed using a 0.35mm CMOS chip. The demand for highly integrated mixed-signal ICs has increased rapidly in recent years. This is mostly driven by the communications industry. However, as the level of integration increases, more and more analogue components are becoming buried deep inside the digital circuitry without external I/O access. Consequently, initial device character- isation and production testing of these components has become more challenging. An area of IC testing that is being affected by this high level of integration are the DC parametric tests. These tests are conducted to characterise a wide variety of mixed-signal circuits such as analogue-to-digital converters (ADCs), PLLs and bias networks. Also, these tests are needed in digital test applications such as pad current leakage and IDDQ tests. One type of DC parametric tests that is of focus involves forcing a voltage at a circuit node while measuring the current that flows into it. The traditional method for on- chip current measurements is by using a transimpedance amplifier (1, 2), an integrating network (3, 4) or a shunt resistance (5). However, all of these circuits involve the use of elaborate ADCs with trimmed components, which makes them more expensive and relatively nonscalable for on-chip implementation. This paper presents a novel technique for force-voltage current measurements. It makes use of simple ADCs and programmable voltage references (DACs) to capture the DC transfer characteristic of an internal load at different current levels. Once known, the transfer characteristic of the internal load can be used indirectly to determine the value of an unknown current level connected to the test circuit. The proposed method requires mostly digital logic with the exception of a comparator and several passive RC components. As a result, the circuit architecture will be able to take advantage of the down-scaling of digital integrated circuit technology and not be affected by the reduction in power supply voltages. Also, the system is programmable,

Seismic Behavior and Analysis of Dual Function Slitted Shear Wall

A new type of passive controlled RC shear wall, called dual function slitted shear wall (DFW wall), was proposed by the first author. DFW wall is formed by setting connectors in the vertical slits of RC slitted wall. DFW wall can provide greater stiffness and strength than RC slitted wall during small and moderate earthquakes, and performs a ductile flexure failure as RC slitted wall with the failure of connectors during severe earthquakes. Experimental studies to investigate the seismic behavior of DFW wall, including seven wall specimens and thirteen connector specimens, were introduced first in this paper. An analytical model was then proposed to calculate the full skeleton load-displacement relation for DFW wall. The analysis results were found to agree well with test ones. A dual seismic structural model was used to study the dynamic response of DFW wall using the time history analysis method. Experimental research and analysis demonstrated the dual control functions, and showed that DFW wall has better seismic performance than the corresponding slitted shear wall.

Low-frequency differentiators and integrators for biomedical and seismic signals

A general active-network synthesis approach to inverse system design is introduced. The approach is applied to a passive RC differentiator and a passive RC integrator to obtain, respectively, a very low-frequency differential integrator and a very low-frequency differential differentiator. The frequency ranges of the proposed circuits, from dc to a few hundred hertz, are particularly suitable to the frequency ranges of biomedical and seismic signals. The advantages of the proposed circuits are delineated and include single time constants, dc stable integrators, and resistive input differentiators. Noninverting and inverting differentiators and integrators could be obtained by grounding one of the input terminals in the differential configurations.

Low-power fully differential CMOS filter for video frequencies

The authors describe a new low-power fully differential second-order continuous-time low-pass filter for use at video frequencies. The filter uses a single active device in combination with MOSFET resistors and grounded capacitors to achieve very low-power consumption and large dynamic range. The ideal integrator is realized using an internally compensated op-amp consisting of only current mirrors and voltage buffers, while the lossy integrator is implemented by a single passive RC circuit. The filter has been simulated using a CMOS process. Results show that with a single 5-V power supply, cutoff frequency can be tuned from 3.5 to 8 MHz, dynamic range is better than 67 dB and power consumption is less than 1.7 mW.

A high-resolution time interpolator based on a delay locked loop and an RC delay line

An architecture for a time interpolation circuit with an rms error of /spl sim/25 ps has been developed in a 0.7-/spl mu/m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology.

A stable inverting integrator with an extended high-frequency range

A stable inverting integrator is described. The integrator is obtained by inverting the transfer function of a passive RC differentiator. The integrator uses one operational amplifier. The resulting integrator has a built-in zero that could extend its high-frequency range of operation considerably beyond that of the Miller integrator. Experimental and simulation results verify the feasibility of the basic concept and the proposed circuit.

New Current-Mode Notch and Allpass Filters with Single Current Difference Amplifier

A new configuration for realization of current-mode notch and allpass filters is presented. It can synthesize second-order notch and allpass filters using a single current difference (Norton) amplifier and at most eight passive RC one port elements. Experimental results obtained from a notch filter realization are presented.

Responses of the transmembrane potential of myocardial cells during a shock.

The purpose of this investigation was to study the transmembrane potential changes (delta Vm) during extracellular electrical field stimulation. Vm was recorded in seven guinea pig papillary muscles in a tissue bath by a double-barrel microelectrode with one barrel in and the other just outside a cell while shocks were given across the bath. The short distance (15 to 30 microns) between the two microelectrode tips and alignment of the tips parallel to the shock electrodes eliminated the shock artifact. Following ten S1 stimuli, an S2 shock field created by a 10-msec square wave was delivered during the action potential plateau or during diastole through shock electrodes 1 cm on either side of the tissue. Four shock strengths creating field strengths of 1.7 +/- 0.1, 2.9 +/- 0.2, 6.1 +/- 0.6, and 8.8 +/- 0.9 V/cm were given for the same impalement. Both shock polarities were given at each shock strength. For shocks delivered during the action potential plateau, the magnitudes of the peak delta Vm caused by the above four potential gradients were 21.1 +/- 8.2, 33.6 +/- 13.6, 49.9 +/- 24.2, and 52.3 +/- 28.0 mV (P < 0.05 among the four groups) for the shocks causing depolarization and 37.9 +/- 14.2, 56.6 +/- 16.4, 83.1 +/- 19.4, and 92.9 +/- 29.1 mV (P < 0.05 among the four groups) for the shocks causing hyperpolarization. Though delta Vm increased as potential gradients increased, the relationship was not linear. The magnitude of hyperpolarization was 1.9 +/- 0.5 times that of depolarization when the shock polarity was reversed (P < 0.05). As potential gradients increased from 1.7 +/- 0.1 to 8.8 +/- 0.9 V/cm, the time constant of the membrane response decreased significantly from 3.5 +/- 1.8 to 1.6 +/- 0.7 msec for depolarizing shocks and from 6.0 +/- 3.1 to 3.4 +/- 1.9 msec for hyperpolarizing shocks (P < 0.01 vs depolarizing shocks). For shocks delivered during diastole, hyperpolarizing shocks induced triphasic changes in Vm during the shock, i.e., initial hyperpolarization, than depolarization, followed again by hyperpolarization. During the action potential plateau, the membrane response cannot be represented by a classic passive RC membrane model. During diastole, activation upstrokes occur even during hyperpolarization caused by shocks creating potential gradients between approximately 2 and 9 V/cm.