Double-balanced Passive Mixer Research Articles

Modified Broadband Ruthroff-Type Transmission Line Transformer Balun for Isolation-Enhanced Passive Mixer Design.

Generalized broadband operation facilitates multifunction or multiband highly integrated applications, such as modern transceiver systems, where ultra-wideband bidirectional passive mixers are favored to avoid a complex up/down-conversion scheme. In this paper, a modified Ruthroff-type transmission line transformer (TLT) balun is presented to enhance the isolation of the mixer from the local oscillator (LO) to the radio frequency (RF). Compared to the conventional methods, the proposed Ruthroff-type architecture adopts a combination of shunt capacitors and parallel coupled lines to improve the return loss at the LO port, thus effectively avoiding the area consumption for the diode-to-balun impedance transformation while simultaneously providing a suitable point for IF extraction. In addition, a parallel compensation technique consisting of an inductor and resistor is applied to the RF balun to significantly improve the amplitude/phase balance performance over a wide bandwidth. Benefiting from the aforementioned operations, an isolation-enhanced 8-30 GHz passive double-balanced mixer is designed as a proof-of-principle demonstration via 0.15-micrometer GaAs p-HEMT technology. It exhibits ultra-broadband performance with 7 dB average conversion loss and 50 dB LO-to-RF isolation under 15 dBm LO power. The monolithic microwave integrated circuit area is 0.96 × 1.68 mm2 including all pads.

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Today it is important to manufacture high quality integrated circuits which are insensitive to device mismatches. This paper presents an analysis of MOSFET transistors mismatches effect on the performance of UWB receiver front-end which constitute the most important part of Wireless Body Area Network sensor node. The receiver is based on Balun LNA with 25% fully differential double-balanced passive mixer. A PMOS and NMOS transistors mismatch models were proposed to determine LNA output offset voltage and mixer offset current respectively. The analysis result suggests that, to minimize NMOS current mismatch, and thus reducing second-order inter modulation distortion, the overdrive voltage must be maximized. A Monte Carlo and harmonic balance simulations were performed using 0.18µm CMOS process to evaluate the impact of mismatch as well as Vth mismatch on the receiver gain and IIP2. Simulation results show that IIP2 of the receiver is less sensitive to mixer NMOS mismatch but receiver gain is more sensitive. The receiver IIP2 confidence interval in case of NMOS mismatch is [24.674, 24.77]dBm and in case of NMOS Vth mismatch is [24.659, 24.857]dBm. This show the robustness of the proposed UWB receiver front end. Therefore the proposed circuit meets the requirement of UWB system perfectly which make it suitable for WBAN applications.

A 39-GHz High Image-Rejection Up-Conversion Mixer in 65-nm CMOS for 5G Communication

This brief presents an up-conversion mixer with high image rejection ratio (IRR) for 5G mmWave communication. To achieve broadband IRR at mmWave frequency with high area efficiency, a current-mode second-order tunable notch filter embedded in a cascode radio frequency (RF) buffer is proposed to realize tracking of the pole and zero frequencies with the switch capacitor array. To address the local oscillator (LO) leakage and even-harmonic distortion, a double-balanced passive mixer is adopted. For better isolation and lower insertion loss, a capacitor-inductor-capacitor (C-L-C) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\pi }$ </tex-math></inline-formula> -type impedance network is introduced in the mmWave T/R switch, realizing the equivalent lumped quarter wave transmission line with high area efficiency. Fabricated in a 65-nm CMOS process, the up-conversion mixer consumes 48.6 mW from a 1.2-V supply. Within the 3-dB bandwidth from 36 to 40.6 GHz, the mixer has a peak conversion gain of 0 dB, and its measured output 1-dB gain compression point (OP1dB) varies from −3 to −1.8 dBm. With the proposed tunable notch filter, the up-conversion mixer achieves a measured IRR of more than 53 dBc from 36 to 40.6 GHz, with a peak value of 58 dBc at 38.2 GHz.

Analysis and Optimization of Voltage-Driven Double-Balanced Passive Mixer for MICS Band Receiver

This paper presents analysis of a 25% duty-cycle fully-differential double-balanced passive mixer dedicated to medical implantable devices. The proposed passive mixer is part of a medical implant communication service (MICS) receiver front-end operating at 402–405[Formula: see text]MHz. By performing time-domain analysis, two LTI models have been developed to study the fully-differential double-balanced passive mixer: A simplified model and a complete model taking into account harmonic components. Both models account for the AC coupling capacitors at the mixer input and account for baseband voltage variation over one LO period. In this study it has been shown the ability of mixer input impedance matching by varying baseband resistor at the mixer output. The frequency of match can be controlled by varying the AC coupling capacitors and baseband capacitors. The performance of the proposed models was compared with that of the mixer and the results were very close. In particular, the results of simulations of the input impedance as a function of the baseband resistance and as a function of the IF frequency show the validity of the proposed models. The main parameters of the passive mixer such as input impedance, gain and noise figure (NF) were optimized taking into account the constraints of our application. The proposed mixer is designed to operate at LO frequency of 403.2[Formula: see text]MHz. Transistors size is optimized to meet the receiver specifications. The mixer realizes a conversion gain of 0[Formula: see text]dB and an NF of 4.8[Formula: see text]dB. Linearity simulations show 25.2[Formula: see text]dBm for IIP3 and 9.66[Formula: see text]dBm for [Formula: see text]dB. The mixer consumes 1.44[Formula: see text]pW without LO circuit.

A 2–18 GHz Compressed Sensing Receiver With Broadband LO Chain in 0.13-$\mu$ m BiCMOS

We present an integrated 2–18 GHz four-channel compressed sensing receiver (CSRX), which performs a $128.5\times $ sub-Nyquist acquisition with 36-Gb/s pseudorandom bit sequence (PRBS) generators in 0.13- $\mu \text{m}$ BiCMOS. The integrated four-channel CSRX consists of broadband receiver chains, each of which includes a distributed RF buffer that operates as an active balun at 2–18 GHz, followed by a double-balanced passive mixer for high local-oscillator (LO)-to-intermediate frequency (IF) isolation at the IF band, and a 700-MHz variable gain amplifier (VGA). Four independent 36-Gb/s PRBS generators are integrated to perform the compressed sensing by mixing the PRBS signal as the random modulator. To deliver the generated wideband PRBS signal to the mixer, the LO driver conducts band-equalization by applying a shunt-shunt feedback amplifier to compensate for the high-frequency degradation of the PRBS LO tones through the LO generation stage. The chip consumes 195 mA per channel with a 2.5-V supply.

A Ka Band FMCW Transceiver Front-End With 2-GHz Bandwidth in 65-nm CMOS

A fully integrated Ka band frequency modulation continuous wave single-chip radar transceiver front-end is proposed in 65-nm CMOS technology. By utilizing VCO with multi-biasing varactor banks, the critical bandwidth and linearity have been improved. To address the challenges of losses and complexities in local oscillator (LO) distribution chain, a three-way transformer-based power divider is proposed and implemented to split the input differential signals to three outputs, in three orthogonal directions. The poly phase filter is also used to obtain the in-phase and quadrature LO signals. To minimize the reflections between the poly phase filter and the following stages, a 1:2 transformer is inserted to provide sufficient matching. For the receiver part, differential cascode amplifier with neutralization capacitors is implemented in the low noise amplifier to obtain gain and stability. By utilizing double balanced passive mixers, noise performances of I/Q paths are improved at low intermediate frequency. The transceiver demonstrates 4.4-dBm output power, 2-GHz bandwidth with 7.5-cm range resolution, and 5.9–7.5 dB double side band noise figure at 4 MHz. The whole transceiver front-end consumes 132 mW from 1.2 V and 2.16 mm2 die size.

A 2.4-GHz High Conversion Gain Passive Mixer Using $Q$ -Boosted $\pi $ -Type LCL Matching Networks in 90-nm CMOS

In this letter, a 2.4-GHz double-balanced passive mixer is presented which offers high conversion gain. The improvement of the local oscillator (LO) and RF input voltage is obtained as a ${Q}$ -factor by the LC resonance of the $\pi $ -type inductor-capacitor-inductor matching network. This passive mixer with a high conversion gain is fabricated using 90-nm-1P5M CMOS technology. The mixer down converts a 2.4-GHz RF frequency to an intermediate frequency of 10 MHz. The measurement results show a 6.5-dB voltage conversion gain, a −6 dBm 1-dB compression point when LO power is −5 dBm and zero dc power consumption.

High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process

This brief presents a new design technique for high-efficiency CMOS millimeter-wave power amplifiers (PAs) and the implementations of a two-stage moderate-power PA, a three-stage high-power PA, and a transmitter all working over 68–78 GHz. The proposed PAs adopt nMOS capacitors connected at the gates of the transistors of the last one or two amplifying stages to compensate for the gate capacitance variation over a large signal swing, thus improving the linearity and the power efficiency. Implemented in a 65-nm CMOS process, the two-stage PA achieves a peak power-added efficiency (PAE) of 24.2%, a maximum gain of 17 dB, and a 3-dB bandwidth from 68 to 78 GHz. The three-stage PA achieves a saturated power (Psat) of 17.3 dBm, a peak PAE of 18.9%, and a maximum gain of 21.4 dB. The transmitter consisting of the three-stage PA and a passive double-balanced mixer with local oscillator shaping technique achieves a Psat of 14.6 dBm, a peak efficiency of 13.9%, and a conversion gain of 15.6 dB.

NMOS Device Optimization for the Design of a W-Band Double-Balanced Resistive Mixer

This letter describes the implementation of NMOS devices in a passive ring mixer whose operating frequency reaches device's cut-off frequency. Conversion gain, linearity and required LO power are discussed regarding device geometry using simple analytic formulas and electrical simulations. The mixer is then embedded in a down-converter including RF, LO and IF buffers and integrated in a 130 nm BiCMOS SiGe technology. Measurements indicate a conversion gain of 14.5 dB at 76.8 GHz, an output-referred 1 dB compression point of -10 dBm and a DSB noise figure of 6.3 dB confirming the interest of double-balanced passive mixers at millimeter-wave frequencies.

Design of a broadband passive X-band double-balanced mixer in SiGe HBT technology

In this paper, a passive double-balanced mixer in SiGe HBT technology is presented. Owing to lack of suitable passive mixing elements in the technology, the mixing elements are formed by diode-connected HBTs. The mixer uses lumped element Marchand baluns on both the local oscillator (LO) and the radio frequency (RF) port. A break out of the Marchand balun is measured. This demonstrates good phase and magnitude match of 0.7° and 0.11 dB, respectively. The Marchand baluns are broadband with a measured 3 dB bandwidth of 6.4 GHz, while still having a magnitude imbalance better than 0.4 dB and a phase imbalance better than 5°. Unfortunately with a rather high loss of 2.5 dB, mainly due to the low Q-factor of the inductors used. The mixer is optimized for use in doppler radars and is highly linear with a 1 dB compression point above 12 dBm IIP2of 66 dBm. The conversion gain at the center frequency of 8.5 GHz is −9.8 dB at an LO drive level of 15 dBm. The whole mixer is very broadband with 3 dB bandwidth from 7 to 12 GHz covering the entire X-band. The LO–IF, RF–IF, and RF–LO isolation is better than 46, 36, and 36 dB, respectively, in the entire band of operation.

A CMOS 77-GHz Receiver Front-End for Automotive Radar

This paper presents the design of a receiver (Rx) front-end for automotive radar application operating at 76-77 GHz. The Rx employs a double conversion architecture, which consists of a five-stage low-noise amplifier (LNA), a sub-harmonic mixer (SHM), and a double-balanced passive mixer (PSM). By adopting this architecture, millimeter-wave frequency synthesizer design can be relaxed. In the LNA layout, the output of each stage is positioned close to the input of the follow stage, thus creating a LC resonance load. As a result, complex interstage matching networks is simplified. The SHM driven by a 38-GHz local oscillator (LO) is adopted to avoid push/pull effect and power consumption of the voltage-controlled oscillator. A PSM is utilized for the second conversion since it consumes no dc current and has low flickering noise. To connect the singled-ended LNA and SHM, a 77-GHz balun is designed; and for driving the SHM, two 38-GHz baluns and an in-phase/quadrature coupler to provide quadrature 38-GHz LO are designed. The proposed Rx is implemented in a 65-nm CMOS technology and measurement results show 16-dB voltage gain and 13-dB calculated noise figure while dissipating 23.5 mA from a black 1.2-V supply.

Design of a Dual-Frequency Retrodirective Array

A dual-frequency retrodirective array is proposed. By using two separated antenna arrays and double balanced passive mixers, the proposed system can achieve dual-frequency retrodirectivity in a bidirectional way. The low-frequency interrogating signal can be retransmitted at the high frequency, and it can also work in a reverse order. The proposed array has the advantages of low cost and high isolation between interrogating and retransmitting signals. The bidirectional characteristic can make it very useful in the two-way communication system. A four-element prototype is designed and fabricated. Measured results show good retrodirective performance.

Design of a low-power ZigBee receiver front-end for wireless sensors

This paper describes the design of a low cost, low-power ZigBee receiver for wireless sensor networks. The receiver consists of a low-noise amplifier, a pair of down-conversion mixers, and a pair of variable-gain low-pass filters. The LNA has a single-ended input, eliminating the need for an off-chip balun, a differential output, allowing it to drive a double-balanced mixer, and it uses noise cancellation to improve its noise performance. The mixers are double-balanced passive mixers to improve the receiver linearity and decrease its power consumption and flicker noise. Finally, the filter is a third-order Butterworth Gm–C filter with a variable input transconductor to provide gain programmability for the receiver. The design is made using 130nm CMOS technology with 1.2V supply. Simulation results show that the receiver can achieve a sensitivity level of −97dBm while consuming only 6mA.

A Single–Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and ${+}$90 dBm IIP2

This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with DigRF interface that supports 10 WCDMA bands (I, II, III, IV, V, VI, VIII, IX, X, XI) and 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900). The receiver is part of a single-chip SAW-less transceiver reference platform IC for mass-market smartphones, which has been designed to meet Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The novel receiver core consists of a single-stage transconductance amplifier (TCA) with large gain control range, a current commutating passive mixer enhanced for automatic on chip IIP2 calibration with 25% duty-cycle LO injection and threshold adjust, and current-input complex Direct Coupled Filter (DCF). The low noise TCAs are designed without inductive loads to save area. A self-contained on chip automatic IIP2 calibration system with algorithm routine, implemented in firmware, is used to optimize IIP2 performance. This topology eliminates the external LNA, inter-stage SAW filter and transimpedance amplifier (TZA) in conventional WCDMA designs and results in current drain and die area savings as well as improved noise. The 25% duty-cycle LO injection, with threshold adjustment, into a current driven passive double-balanced mixer results in 3 dB additional gain, lower noise figure and lower intermodulation distortion. Large signal blocking and 1/f noise performance are improved significantly by eliminating the 0 and 180deg LO signal crossover at the mixer. The full receiver achieves 2.2 dB/2.39 dB simplex/duplex NF (with - 24.5 dBm TX leakage), > 90 dBm complex two-tone IIP2, 60 dB gain and - 1/+ 5 dBm half/full-duplex image IIP3. The receiver core consumes only 15.1 mA from a 1.5 V supply.