Pass Transistor Research Articles

A Novel Quaternary Half Subtractor Using 2:1 Multiplexer

Multiple-valued logic (MVL) is a logic in which there are more than two truth values. MVL is used due to difficulty in interconnection problems in binary system. Carbon nanotube field-effect transistors (CNTFET) is used to design the Quaternary Half Subtractor (QHS) circuit. Sub blocks of Module (0210), Module (1021), Module (2102), Module (3210) using three supply voltage devices and Quaternary Multiplexer 2:1 using pass transistor have designed in this paper. Therefore, compared to existing designs, less no. of transistors are needed. Comparing proposed Half subtractor using 4:1 MUX modules to current one’s reveals that the 2:1 multiplexer-based method leads in lower power usage. These proposed designs have proven to work satisfactorily under a variety of operating situations, including power, delay, and power delay product (PDP).

Design of Area-Efficient and Low-Power Magnetic Full Adder

Complementary metal oxide semiconductor (CMOS) is an extensively used promising technology for developing integrated circuits, such as memory chips, microprocessors and microcontrollers with high noise immunity. However, deep scaling of CMOS technology ([Formula: see text] [Formula: see text]nm) suffers from various impediments at the device and architectural level, namely high leakage current, increased radiation sensitivity, more die area and dynamic power dissipation. To overcome these limitations of CMOS devices, logic-in-memory (LIM) structures have been developed with spin-based devices like Magnetic Tunnel Junctions (MTJs). MTJs are not affected by external particles and feature zero standby power. The MTJs in magnetic logic circuit and magnetic random-access memory (MRAM) applications are robust against radiation, high speed, low leakage power, nonvolatility and easily compatible with the back end. Existing magnetic full adder (MFA) techniques require augmented circuits for seamless operation. A major drawback in the existing MFA structure is the data loss due to single event upset (SEU) and poor sensitivity of pre-charge sense amplifiers (PCSAs) to input arrival timing. This paper proposes an MTJ-based nonvolatile magnetic full adder (NV-MFA) using 10T logic to address the above issues. The output buffer circuit is designed with a read-write parallel switching (RWPS) writing circuit based on spin orbit torque (SOT). The proposed circuit is more immune to the fault occurrence compared with the existing pass transistor and PCSA-based MFA logic. It leads to reduced power dissipation, die area and delay. Perpendicular anisotropy MTJ (CoFeB/MgO/CoFeB) model is chosen for the MTJ structure. It is suitable for efficient MRAM structure. The transient response is verified on Cadence virtuoso using 45[Formula: see text]nm gpdk CMOS technology. The simulation analysis shows the performance is enhanced with fault-free data output and improved reliability compared with previous MFAs.

Design of a Low-Power Dynamic Latched Comparator for Biomedical Applications

Abstract The latched comparator is a fundamental component of all ADC topologies. Thermal noise, kickback noise, and offset voltage impact the energy efficiency of the comparator significantly. In cardiac IMD ADCs, latched comparator kickback noise may impact resolution, accuracy, and settling time. This paper describes the design and development of an a low-power dynamic latched comparator optimised for biomedical applications and running at 1V. The suggested comparator is achieved on a 45 nm CMOS technology node, having the main goal of reducing kickback noise. The main concept of the recommended comparator has been utilizing the novel resetting approach and kickback noise reduction approach to preserve the charge and kickback noise, respectively. This approach aids in minimizing delay, power consumption, and kickback noise using shared charging logic. The charging-sharing technique involves using a single-pass transistor positioned across two output nodes. The pass transistor distributes the charge evenly across two output nodes throughout the reset phase. Due to the shared charging of the load capacitances, the voltage at the output nodes would not drop under the threshold value. As a result, the input signal could be evaluated more quickly during the regenerative stage. The comparator's delay is calculated using a rigorous statistical analysis considering the circuit's random factors. The offset of the proposed comparator is verified using thorough Monte Carlo simulations. The comparator reduces power while preserving noise. Also, the measured simulation results of recommended comparator outperform state-of-the-art comparators regarding kickback noise, delay, power consumption, and power delay product (PDP). The input voltage inversely affects the comparator's delay. Further, the simulation shows that the comparator consumes 9.36μW at 1 V and 1GHz sampling frequency. The simulation results confirm that the suggested comparator effectively reduces power consumption by atleast 66.98%. The proposed comparator has less PDP value by 44.44%. Also, suggested comparator effectively reduces offset voltage by 7.6% but with a corresponding increase in the area by 5%. Additionally, the comparator successfully reduces kickback noise by 44.6%. The obtained results are not silicon proven and bound to be in the pre-silicon stage. The low-power behaviour of the suggested technique is validated using analytical derivations, PVT corner analysis, and post-layout simulation.

High speed and low power hybrid adder using 22 nm SG-TG FinFET

Abstract This paper demonstrates a new 22-T (transistor) hybrid adder for low-power applications using 22 nm shorted gate (SG) tri-gate (TG) FinFET technology. Large conducting channels and increased gate control make FinFET suitable for high-speed low-power computing circuits. The proposed hybrid adder is designed using pass transistor and CMOS logic. Also, it adopts the state-of-the-art techniques of dynamic leakage balancing on the ground path and stacking ground transistors that reduce parasitic effects and increase the speed of the logic transitions compared to traditional designs. Extensive simulations were executed to characterize for PDP (Power Delay Product), power dissipation, and delay of the hybrid adder circuit. From the Monte Carlo analysis, the robustness and efficiency of the circuit are also observable for minimum variation in power and delay due to process voltage and temperature (PVT) variations. Besides, concerning the supply variability and temperature, the circuit shows excellent stability by keeping the power consumption and delay performance consistent. The proposed 22-T hybrid adder using 22 nm SG-TG FinFET are very well-suited in low power and high-speed processors showing highly stable behaviour with reduced process variability.

A wideband high-PSR OCL LDO using a gain-relaxed OTA featuring dynamic complex zeros frequency compensation

This article proposes an Output-Capacitor-Less (OCL) Low-Dropout (LDO) regulator with an assisted positive feedback loop technique, which mimics a negative resistance, along with a single common-gate stage. Conventional techniques utilize multistage high-gain OTA to achieve a high DC loop gain. However, such an OTA suffers from high power consumption and sophisticated frequency compensation mechanisms. Instead, the use of a single-stage relatively low-gain OTA helps to extend the bandwidth. Then, the overall DC loop gain is maximized by the proposal of a novel negative resistance circuit. To further improve the PSR, a bulk-driven ripple canceling path that is insensitive to process corners is proposed making the LDO suitable for high-PSR applications. Stability is another challenge in the design of OCL LDOs due to its associated complex poles. We propose a new frequency compensation technique by introducing two complex zeros to eliminate these complex poles. Hence, the overall stability is improved. Since these complex poles location vary from light to heavy loads, the proposed zeros dynamically change accordingly. Besides, this suggested mechanism has been analyzed using the generalized time-and-transfer constants (TTCs) circuit analysis technique. Under heavy load conditions, the suggested LDO has attained phase and gain margins of 62.8° and 29 dB, respectively. Moreover, Monte Carlo simulations along with process and temperature variations have been investigated to prove the reliability of such a frequency compensation technique. The proposed LDO has been implemented in 65 nm CMOS technology node with a short pass transistor length of 100nm. The simulation results reveals that the LDO draws 299.4μA of quiescent current under light load conditions and 296.8μA under heavy load conditions (including the bandgap voltage reference). The suggested LDO functions at 1.2V supply voltage, delivers 0.93V output voltage and can handle a load current up to 10mA with load regulation of 17μV/mA, line regulation of 2.22mV/V, and PSR of −48.7dB at low frequencies. The PSR at 1MHz is at least −32.5dB which is superior to the reported recent LDOs.

Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application

Advances in wearable technology, IoT, and mobile applications have increased the demand for ultra-low-power electronic devices. Adiabatic Logic Circuit (ALC) is a design technique utilized in digital circuits to decrease the power consumption by decreasing the dynamic power dissipation. Current technologies face challenges in achieving both high performance and ultra-low power consumption. This research work introduces a novel approach in digital circuit design, specifically the Gate All-around Carbon Nanotube Field Effect Transistor with Discrepancy Cascode Pass Transistor Adiabatic Logic (GAA-CNTFET-DCPTAL), tailored for ultra-low power applications. This design operates efficiently with a four-phase Power Clock (PC) and demonstrates remarkable performance by achieving operation frequencies of up to 1 GHz while minimizing energy dissipation. GAA-CNTFET provides superior electrostatic control and high carrier mobility, reducing leakage currents and enhancing switching speeds. Simultaneously, Discrepancy Cascode Pass Transistor Adiabatic Logic (DCPTAL) uses adiabatic logic principles and a cascode structure to minimize energy dissipation during switching events. The technology node of proposed model is 10 nm. The software used for assessment is HSPICE is used for the simulation and validation of the proposed design. The proposed GAA-design attains 25.36 %, 14.28 %, and 16.06 % lower average power analyzed with existing techniques, such as Design with Evaluation of Clocked Differential Adiabatic Logic Families for the applications of low Power (DE-CDAL-LPA), Adiabatic logic-base strong ARM comparator for ultra-low power applications (AL-SARM-ULPA) and Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC with Embedded Applications (2PADCL-ULP-VLSI) respectively.

Design and Implementation of PLL with Dead Zone-Less Low-Power Phase Frequency Detector

This project introduces a Phase-Frequency Detector (PFD) that includes a dedicated circuit for removing the dead zone. This design utilizes Pass Transistor Logic (PTL) and Delay Cells (DCs) to effectively address this issue. Additionally, a Low-Pass Filter is integrated into the system and connected with charge pump, employing a technique that replaces resistors with transistors, thereby significantly reducing the overall circuit area. Furthermore, a Phase-Locked Loop (PLL) serves to eliminate the dead zone and significantly reduce the circuit's size. This project aims to advance circuit design methodologies by enhancing performance and minimizing area requirements.

A Power-Efficient Envelope-Detector-Less Amplitude-Shift-Keying Forward Telemetry for Wirelessly Powered Biomedical Devices.

This paper proposes an envelope-detector-less (EDL) amplitude-shift-keying (ASK) forward telemetry (FT) demodulator for wireless power/data transfer (WPDT) systems. The EDL ASK FT demodulator can substitute bulky and power-hungry components, which are an envelope detector and an analog comparator in the conventional ASK FT demodulator, with a digital controller, reducing both power dissipation and chip area. The proposed demodulator shares the gate control signals of pass transistors, which are used in an ac-dc regulator for wireless power reception, to maintain a constant load voltage while efficiently demodulating the forward telemetry data. Also, a proposed digital cleaner in the EDL demodulator refines this control signal into a wide pulse without suffering from resonant frequency noise, while a synchronizer can align its frequency with the data rate and resonant frequency. The 0.25-μm CMOS prototype chip of the proposed power-path-less EDL ASK FT demodulator, equipped with the ac-dc regulator, demonstrates a significant 38.2% reduction in power dissipation compared to the conventional ASK FT demodulator. Moreover, the EDL ASK FT demodulator occupies only 0.023-mm2 silicon area and achieves a low bit error rate (BER) less than 10-4 while maintaining a regulated voltage of 4.5 V on the load.

Full-Swing Nanosecond Delay Hybrid Level Shifter for Time-Critical Applications

A crucial component of digital integrated circuits with numerous power domains is the level shifter (LS). The traditional topologies are currently the mirror LS and cross-coupled LS. For full-swing level conversions from extremely low voltage to the nominal voltage of the supply, ahybrid LS is proposed in this paper, which is a combination of the current mirror LS and cross-coupled LS with a swing-aware output inverter. The proposed LS circuit is designed to ensure full swing, static current-free, and limited current-contention level conversions by preserving the benefits of the current mirror and cross-coupled LS, and using them to eliminate each other’s shortcomings. The proposed hybrid LS is designed and implemented by using 45-nm technology in Cadence Virtuoso tool. Pass transistors and current limiters with multiple thresholds are included for the suggested LS. The proposed LS provides voltage conversion from 0.10 V to 1.20 V. At alevel-shifting voltage of 0.20 V, the proposed hybrid LS at 1 MHz input frequency demonstrates a delay of 8.38 ns, an average power consumption of 3.81 µW, and an energy per transition of 26.64 fJ. Additionally, the suggested LS has low delay, good supply voltage scaling, and delay scalability.

Design of low delay low power hybrid logic based flip-flop using FinFET

The need for a low-power and high-speed technology for computation of digital signals is rising due to the fast growth of technological innovations. Flip-flops serve as fundamental elements in signal processing technologies. Hybrid logic has great potential for constructing flip-flop circuits because of its minimal transistor count as well as low-power properties.The present investigation presents a design for a tiny and low-power hybrid flip-flop that operates fully statically. The design has been developed by utilizing different circuitry-reduction techniques. It incorporates a hybrid logic approach combining pass transistor logic to decrease circuit complexity. The ongoing work utilizes a hybrid logic with low delay and low power to generate flip-flops. The proposed flip-flop design significantly decreases latency compared to the existing master-slave flip-flops. This flip-flop remains immune to clock overloading, resulting in reduced power consumption. Reducing the quantity of PFET (P-channel Field Effect Transistor) transistors enhances the circuit's delay, area, and power consumption. Implementing these circuit optimization techniques yields several benefits, such as reduced CLOCK-to-OUT and DIN-to-OUT node delays, decreased average power consumption, lower leakage power, and a transistor count of only 18. The results were achieved using Cadence Virtuoso at 18 nm finFET technology, with varied process corners, supply voltages ranging from 0.7 V to 1 V, and temperatures ranging from -50 °C to 75 °C. This study also presents a Monte Carlo simulation of power consumption, leakage, and delay for the suggested flip-flop. According to the simulations, the recommended flip-flop exhibits exceptional stability. The recommended flip-flop has lower power usage by at least 17.95 % compared to standard architectures due to the lower number of PFET transistors.

Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design

CNTFETs are a shows potential choice for traditional CMOS technology due to their potential for lesser power consumption and superior performance. In the present paper, a new 1-bit hybrid full adder has been deliberated and proposed using both pass transistor (PT) and transmission gate logics (TGL), which utilizes a total of 16 transistors. The combination of PT and TGL can lead to improved power efficiency, reduced delay, and enhanced circuit performance in various VLSI applications. For 0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0748 μW, which is to be an exceptionally low value with a lesser delay of 7.586 Ps and the power-delay-product (PDP) of 0.5674 aJ. The results obtained from this analysis demonstrate the power efficiency, speed, and overall performance of the proposed full adder design. The combination of 32-nm CNTFET technology, deliberate circuit design choices, and the use of specific logic elements (CMOS inverters and strong transmission gates) contributes to the reported characteristics. Using a 0.9 V supply voltage and 32-nm Stanford CNTFET Model technology, the suggested 1-bit adder circuit's concert was investigated using the Mentor Graphics Tool. Finally, using the proposed 1-bit full adder circuit, an N-bit ripple carry adder (N=8, 16 & 32) is implemented and demonstrated. The Simulation results of the 8-bit RCA with a power consumption of 0.373 μW, the delay is 16.852 Ps and the PDP is 6.2857 aJ. These results show that proposed RCA’s have better performance compared to the already reported designs in terms of performance, speed, and power economy.

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

High PSR external capacitor‐less LDO with adaptive supply‐ripple cancellation technique

AbstractThis work presents an external capacitor‐less low‐dropout regulator (CL‐LDO) with high power supply rejection (PSR) over a wide frequency and load current ( ) range. The high PSR is implemented with an adaptive supply‐ripple cancellation (ASRC) technique. The proposed ASRC circuit consists of a buffer with diode‐connected structure and an adjusting unit. The novel buffer introduces the supply ripple through the diode‐connected transistor to the gate of the pass transistor, enhancing the PSR in the range of 1 MHz. Additionally, the adjusting unit trims the current of the buffer continuously according to the magnitude of to optimize the PSR adaptively. Designed in a 55 nm CMOS process with an input voltage of 1.4 V, the proposed LDO achieves −69 dB and −55 dB PSR at 100 KHz and 1 MHz for 50 mA of , respectively. Moreover, the maximum current efficiency of the LDO is 99.8% at a full of 50 mA.

Design and optimization of phase frequency detector through Taguchi and ANOVA statistical techniques for fast settling low power frequency synthesizer

In this work, a novel phase frequency detector (PFD) architecture using pass transistor logic is proposed. The circuit does not have a reset path, resulting in the elimination of blind zone and dead zone. The ϕ-V characteristics of the PFD were found to have better linearity across the range of −π to π due to the absence of blind and dead zones. The Taguchi and ANOVA statistical techniques were used to optimize the PFD. The optimized PFD exhibited a phase noise of −142.24 dBc/Hz, consumed 5.64 μW of power and had a maximum operating frequency of 5.25 GHz, and a delay of 10.65 ps. Using this PFD, a GHz-range synthesizer was designed, and its performance characteristics were obtained from circuit simulations using CADENCE Virtuoso. The synthesizer had a power consumption of 4.25 mW at a supply of 1.8 V, achieved a lock time of 2.95μs, and could generate frequencies ranging from 0.1 GHz to 4.75 GHz while occupying a chip area of 0.013 mm2. Moreover, the work introduced a new figure of merit, FoM. The synthesizer has potential applications in various devices such as radio receivers, televisions, mobile phones, satellite receivers, and GPS systems.

A Low Quiescent Current Fast Transient LDO Regulator With Segmented Pass Transistors

A Low Quiescent Current Fast Transient LDO Regulator With Segmented Pass Transistors

Performance Analysis of Hybrid Comparator using 45nm Technology

In the present real-time world, due to the improvements and innovations of System on Chip (SoC) applications, there is a requirement to integrate multiple technology design topologies. The electronic system design is classified as analog, digital, and mixed-signal design. The comparator is the major building block used in the datapath of System on Chip (SoC) application device. The usage of these devices depends on not only functionality but also on the non-functionality parameters considering different performance estimation metrics. The nonfunctional performance metrics for a transistor level design depends on the number of transistors, switching activities of logic level voltages and delay between input and outputs. These performance metrics are improved by considering the multiple logic families for multiple output generations instead of using a single logic family topology. The comparator is the major component in the arithmetic circuits for SoC applications and can be realized by using various design topologies. The vividly used topologies are Conventional CMOS logic, Pass Transistor Logic (PTL), Gate Diffusion Input (GDI) Logic, Stacking technique, Quantum-dot cellular automata, etc. The selection of the design topology for the comparator is made based on the non-functional parameters. The performance of non-functional parameters is improved by combining the topology architectures of different design techniques. In this paper, the comparator is designed using conventional CMOS logic, PTL, GDI, and a hybridized topology for best performance and the same is implemented using 45nm technology. These circuits are designed by using Cadence Virtuoso Electronic Design Automation (EDA) design tools. Non-functional performance parameters are analyzed for different topologies. Index Terms: VLSI Design, Comparator, Datapath, EDA tools, CMOS Logic, GDI Logic, PTL Logic.

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness.

WITHDRAWN: Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

In this paper, we propose a hybrid full-swing adder (HFSA) circuit that uses the hybrid full-swing logic (HFSL) technique, which consists of 20 transistors. This circuit relies heavily on a 12-transistor XOR-XNOR circuit to optimize the area and power. Our novel XOR-XNOR circuit plays a crucial role in achieving high-efficiency HFSA circuits. It integrates 2-to-1 multiplexers, pass transistor logic, and inverters to deliver glitch-free full-swing outputs. We compared the efficiency and practicality of our design with those of 10 alternatives by considering their performances and characteristics. Our novel XOR-XNOR circuit surpassed its counterparts with an exceptional chip area reduction of 14.14–28.01 %, an average power of 2.44 μW, and remarkably low delays of 25.88 and 24.87 ps. Notably, the proposed full adder achieved a chip area reduction of 11.30–49.69 %, 3.582 μW power, and a 72.66 ps delay. It emphasizes large-scale structures, such as 4-bit to 64-bit full adders, implemented using cascaded designs with a novel ripple carry adder. Using multipoint and Monte Carlo analysis in the ADEXL design suite to ensure the reliability of all circuits using the Cadence Virtuoso with the GPDK45 nm technology. The proposed method is an alternative to high-speed electronic systems with potential benefits.