Code Partitioning Research Articles

Equivalent formulations and necessary optimality conditions for the Lennard–Jones problem

The minimization of molecular potential energy functions is one of the most challenging, unsolved nonconvex global optimization problems and plays an important role in the determination of stable states of certain classes of molecular clusters and proteins. In this paper, some equivalent formulations and necessary optimality conditions for the minimization of the Lennard–Jones potential energy function are presented. A new strategy, the code partition algorithm, which is based on a bilevel optimization formulation, is proposed for searching for an extremal Lennard–Jones code. The convergence of the code partition algorithm is proved and some computational results are reported.

Wavelet-based very low bit-rate video coding using image warping and overlapped block motion compensation

The authors present an algorithm for very low bit-rate video coding that combines new ideas in motion estimation, wavelet filter design, and wavelet-based coding techniques. A new motion compensation technique using image warping and overlapped block motion compensation is proposed to reduce temporal redundancies in a given image sequence. This combined motion model has the advantage of representing more complex motion than simple block matching schemes. To further improve the quality of the temporal prediction, an adaptive grid with variable density according to the varying motion activity of a given scene is generated. An adaptively switched high-quality texture interpolation is employed to cope with the problem of fractional displacements in such a way that both objective and subjective reconstruction quality is improved. Spatial decorrelation of the motion compensated residual images is performed using an one-parametric family of biorthogonal infinite impulse response (IIR) wavelet filters coupled with the highly efficient pre-coding scheme of ‘partitioning, aggregation and conditional coding’ (PACC). Experimental results demonstrate significant improvements in objective quality of 1.0–2.3 dB PSNR in comparison to the H.263+ test model TMN10 using advanced coding options. In addition, the authors' intracoding method provides a performance gain of 0.5 dB PSNR on the average for a test suite of various still images when compared to the emerging still image coding standard JPEG-2000.

Dynamic code partitioning for clustered architectures

Recent works^(1) show that delays introduced in the issue and bypass logic will become critical for wide issue superscalar processors. One of the proposed solutions is clustering the processor core. Clustered architectures benefit from a less complex partitioned processor core and thus, incur in less critical delays. In this paper, we propose a dynamic instruction steering logic for these clustered architectures that decides at decode time the cluster where each instruction is executed. The performance of clustered architectures depends on the inter-cluster communication overhead and the workload balance. We present a scheme that uses runtime information to optimize the trade-off between these figures. The evaluation shows that this scheme can achieve an average speed-up of 35% over a conventional 8-way issue (4eint+4efp) machine and that it outperforms other previous proposals, either static or dynamic.

Error-resilient coding in JPEG-2000 and MPEG-4

The rapid growth of mobile communications and the widespread access to information via the Internet have resulted in a strong demand for robust transmission of compressed image and video data for various multimedia applications and services. The challenge of robust transmission is to protect the compressed image/video data against hostile channel conditions while bringing little impact on bandwidth efficiency. This paper addresses this critical problem and provides an overview of the error-resilient approaches that have been evaluated and inserted into the emerging JPEG-2000 wavelet-based image coding standard. We also review the state-of-the-art techniques adopted in the MPEG-4 standard for robust transmission of video and still texture data. These techniques include resynchronization strategies, data partitioning, reversible VLCs, and header extension codes. The performance of these approaches under various channel conditions is evaluated.

An efficient heuristic for code partitioning

In this paper, we propose a heuristic for code partitioning for distributed memory multiprocessors (DMMs). Our method is data-flow based where all levels of parallelism can potentially be exploited. Given a weighted directed acyclic graph (DAG) representation of the program, our partitioning algorithm automatically determines the granularity of parallelism by partitioning the graph into tasks to be scheduled on the DMM. The granularity of parallelism depends only on the program to be executed and on the target machine parameters. The output of our algorithm is passed on as input to the scheduling phase. Unlike the scheduling problem as defined by Yang [A. Gerasoulis, T. Yang, IEEE Transactions on Parallel and Distributed Systems 4 (6) (1993) 686–701; T. Yang, Ph.D. Thesis, Rutgers University, New Brunswick, NJ, May 1993; T. Yang, A. Gerasoulis, IEEE Transactions on Parallel and Distributed Systems 5 (9) (1994) 951–967], the method presented in this paper uses task merging rather than task clustering. Finding an optimal solution to this problem is NP-complete. Due to the high cost of graph algorithms, it is nearly impossible to come up with close to optimal solutions that do not have very high cost (higher order polynomial). Therefore, our goal is to find a heuristic that gives good performance, and that has relatively low cost. Given a DAG with E edges and N nodes, the time complexity of our partitioning algorithm is O( E· N 3) in the worst case. For some cases, the average time complexity of the algorithm is O( N( E+ N)).

Intermediacy Prediction for High Speed Berger Code Checkers

We present an intermediacy prediction method that can be used to designhigh speed checkers for Berger codes, as well as for any other unordered code. In the proposed method, the received information and check bits are processed simultaneously toward an intermediate result. A two-rail code checker is then used to compare the two versions of such an intermediate result. Recall that, in conventional checkers for unordered codes, the received check bits remain idle until the received information bits are converted to the re-generated check bits. Therefore, our proposed intermediacy prediction method allows a checker's speed improvement. We show the application of our method to two well-Bergercode checker architectural solutions: (1) the threshold function based implementation, and (2) the Berger code partitioning design. We have verified that, as expected, the proposed method can improve the detecting speed of these existing solutions with moderate or minimum increase, and sometimes decrease, in hardware complexity.

Compilation techniques for parallel systems

Over the past two decades tremendous progress has been made in both the design of parallel architectures and the compilers needed for exploiting parallelism on such architectures. In this paper we summarize the advances in compilation techniques for uncovering and effectively exploiting parallelism at various levels of granularity. We begin by describing the program analysis techniques through which parallelism is detected and expressed in form of a program representation. Next compilation techniques for scheduling instruction level parallelism (ILP) are discussed along with the relationship between the nature of compiler support and type of processor architecture. Compilation techniques for exploiting loop and task level parallelism on shared-memory multiprocessors (SMPs) are summarized. Locality optimizations that must be used in conjunction with parallelization techniques for achieving high performance on machines with complex memory hierarchies are also discussed. Finally we provide an overview of compilation techniques for distributed memory machines that must perform partitioning of both code and data for parallel execution. Communication optimization and code generation issues that are unique to such compilers are also briefly discussed.

A Computation+Communication Load Balanced Loop Partitioning Method for Distributed Memory Systems

Due to a significant communication overhead of sending and receiving data, the loop partitioning approaches on distributed memory systems must guarantee not just the computation load balance but computation+communication load balance. The previous approaches in loop partitioning have achieved a communication-free, computation load balanced iteration space partitioning solution for a limited subset of DOALL loops. But a large category of DOALL loops inevitably result in communication and the trade-offs between computation and communication must be carefully analyzed for these loops in order to balance out the combined computation time and communication overheads. In this work, we describe a partitioning approach based on the above motivation for the general cases of DOALL loops. Our goal is to achieve a computation+communication load balanced partitioning through static data and iteration space distribution. Our approach first performs partitioning of iteration and data spaces of a loop nest by analyzing communication and parallelism; it then performs architecture-dependent analysis to adjust the granularity of partitions, load balance each partition with respect to total computation+communication, and then performs mapping of partitions onto the available number of processors. This multiphase partitioning method works as follows. First, the code partitioning phase analyzes the references in the body of the DOALL loop nest and determines a set of directions for reducing a larger degree of communication by trading a lesser degree of parallelism. The partitioning is carried out in the iteration space of the loop by cyclically following a set of direction vectors such that the data references are maximally localized and reused, eliminating a larger communication volume than parallelism. We then perform data space partitioning based on a new larger partition owns rule to minimize the communication overhead for a compute intensive partition by localizing its references relatively more than a smaller noncompute intensive partition. A partition interaction graph is then constructed which is used by the architecture-dependent analysis phase to merge the partitions to achieve granularity adjustment, computation+communication load balance, and mapping on the actual number of available processors. Relevant theory and algorithms are developed along with a performance evaluation on the Cray T3D.

Adapting to Hostile Architectural Environments

Adapting to Hostile Architectural Environments

Generalized algorithm for design of DC-free codes based on multilevel partition chain

A generalized algorithm for design of DC-free codes based on the multilevel partition chain is presented. The multilevel partition chain is formed from the code partition chain of Reed-Muller codes. Some parameters such as the maximum runlength and running digital sum (RDS) of DC-free codes are also obtained. The results show that the DC-free codes obtained by the presented design algorithm have good coding parameters.

Performance modeling and code partitioning for the DS architecture

DS (Decoupled-Superscalar) is a new microarchitecture that combines decoupled and superscalar techniques to exploit instruction level parallelism. Issue bandwidth is increased while circuit complexity growth is controlled with little negative impact on performance. Programs for DS are compiled into two instruction substreams: the dominant substream navigates the control flow and the rest of computational task is shared between the dominant and subsidiary substreams. Each substream is processed by a separate superscalar core realizable with current VLSI technology. DS machines are binary compatible with superscalar machines having the same instruction set, and a family of DS machines is binary compatible without recompilation.DS run time behavior is examined with an analytical model. A novel technique for controlling slip between substreams is introduced. Code partitioning issues of instruction count balancing and residence time balancing, important to any split-stream scheme, are discussed. Simulation shows DS achieves performance comparable to an aggressive superscalar, but with potentially less complex hardware and faster clock rate.

Analysis of a Heuristic for Code Partitioning

In this paper, we analyze the time complexity and performance of a heuristic for code partitioning for Distributed Memory Multiprocessors (DMMs). The partitioning method is data-flow based where all levels of parallelism are exploited. Given a weighted Directed Acyclic Graph (DAG) representation of the program, our algorithm automatically determines the granularity of parallelism by partitioning the graph into tasks to be scheduled on the DMM. The granularity of parallelism depends only on the program to be executed and on the target machine parameters. The output of our algorithm is passed on as input to the scheduling phase. Finding an optimal solution to this problem is NP-complete. Due to the high cost of graph algorithms, it is nearly impossible to come up with close to optimal solutions that do not have very high cost (higher order polynomial). Our proposed heuristic gives good performance and has relatively low cost.

Partitions: A taxonomy of types and representations and an overview of coding techniques

Abstract Recognising the importance of partition or shape coding in the field of image and video coding, and the fact that a systematisation of the subject would simplify the comparison of partition coding techniques, this paper proposes a classification of partition types and partition representations into a taxonomy tree. The partition type level of the tree classifies the possible partition types that may have to be coded. The partition representation level classifies the possible representations for each partition type. This paper also overviews the partition coding techniques which address the considered partition types and which use the identified partition representations. Emphasis is given to binary partition coding techniques proposed within the framework of MPEG-4.

Generalized concatenation of convolutional codes

AbstractGeneralized concatenation of inner and outer convolutional codes is studied. The essential problem is the partitioning of the inner code. A construction procedure to obtain a suitable equivalent description for a given code is derived, which gives the best possible distances in the partitioned subcodes. The construction rule is illustrated with two examples. A small code is studied to emphasize the ideas of the construction and a large code, namely the satellite standard code, demonstrates the considerable gains in decoding performance when using generalized concatenation. Furthermore, the possibilities for iterative decoding are pointed out.

Computer aided parallelisation tools (CAPTools) — conceptual overview and performance on the parallelisation of structured mesh codes

C omputer A ided P arallelisation T ools (CAPTools) is a toolkit designed to automate as much as possible of the process of parallelising scalar FORTRAN 77 codes. The toolkit combines a very powerful dependence analysis together with user supplied knowledge to build an extremely comprehensive and accurate dependence graph. The initial version has been targeted at structured mesh computational mechanics codes (eg. heat transfer, Computational Fluid Dynamics (CFD)) and the associated simple mesh decomposition paradigm is utilised in the automatic code partition, execution control mask generation and communication call insertion. In this, the first of a series of papers [1–3] the authors discuss the parallelisations of a number of case study codes showing how the various component tools may be used to develop a highly efficient parallel implementation in a few hours or days. The details of the parallelisation of the TEAMKE1 CFD code are described together with the results of three other numerical codes. The resulting parallel implementations are then tested on workstation clusters using PVM and an i860-based parallel system showing efficiencies well over 80%.

Automatic parallel code generation for message passing on distributed memory systems

The availability of a very accurate dependence graph for a scalar code is the basis for the automatic generation of an efficient parallel implementation. The strategy for this task which is encapsulated in a comprehensive data partitioning code generation algorithm is described. This algorithm involves the data partition, calculation of assignment ranges for partitioned arrays, addition of a comprehensive set of execution control masks, altering loop limits, addition and optimisation of communications for all data. In this context, the development and implementation of strategies to merge communications wherever possible has proved an important feature in producing efficient parallel implementations for numerical mesh based codes. The code generation strategies described here are embedded within the Computer Aided Parallelisation tools (CAPTools) software as a key part of a toolkit for automating as much as possible of the parallelisation process for mesh based numerical codes. The algorithms used enables parallelisation of real computational mechanics codes with only minor user interaction and without any prior manual customisation of the serial code to suit the parallelisation tool.

The finest homophonic partition and related code concepts

Let C be a finite set of n words having total length L where all words are taken over a R-element alphabet. The set C is called numerically decipherable if any two factorizations of the same word over the given alphabet into words in C have the same length. An O(nL/sup 2/) time and O((n+k)L) space algorithm is presented for computing the finest homophonic partition of C provided that this set is numerically decipherable. The latter property can be decided by another algorithm requiring O(nL) time and O((n+k)L) space. The two algorithms are based on a technique related to dominoes.

Throughput analysis of digital partitioning with error-correcting codes for optical matrix–vector processors

Digital partitioning and error-correcting codes provide a technique for achieving high-accuracy computations with analog optical matrix-vector processors. We present the results of a detailed throughput analysis of this technique. The results indicate that using one processor per submatrix provides the best compromise between system throughput and hardware requirements over a range of matrix sizes. Errorcorrecting codes are shown to not significantly degrade system throughput for large matrix sizes. Finally, a comparison to digital electronic computers is made.

Combining digital partitioning and error-correcting codes for high accuracy optical computing

Digital partitioning is a promising new technique for achieving high accuracy computations on analogue optical matrix-vector processors. One potential drawback of digital partitioning is its sensitivity to errors. Error-correcting codes can enhance the performance of the digital partitioning algorithm by reducing the sensitivity to errors. Simulation results are presented showing the benefits of using error-correcting codes with digital partitioning. In addition, an analysis of the time requirements for encoding and decoding the error-correcting codes and the effect on system throughput is presented.

Efficient register allocation via coloring using clique separators

Although graph coloring is widely recognized as an effective technique for register allocation, memory demands can become quite high for large interference graphs that are needed in coloring. In this paper we present an algorithm that uses the notion of clique separators to improve the space overhead of coloring. The algorithm, based on a result by R. Tarjan regarding the colorability of graphs, partitions program code into code segments using clique separators. The interference graphs for the code partitions are constructed one at a time and colored independently. The colorings for the partitions are combined to obtain a register allocation for the entire program. This approach can be used to perform register allocation in a space-efficient manner. For straight-line code (e.g., local register allocation), an optimal allocation can be obtained from optimal allocations for individual code partitions. Experimental results are presented demonstrating memory demand reductions for interference graphs when allocating registers using clique separators.