Partial Reconfiguration Research Articles

An improved reconfiguration algorithm for handling 1-point NoC failures

In today’s world, the demands for high-performance computing necessitate faster on-chip communication. Current chips with a large number of on-chip elements need an efficient alternative such as network-on-chip (NoC) for on-chip communication. As technology down scales toward the deep sub-micron, process variability makes the transistors more unreliable. Hence, on-chip elements including NoC can suffer from permanent/transient failures. In an NoC, 1-link/1-router failure can disrupt overall connectivity. The paper presents an improved routing reconfiguration algorithm for handling all 1-point permanent failures in 2D mesh NoC. By 1-point failure, we mean a failure can be occurred on any network link/router. State-of-the-art approaches either require a large number of reconfiguration cycles or provide partial support for 1-point failures, i.e., cover only 1-link failures. Proposed approach performs partial reconfiguration of routing function implemented using logic-bits instead of costly routing tables, thus reducing hardware overheads for larger networks as well. In terms of performance, the average flit latency cycles are reduced up to 31% and the average network throughput is improved up to 14.5% for 1-router failure in 8 × 8 2D mesh NoC. For 2-router failures, the improvements are 20% and 13% in terms of average flit latency cycles and average network throughput, respectively.

Task‐based preemptive scheduling on FPGAs leveraging partial reconfiguration

SummaryField‐programmable gate arrays (FPGAs) are an attractive type of accelerator for all‐purpose high performance computing computing systems due to the possibility of deploying tailored hardware on demand. However, the common tools for programming and operating FPGAs are still complex to use, especially in scenarios where diverse types of tasks should be dynamically executed. In this work, we present a programming abstraction with a simple interface that internally leverages high‐level synthesis, dynamic partial reconfiguration and synchronization mechanisms to use an FPGA as a multi‐tasking server with preemptive scheduling and priority queues. This leads to an improved use of the FPGA resources, allowing the execution of several different kernels concurrently and deploying the most urgent ones as fast as possible. The results of our experimental study show that our approach incurs only a 10 5% overhead in the worst case when using two reconfigurable regions, whilst providing a significant performance improvement of at least 24 21% over the traditional full reconfiguration approach.

Natural variation of warm temperature-induced raffinose accumulation identifies TREHALOSE-6-PHOSPHATE SYNTHASE 1 as a modulator of thermotolerance.

High-temperature stress limits plant growth and reproduction. Exposure to high temperature, however, also elicits a physiological response, which protects plants from the damage evoked by heat. This response involves a partial reconfiguration of the metabolome including the accumulation of the trisaccharide raffinose. In this study, we explored the intraspecific variation of warm temperature-induced raffinose accumulation as a metabolic marker for temperature responsiveness with the aim to identify genes that contribute to thermotolerance. By combining raffinose measurements in 250 Arabidopsis thaliana accessions following a mild heat treatment with genome-wide association studies, we identified five genomic regions that were associated with the observed trait variation. Subsequent functional analyses confirmed a causal relationship between TREHALOSE-6-PHOSPHATE SYNTHASE 1 (TPS1) and warm temperature-dependent raffinose synthesis. Moreover, complementation of the tps1-1 null mutant with functionally distinct TPS1 isoforms differentially affected carbohydrate metabolism under more severe heat stress. While higher TPS1 activity was associated with reduced endogenous sucrose levels and thermotolerance, disruption of trehalose 6-phosphate signalling resulted in higher accumulation of transitory starch and sucrose and was associated with enhanced heat resistance. Taken together, our findings suggest a role of trehalose 6-phosphate in thermotolerance, most likely through its regulatory function in carbon partitioning and sucrose homoeostasis.

ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge

Partial reconfiguration (PR) is a key enabler to the design and development of adaptive systems on modern Field Programmable Gate Array (FPGA) Systems-on-Chip (SoCs), allowing hardware to be adapted dynamically at runtime. Vendor-supported PR infrastructure is performance-limited and blocking, drivers entail complex memory management, and software/hardware design requires bespoke knowledge of the underlying hardware. This article presents ZyPR: a complete end-to-end framework that provides high-performance reconfiguration of hardware from within a software abstraction in the Linux userspace, automating the process of building PR applications with support for the Xilinx Zynq and Zynq UltraScale+ architectures, aimed at enabling non-expert application designers to leverage PR for edge applications. We compare ZyPR against traditional vendor tooling for PR management as well as recent open source tools that support PR under Linux. The framework provides a high-performance runtime along with low overhead for its provided abstractions. We introduce improvements to our previous work, increasing the provisioning throughput for PR bitstreams on the Zynq Ultrascale+ by 2× and 5.4× compared to Xilinx’s FPGA Manager.

Automated design and usage of the Fault-Tolerant dynamic partial reconfiguration controller for FPGAs

This article presents a new design automation method for Fault-Tolerant (FT) systems implemented on dynamically reconfigurable Field Programmable Gate Arrays (FPGAs). The method aims at minimizing the human interactions needed to incorporate FT mechanisms into an existing system. It starts with a source code of an original unhardened circuit. It continues by automated manipulation of the source code, algorithmic strategic selection of suitable FT techniques, design space exploration of candidate FT implementations, and selection of the resulting implementation. The method also includes efficient evaluation of achieved FT parameters performed on the target HW. As a novel approach working on the level of HW description languages is employed, the code modification is separated, which differentiates our method from others. The case study utilizing this method targets the design of an experimental FT dynamic partial reconfiguration controller for an FPGA. This controller is helpful for the restoration of faulty components due to a single-event upset on an FPGA. We used the method to generate a set of Pareto-optimal controllers concerning the design’s Mean Time to Failure (MTTF) parameter, power consumption, and size. Then, the FT controller is connected to several benchmark circuits, and the reliability parameters are evaluated at the entire system level. Our results show that by replacing the standard reconfigurable controller with our automatically-designed FT controller for one specific benchmark, the design size increased by 20.1%, and MTTF increased by 11.7%. However, the efficiency is highly dependent on the target system size, MTTF, and circuit functionality. We also estimate that a complex system defined by half a million configuration bits would improve MTTF by more than 50%.

Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow

Dynamic Partially Reconfiguration (DPR) on FPGA has attracted significant research interest in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in the current DPR design flow, leveraging benefits from DPR requires specific design expertise with laborious manual design effort. Considering the complicated concurrency relations among various functions, it is challenging to select appropriate Partial Reconfiguration Modules (PR Modules) and cluster them into proper groups with a proper reconfiguration schedule so that the hardware modules can be swapped in and out correctly during the run time. Furthermore, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we propose a Maximum-Weight Independent Set model to formulate the PR Module selection and clustering problem so that the original manual exploration can be solved efficiently and automatically. We also propose a step-wise adjustment configuration prefetching strategy incorporated in our model to generate optimized reconfiguration schedules. Our proposed approach not only supports various design constraints but also can consider multiple objectives such as area and reconfiguration delay. Experimental results show that our approach can optimize resource utilization and reduce reconfiguration delay with good scalability. Especially, the implementation of the real design case shows that our approach can be embedded in Xilinx's DPR design flow successfully.

Resurrecting Maghreb Pluriel ?: Jews and Postauthoritarian Tunisia

Abstract: The Tunisian revolution of 2011 marked a partial reconfiguration of the political elite and the beginning of a protracted democratization process whose long-term success is far from secured. In this article, I discuss societal/political/cultural transformations toward democracy in Tunisia since 2011 through the prism of its tiny Jewish minority. The perceived homogeneity of Tunisian society has come under increasing scrutiny since the revolution, and this includes a heightened visibility of the country's Jewish community and a degree of public debate on related topics. I focus on three cases: the preservation of Jewish cultural heritage, the demise of an NGO designed to fight racism and antisemitism in Tunisia, and the commemoration of the German occupation of Tunisia during World War II. Addressing contemporary Tunisian history "from the margins" enables a more nuanced understanding of political struggles that accompany processes of de-/re-territorializing Tunisian collective identities.

Resurrecting Maghreb Pluriel ?: Jews and Postauthoritarian Tunisia

Abstract: The Tunisian revolution of 2011 marked a partial reconfiguration of the political elite and the beginning of a protracted democratization process whose long-term success is far from secured. In this article, I discuss societal/political/cultural transformations toward democracy in Tunisia since 2011 through the prism of its tiny Jewish minority. The perceived homogeneity of Tunisian society has come under increasing scrutiny since the revolution, and this includes a heightened visibility of the country's Jewish community and a degree of public debate on related topics. I focus on three cases: the preservation of Jewish cultural heritage, the demise of an NGO designed to fight racism and antisemitism in Tunisia, and the commemoration of the German occupation of Tunisia during World War II. Addressing contemporary Tunisian history "from the margins" enables a more nuanced understanding of political struggles that accompany processes of de-/re-territorializing Tunisian collective identities.

Designing Reconfigurable Cyber-Physical Systems Using Unified Modeling Language

Technological progress in recent years in the Cyber-Physical Systems (CPSs) area has given designers unprecedented possibilities and computational power, but as a consequence, the modeled CPSs are becoming increasingly complex, hierarchical, and concurrent. Therefore, new methods of CPSs design (especially using abstract modeling) are needed. The paper presents an approach to the CPS control part modeling using state machine diagrams from Unified Modelling Language (UML). The proposed design method attempts to combine the advantages of graphical notation (intuitiveness, convenience, readability) with the benefits of text specification languages (unambiguity, precision, versatility). The UML specification is transformed using Model-Driven Development (MDD) techniques into an effective program in Hardware Description Language (HDL), using Concurrent Finite State Machine (CFSM) as a temporary model. The obtained HDL specification can be analyzed, validated, synthesized, and finally implemented in Field Programmable Gate Array (FPGA) devices. The dynamic, partial reconfiguration (a feature of modern FPGAs) allows for the exchange of a part of the implemented CPS algorithm without stopping the device. But to use this feature, the model must be safe, which in the proposed approach means, that it should possess special idle states, where the control is transferred during the reconfiguration process. Applying the CFSM model greatly facilitates this task. The proposed design method offers efficient graphical modeling of a control part of CPS, and automatic translation of the behavior model into a synthesizable Verilog description, which can be directly implemented in FPGA devices, and dynamically reconfigured as needed. A practical example illustrating the successive stages of the proposed method is also presented.

Modular Hardware/Software Architecture for Edge Units in Highly Flexible Manufacturing Systems

With the increasing demand for individualized production and swift adaptability to changing market needs, new manufacturing system concepts emerge. Aiming for high flexibility and scalability, they rely on universal reconfigurable machines that can be used in various production steps by automatically changing tools and sensors. Consequently, the data processing infrastructure is required to support the frequent exchange of process-specific software applications, ranging from control and monitoring tasks to complex sensor data processing. This can be a major challenge when computation-intensive software is supported by hardware acceleration to achieve the desired performance or latency requirements. In this paper, we present an edge unit architecture that allows for hosting such applications while meeting the needs for modularity and reconfigurability. It builds upon a hypervisor to partition fixed processing resources among the applications. We present a mechanism that extends this partitioning to field-programmable gate arrays (FPGA) by using dynamic partial reconfiguration. This provides the option to deploy application-specific hardware accelerators with computation-intensive applications while maintaining modularity and on-line reconfigurability. We conclude the paper by pointing out the potential of the proposed architecture based on a use case for automated disassembly in a reconfigurable robotic cell.

Moving NFV Toward the Antenna Through FPGA-Based Hardware Reconfiguration

This paper presents a system architecture and design, enabling hardware level virtualization for radio units in a 5G and beyond Cloud Radio Access Networks environment. This aims to increase system flexibility and reconfigurability, bringing Network Function Virtualization closer to the antenna, leveraging the Hardware as a Service concept. Using Field Programmable Gate Array partial reconfiguration capabilities, an architecture was designed with independent transmission channels capable of dynamically change waveforms depending on user requirements, while maintaining the core system running. It was achieved an Error Vector Magnitude below 1.4% for sub-6 GHz frequencies and a channel reconfiguration time below 8 ms.

DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs

For several new applications, FPGA-based computation has shown better latency and energy efficiency compared to CPU or GPU-based solutions. We note two clear trends in FPGA-based computing. On the edge, the complexity of applications is increasing, requiring more resources than possible on today's edge FPGAs. In contrast, in the data center, FPGA sizes have increased to the point where multiple applications must be mapped to fully utilize the programmable fabric. While these limitations affect two separate domains, they both can be dealt with by using dynamic partial reconfiguration (DPR). Thus, there is a renewed interest to deploy DPR for FPGA-based hardware. In this work, we present <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Doing More with Less (DML)</i> – a methodology for scheduling heterogeneous tasks across an FPGA's resources in a resource efficient manner while effectively hiding the latency of DPR. With the help of an integer linear programming (ILP) based scheduler, we demonstrate the mapping of diverse computational workloads in both cloud and edge-like scenarios. Our novel contributions include: enabling IP-level pipelining and parallelization to exploit the parallelism available within batches of work in our scheduler, and strategies to map and run multiple applications simultaneously. We consider the application of our methodology on real world benchmarks on both small (a Zedboard) and large (a ZCU106) FPGAs, across different workload batching and multiple-application scenarios. Our evaluation proves the real world efficacy of our solution, and we demonstrate an average speedup of 5X and up to 7.65X on a ZCU106 over a bulk-batching baseline via our scheduling strategies. We also demonstrate the scalablity of our scheduler by simultaneously mapping multiple applications to a single FPGA, and explore different approaches to sharing FPGA resources between applications.

Intelligent Optimization Approaches for a Secured Dynamic Partial Reconfigurable Architecture-Based Health Monitoring System

In this work, an intelligent multi-objective optimization technique is proposed to optimize various parameters such as power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]) for a health monitoring system designed using the Secured Dynamic Partial Reconfiguration (SDPR) architecture. The cost-efficient Dynamic Partial Reconfiguration (DPR)-based field-programmable gate array (FPGA) is very useful for analyzing many applications such as automation and data processing. The novelty of this paper is to design a new intelligent SDPR (i-SDPR) module in order to achieve better performance in a health monitoring system by considering various performance parameters. The SDPR architecture is incorporated with two reconfigurable modules such as Encrypt and Authenticate, which results in an increase in the core power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]). So, to improve the performance of the SDPR-based health monitoring system, there is a necessity to optimize the performance parameters and it is achieved through intelligent multi-objective evolutionary (MOEA) techniques. The intelligent multi-objective evolutionary techniques such as Niched-Pareto Genetic Algorithm (NPGA), Pareto Archived Evolution Strategy (PAES) and Pareto Envelope-based Selection Algorithm (PESA) have been considered for better optimization in the performance parameters. For the study, the free-to-use MIMIC-III dataset is taken, which contains critically admitted various intensive care unit patient data. The dataset is processed through any one of the multi-objective evolutionary operators till satisfying the conditions and then forwarded to implementation. The proposed architecture has been implemented and tested using Cyclone[Formula: see text] V SX SoC Development Kit. The comparative analysis of various performance parameters was done for the proposed i-SDPR with the existing techniques such as the DPR and SDPR approach to show the improvement. The results declare that the proposed techniques obtain better performance compared to the existing techniques.

A Power-Aware Real-Time System for Multi-Video Treatment on FPGA with Dynamic Partial Reconfiguration and Voltage Scaling

As the energy consumption is an evaluating factor for System-On-Chip (SOC) design, this paper presents a power-aware architecture for a real-time multi-video system on FPGA. This architecture aims to optimize power consumption for a multi-video system on ARM-based architectures. The proposed architecture uses dynamic reconfiguration and voltage scaling to create a power-aware system for real-time multi-video processing with minimal power dissipation. Dynamic partial reconfiguration was used to optimize the utilization of resources and reduce dynamic power consumption. Voltage scaling was also used to optimize dynamic power consumption, by configuring the blocks to use the minimum necessary voltage for normal operating conditions. The proposed architecture focused on the Zynq platform. The results showed power savings of up to 70% concerning performance and real-time constraints.

The Benefits and Costs of Netlist Randomization Based Side-Channel Countermeasures: An In-Depth Evaluation

Exchanging FPGA-based implementations of cryptographic algorithms during run-time using netlist randomized versions has been introduced recently as a unique countermeasure against side channel attacks. Using partial reconfiguration, it is possible to shuffle between structurally different but functionally similar versions of a cryptographic implementation. The resulting varying power profile enhances the resistance against power-based side channel attacks. While side channel leakage is reduced, costs in terms of additional resources and/or lowered throughput are often increased due to the overheads of the required online partial reconfiguration. In this work, we provide an in-depth evaluation of the leakage-area-throughput trade-off.

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration

RASHT: A Partially Reconfigurable Architecture for Efficient Implementation of CNNs

Convolutional neural networks (CNNs) are widely used in machine learning (ML) applications such as image processing. CNN requires heavy computations to provide significant accuracy for many ML tasks. Therefore, the efficient implementations of CNNs to improve performance using limited resources without accuracy reduction is a challenge for ML systems. One of the architectures for the efficient execution of CNNs is the array-based accelerator, that consists of an array of similar processing elements (PEs). The array accelerators are popular as high-performance architecture using the features of parallel computing and data reuse. These accelerators are optimized for a set of CNN layers, not for individual layers. Using the same accelerator dimension size to compute all CNN layers with varying shapes and sizes leads to the resource underutilization problem. We propose a flexible and scalable architecture for array-based accelerator that increases resource utilization by resizing PEs to better match the different shapes of CNN layers. The low-cost partial reconfiguration improves resource utilization and performance, resulting in a 23.2&#x0025; reduction in computational times of GoogLeNet compared to the state-of-the-art accelerators. The proposed architecture decreases the on-chip memory access rate by 26.5&#x0025; with no accuracy loss.

Implementation of Robotic Navigation Algorithms Using Partial Reconfiguration on Zynq SoC

The purpose for this research work is to design a heterogeneous method for adaptive, task-based computer hardware reconfiguration for adaptive mobile robotic applications. The proposed method uses the dynamic reconfiguration technique to modify the navigation system to meet the requirements of various navigation algorithms for accomplishing an assigned task. In this work, we have proposed an efficient architecture that satisfies the requirements with adequate hardware and software resources by dynamically reconfiguring the system. The ability to change resources allows robots to collaborate more easily, to enhance performance and fault tolerance. The method is endorsed with case studies in which a multiple mobile robots are loaded with bitfile and their behaviors are dynamically modified during runtime. This paper also proposes the hardware implementation of navigation algorithms on Zynq SoC, XC7Z020CLG484-1, using Xilinx Vivado 2017.3 to simulate and synthesize the design. Verilog is a real-time hardware description language, which is used to deploy multiple robots. Software Development Kit (SDK) is used to facilitate the generation of integrated software applications for Xilinx embedded processors. One of the important aspects of this work is adopting an FPGA-based robot in service-based applications for assisting humans in their daily lives.

Theorizing the devices of sociotechnical governance: Systemic practices, visions, and dynamics of change in Mexico's energy transition

Fossil-fuel-based energy systems have been built around visions, rules, practices, and social relationships, which can become entrenched, difficult to displace, and hence influential in the configuration of energy futures. Grounded in the interpretative tradition of science and technology studies, the present article introduces the notion of devices of sociotechnical governance (DSGs) to analyze this issue. DSGs comprise the political designs which dynamically shape and are shaped by sociotechnical systems and their social relations. The article examines Mexico's political path through energy transition (ET)—particularly in its ET law and social impact assessments—as examples of DSGs. Having traced policy formation processes, outcomes, and feedback loops, the findings suggest that climate mitigation and the social effects of renewables have shaped infrastructures, development geographies, and social agendas in Mexico, leading to the system's partial reconfiguration and contestation. Nevertheless, context-specific visions, rules, and practices (e.g., centralized decision-making, top-down management, and energy sovereignty), built along with state-owned energy companies, have persisted, influencing how institutions process emerging agendas, group dynamics, and policy outputs. By doing so, DSGs are meant to contribute to scholarly efforts to explain the interactions between and coevolution of ET policies and sociotechnical systems.

Vulnerability evaluation on 16 nm FinFET Ultrascale+ MPSoC using fault injection and proton irradiation

The SEE vulnerability in two ways bitstream loading implementations on a dynamic partial reconfiguration (DPR) design is examined using fault injections and proton irradiations on a Xilinx 16 nm FinFET Ultrascale+ MPSoC. During fault injection, two kinds of soft errors are detected, they are system halt (SH) and calculation result error (CRE). In comparison, the detected errors are only SHs in the 100 and 80 MeV proton irradiations. Also, the critical bit error and cross sections are calculated in the fault injection and proton irradiation, respectively. The results signify that there is almost no difference in SEE vulnerability between the two ways of bitstream loading in DPR design.