Partial Trench Isolation Research Articles

Vertical 4H-SiC n-i-p-n APDs With Partial Trench Isolation

In this letter, in order to improve avalanche characteristics in deep ultraviolet range and enhance fill factor, vertical 4H-SiC n-i-p-n avalanche photodiodes (APDs) are designed and fabricated, in which avalanche current flows through a forwardbiased p-n junction formed between the p epi-layer and the n-type substrate. Compared with a traditional n-i-p APD, no obvious difference of gain-voltage and photo-response characteristics is observed, indicating the feasibility of the proposed n-i-p-n device structure. When a partial trench isolation scheme is applied, the vertical n-i-p-n APD shows a high fill factor of 78.3% and a low-bias quantum efficiency of 66%.

High Fill-Factor 4H-SiC Avalanche Photodiodes With Partial Trench Isolation

In this letter, a beveled mesa 4H-SiC ultraviolet (UV) avalanche photodiode (APD) with partial trench isolation is reported. By adopting this partial trench isolation structure, when device diameter of the APD is $150~\mu \text{m}$ , its fill factor can increase from 33.9% to 63.5% compared with the traditional full trench isolation structure. The photocurrent of the APD shows corresponding improvement when illuminated with the same UV light source. Through current–voltage, spectral response, and single photon detection characterizations, it is proved that the performance of the partial trench isolation APD does not degrade compared with the traditional full trench isolation structure. The APD fabricated in this letter with partial trench isolation shows a unity-gain peak quantum efficiency of 66.4% at 270 nm and a single photon detection efficiency of 9.5% at 280 nm when the dark count rate is fixed at 1 Hz/ $\mu \text{m}^{2}$ .

Effect of a body-tie structure fabricated by partial trench isolation on the suppression of floating body effect induced soft errors in SOI SRAM investigated using nuclear probes

Soft errors induced by proton, helium and oxygen ion irradiations were measured as a function of distance between a body electrode under partial trench isolation and a metal pad connected to a tungsten via for the first metal layer of a silicon-on-insulator (SOI) static random access memory. Abnormal drain charges induced by ion irradiations with various distances in the SOI metal oxide semiconductor field effect transistor were simulated to be compared with the experimental results. The soft errors were found to depend on the distance between the body electrode and the metal pad in the case of the abnormal drain charge, which is induced by incident ions, lower than the critical charge of the SRAM cells. The soft errors did not depend on the distance for the abnormal drain charges higher than the critical charge.

High Soft-Error Tolerance Body-Tied Silicon-on-Insulator Technology with Partial Trench Isolation

This paper presents soft-error tolerance for partially depleted silicon-on-insulator (SOI) devices with partial trench isolation (PTI) that realize a body-tied structure. Mechanism of charge collections due to alpha-particle strikes is clarified for a body-tied SOI device with the PTI structure and a body-floating SOI device. It is estimated that the soft-error tolerance of the body-floating SOI device is lower than that of the body-tied one because of parasitic bipolar action. Soft-error testing by using 0.18 µm 4 Mbit static random-access memory (SRAM) indicates that the body-tied SOI devices with the PTI structure have high soft-error tolerance as compared with bulk devices. The charge collections for the PTI structure are also investigated to mitigate the soft errors. It is demonstrated that the body-tied PTI SOI technology is one of the best solutions for high-performance system LSIs with high soft-error tolerance.

Feasibility Study of a Novel Four Transistor Silicon-on-Insulator Static Random Access Memory Cell Utilizing Partial Trench Isolation

A novel static random access memory (SRAM) cell composed of four thin film silicon-on-insulator (TFSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) intended for 0.5 V operation is proposed. The body regions of the cross-coupled transistor pair are utilized as load resistors. Transfer MOSFETs connecting each SRAM cell to a word line are dynamic threshold MOSFETs (DTMOSs). By utilizing partial trench isolation, the need of special gate shapes for realizing body contacts is eliminated in the proposed SRAM cell. A device simulator with circuit analysis capability reveals that the proposed SRAM cell can be operated properly under a supply voltage of as low as 0.5 V.

Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

A 0.18 /spl mu/m silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated. The hybrid trench isolation is a combination of partial trench isolation and full trench isolation. In the partial trench isolation region, a part of the SOI layer remains under the field oxide so as to provide scalable body-tied SOI metal-oxide-semiconductor field-effect transistors (MOSFETs), while in the full trench isolation region, the whole of the SOI layer is replaced by the field oxide so as to provide high quality passives. It is demonstrated that this technology improves the maximum oscillation frequency and the minimum noise figure of the MOSFET and the Q-factor of the inductor, compared with bulk technology. Moreover, it is verified that the partial-trench-isolated body-tied structure suppresses the floating body effect of SOI devices for RF/analog applications and thus guarantees low-noise characteristics, stability, linearity, and reliability. It is concluded that this technology will be one of the key technologies for supporting the evolution of wireless communications.