The problems with synchronous designs at high clock fre- quencies have been well documented. This makes an asynchronous ap- proach attractive for high speed technologies like GaAs. We investigate the issues involved by describing the design of a parallel multiplier that can be part of a floating point multiplier. We first present a new architecture called the partial army of array (PAA) that is more regular than a partial tree approach while having the same latency. We then show how this architecture can be used in a self-timed implementation in the style of micropipelines. We next describe how we can design the final carry propagate adder using a new precharged logic family in GaAs that we developed as part of this project. We conclude with some genera1 observations on doing asynchronous design in GaAs. Zndex Terms- Self-timed systems, micropipelines, multipliers, GaAs, precharged circuits.