Partial Reconfiguration Capabilities Research Articles

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

This article tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms. Applications are composed of directed acyclic graphs of tasks, with each directed-acyclic-graph (DAG) having a minimum inter-arrival period for its activation requests and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multi-core platforms with Dynamic Voltage and Frequency Scaling (DVFS) capabilities, including big.LITTLE Arm architectures and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by minimizing power consumption, respecting precise timing constraints, maximizing the applications’ slack, respecting given power consumption constraints, or even a combination of these, in a multi-objective formulation. We propose an off-line optimization of the mentioned problem based on mixed-integer quadratic constraint programming (MIQCP). The optimization provides the DVFS configuration of all the CPUs (or accelerators) capable of frequency switching and the placement to be followed by each task in the DAGs, including the software-vs.-hardware implementation choice for tasks that can be hardware accelerated. For relatively big problems, we developed heuristic solvers capable of providing suboptimal solutions in a significantly reduced time compared to the MIQCP strategy, thus widening the applicability of the proposed framework. We validate the approach by running a set of randomly generated DAGs on Linux under SCHED_DEADLINE, deployed onto two real boards, one with Arm big.LITTLE architecture, the other with FPGA acceleration, verifying that the experimental runs meet the theoretical expectations in terms of timing and power optimization goals.

Moving NFV Toward the Antenna Through FPGA-Based Hardware Reconfiguration

This paper presents a system architecture and design, enabling hardware level virtualization for radio units in a 5G and beyond Cloud Radio Access Networks environment. This aims to increase system flexibility and reconfigurability, bringing Network Function Virtualization closer to the antenna, leveraging the Hardware as a Service concept. Using Field Programmable Gate Array partial reconfiguration capabilities, an architecture was designed with independent transmission channels capable of dynamically change waveforms depending on user requirements, while maintaining the core system running. It was achieved an Error Vector Magnitude below 1.4% for sub-6 GHz frequencies and a channel reconfiguration time below 8 ms.

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

IoT technology is evolving at a quick pace and is becoming an important part of everyday life. Consequently, IoT systems hold large amounts of data related to the user of the system that is vulnerable to security breaches. Thus, data collected by IoT systems need to be secured efficiently without affecting the IoT systems’ performance and without compromising security as well. In this paper, a high-performance dynamic security system is introduced. The system makes use of the ZedBoard’s dynamic partial reconfiguration capability to shift between three distinct cipher algorithms: AEGIS, ASCON, and DEOXYS-II. The switching between the three algorithms is performed using two different techniques: the algorithm hopping technique or the power adaptive technique. The choice of which technique to be used is dependent on whether the system needs to be focused on performance or power saving. The ciphers used are the CAESAR competition finalists that achieved the greatest results in each of the three competition categories, where each cipher algorithm has its own set of significant characteristics. The proposed design seeks to reduce the FPGA reconfiguration time by the application of LZ4 (Lempel-Ziv4) compression and decompression techniques on the ciphers’ bitstream files. The reconfiguration time decreased by a minimum of 38% in comparison to the state-of-the-art design, while the resource utilization increased by approximately 2%.

Dynamic Partial Reconfiguration Profitability for Real-Time Systems

Modern field-programmable gate arrays offer dynamic partial reconfiguration (DPR) capabilities, a characteristic that opens new scheduling opportunities for real-time applications running on heterogeneous platforms. To evaluate when it is really useful to exploit a DPR, in this letter, we present the characterization of its reconfiguration cost in terms of time and a definition of the “DPR Profitability” concept targeting real-time systems. To obtain such results, the components involved in a DPR process have been identified and an innovative approach to calculate the DPR time and its worst-case bound is provided. We validate our approach on a real DPR-compliant platform, showing that our proposal is general enough to be applied to modern DPR-compliant platforms.

An SoC-FPGA-Based Iterative-Closest-Point Accelerator Enabling Faster Picking Robots

The conventional picking robots suffered from low picking throughput due to a large amount of computation of the object-pose-estimation algorithm which is called iterative-closest-point (ICP) algorithm. This article presents an field-programmable gate array (FPGA)-based ICP accelerator, which achieves 11.7-times-faster object-pose estimation by a picking robot compared with the state-of-the-art technique based on K-D-tree <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -nearest neighbor (NN) search and four-core CPU. To accelerate the ICP, both algorithm-level and hardware-level techniques have been proposed and developed. The former is a hierarchical-graph-based <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -NN search enabling simultaneous acquisition of plural neighboring points. The latter is a sorting-network-based circuit implemented on an system on a chip (SoC)-FPGA. In addition, dynamic structural reconfiguration between the two key functionalities (graph generation and nearest neighbor search) is explored by utilizing the partial reconfiguration capability of FPGA to save the required hardware resource. Experiments of the proposed FPGA-based ICP accelerator using Amazon Picking Challenge data sets have confirmed that the object-pose estimation by ICP takes only 0.72 s at the power consumption of 4.2 W.

Scheduling and Resource Planner Based on Multicriteria Method for Partially Dynamically Reconfigurable Systems

Dynamically Reconfigurable FPGAs allow to accelerate the reconfiguration process downloading partial bitstreams to those areas created for that. The partial reconfiguration capability allows to share hardware resources between different tasks during the design lifecycle. In this paper we propose an algorithm based on Logic Score of preference (LSP) multicriteria decision method for floor planning, scheduling and order of deployment of these partial bitstreams during design lifecycle. The proposed method is well suited to be implemented in preemptive systems in which the deadline of a critical task can demand the preemption of a lower priority one.

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

In the era of IoT, embedded systems are becoming the cornerstone of many IoT related applications, such as smart cars and wearable devices. However, embedded devices have numerous constraints and requirements, including stringent area and power, reduced cost and time-to-market, and increased speedup. Furthermore, these applications are becoming increasingly compute/data-intensive requiring more processing power. Also, especially for IoT related applications, security is another major issue in resource-constrained embedded devices. Although cryptographic algorithms are widely used to ensure the security of these applications, commonly used ones, such as AES, are unsuitable for highly constrained embedded devices, due to their sheer complexity. Hence, several lightweight cryptographic algorithms were proposed in the literature that might be better suited for embedded devices. From these, SPECK and SIMON, introduced by NSA, are the two most popular ones. Another important challenge is how to incorporate the cryptographic algorithms in to embedded devices, efficiently and effectively, without compromising the integrity of the compute/data-intensive applications running on these small-footprint devices. Our previous analysis demonstrated that FPGAs are currently the best avenue to support compute/data-intensive applications running on resource-constrained embedded devices, due to FPGA’s many attractive traits, including, post-fabrication reprogrammability, dynamic and partial reconfiguration capabilities, and reduced time-to-market. Also, FPGAs can be utilized to provide several advantages/features required for the embedded device’s security, such as cryptographic algorithm agility, algorithm upload, algorithm modification, and resource efficiency. In this research work, we introduce novel, unique, and efficient dynamic and partial reconfigurable hardware architectures for the most popular SPECK and SIMON algorithms on embedded devices, considering the constraints associated with these devices and the requirements of the applications running on embedded devices. We also introduce unique system-level architectures for our proposed designs. To the best of our knowledge, no similar work exists in the literature that provides dynamic and partial reconfigurable hardware for SPECK and SIMON, and also provides system-level architecture. Our dynamic and partial reconfigurable hardware designs achieve 28% space saving compared to its static reconfigurable hardware, and 59 times speedup compared to its software counterpart.

A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications

In future wireless communication systems, several radio access technologies will coexist and interwork to provide a great variety of services with different requirements. Thus, the design of flexible and reconfigurable hardware is a relevant topic in wireless communications. The combination of high performance, programmability and flexibility makes Field-programmable gate array a convenient platform to design such systems, especially for base stations. This paper describes a dynamically reconfigurable baseband modulator for Orthogonal Frequency Division Multiplexing and Filter-bank Multicarrier modulation waveforms implemented on a Virtex-7 board. The design features Dynamic Partial Reconfiguration (DPR) capabilities to adapt its mode of operation at run-time and is compared with a functionally equivalent static multi-mode design regarding processing throughput, resource utilization, functional density and power consumption. The DPR-based design implementation reserves about half the resources used by static multi-mode counterpart. Consequently, the baseband processing dynamic power consumption observed in the DPR-based design is between 26 mW to 90 mW lower than in the static multi-mode design, representing a dynamic power reduction between 13% to 52%. The worst-case DPR latency measured was 1.051 ms, while the DPR energy overhead is below 1.5 mJ. Considering latency requirements for modern wireless standards and power consumption constraints for commercial base stations, the DPR application is shown to be valuable in multi-standard and multi-mode systems, as well as in scenarios such as multiple-input and multiple-output or dynamic spectrum aggregation.

Ultrahigh Energy Heavy Ion Test Beam on Xilinx Kintex-7 SRAM-Based FPGA

In recent years, field-programmable gate array (FPGA) devices have attracted a lot of attentions due to the increasing performance they provide thanks to technology scaling, besides their high flexibility through in-field reprogramming and/or partial reconfiguration capability. However, when such devices are to be deployed in safety- and mission-critical applications such as avionic and space applications, it is mandatory to verify the reliability of the device in the target environment where radiation effect is considered as one of the major sources of faults in the system. For static random access memory (SRAM)-based FPGA devices, the SRAM cells holding the configuration data for the circuit implemented on the devices are highly susceptible against single-event upset (SEU) induced by charged particle striking the device and one single SEU in the configuration memory may corrupt the implemented circuit design causing system misbehavior. In this paper, we present the radiation test data on Xilinx Kintex-7 SRAM-based FPGA using ultrahigh energy heavy-ion test beam for the first time available to third-party radiation test in CERN.

Scheduling and Resource Planner Based on Multicriteria Method for Partially Dynamically Reconfigurable Systems

Dynamically Reconfigurable FPGAs allow to accelerate the reconfiguration process downloading partial bitstreams to those areas created for that. The partial reconfiguration capability allows to share hardware resources between different tasks during the design lifecycle. In this paper we propose an algorithm based on Logic Score of preference (LSP) multicriteria decision method for floor planning, scheduling and order of deployment of these partial bitstreams during design lifecycle. The proposed method is well suited to be implemented in preemptive systems in which the deadline of a critical task can demand the preemption of a lower priority one.

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications

The advent of the Internet of Things has motivated the use of Field Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities for dynamic non-invasive modifications to circuits implemented on the FPGA. In particular, the ability to perform DPR over the network is essential in the context of a growing number of Internet of Things (IoT)-based and embedded security applications. However, the use of remote DPR brings with it a number of security threats that could lead to potentially catastrophic consequences in practical scenarios. In this paper, we demonstrate four examples where the remote DPR capability of the FPGA may be exploited by an adversary to launch Hardware Trojan Horse (HTH) attacks on commonly used security applications. We substantiate the threat by demonstrating remotely-launched attacks on Xilinx FPGA-based hardware implementations of a cryptographic algorithm, a true random number generator, and two processor based security applications - namely, a software implementation of a cryptographic algorithm and a cash dispensing scheme. The attacks are launched by on-the-fly transfer of malicious FPGA configuration bitstreams over an Ethernet connection to perform DPR and leak sensitive information. Finally, we comment on plausible countermeasures to prevent such attacks.

Matching circuits can be small: Partial evaluation and reconfiguration for FPGA-based packet processing

Network functions like routing or firewalling require specialized hardware such as FPGAs to process packets at high rates. Such hardware must be fast enough to process packets at line rate, and it must be programmable to update the installed packet processing policy. However, these goals are conflicting because a generic programmable circuit must provide sufficient resources to support a wide range of policies, which can lead to unused circuitry and low clock rates. Also, it misses logic optimization opportunities with regard to the structure of the installed policy. In this work, we investigate the optimization potential of policy-specific generated network processing circuits. Using the example of router forwarding information bases (FIBs), we demonstrate that FIB-specialized circuits need significantly fewer logic resources than equivalent generic forwarding circuits. In combination with the partial reconfiguration capability of FPGAs, we obtain efficient low-latency forwarding engines whose matching circuitry can be replaced on demand.

Energy efficient processing of motion estimation for embedded multimedia systems

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions.

A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications

The Internet of Things (IoT) is a dynamic, ever-evolving “living” entity. Hence, modern Field Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities, which allow in-field non-invasive modifications to the circuit implemented on the FPGA, are an ideal fit. Usually, the activation of DPR capabilities requires the procurement of additional licenses from the FPGA vendor. In this work, we describe how IoTs can take advantage of the DPR capabilities of FPGAs, using a modified DPR methodology that does not require any paid “add-on” utility, to implement a lightweight cryptographic security protocol. We analyze possible threats that can emanate from the availability of DPR at IoT nodes, and propose possible solution techniques based on Physically Unclonable Function (PUF) circuits to prevent such threats.

New approach to emulate SEU faults on SRAM based FPGAS

Field Programmable Gate Arrays (FPGAs) offer high capability in implementing of complex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets (SEUs). To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided. In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA. Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.

Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

A Givens rotation based scalable QRD core which utilizes an efficient pipelined and unfolded 2D multiply and accumulate (MAC) based systolic array architecture with dynamic partial reconfiguration (DPR) capability is proposed. The square root and inverse square root operations in the Givens rotation algorithm are handled using a modified look-up table (LUT) based Newton-Raphson method, thereby reducing the area by 71% and latency by 50% while operating at a frequency 49% higher than the existing boundary cell architectures. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for any real matrices of sizem×n, where4≤n≤8andm≥nby dynamically inserting or removing the partial modules. The evaluation results demonstrate a significant reduction in latency, area, and power as compared to other existing architectures. The functionality of the proposed core is evaluated for a variable length adaptive equalizer.

Fault Demotion Using Reconfigurable Slack (FaDReS)

We propose an active dynamic redundancy-based fault-handling approach exploiting the partial dynamic reconfiguration capability of static random-access memory-based field-programmable gate arrays. Fault detection is accomplished in a uniplex hardware arrangement while an autonomous fault isolation scheme is employed, which neither requires test vectors nor suspends the computational throughput. The deterministic flow of the fault-handling scheme achieves an improved recovery in a bounded number of reconfigurations. This approach extends existing signal processing properties to accommodate fault handling, and is validated by implementing an H.263 video encoder discrete cosine transform (DCT) block. The peak signal-to-noise ratio measure of the video sequences indicates fault tolerance in the DCT block with only limited quality degradation, during the isolation and recovery phases spanning a few frames.

Dynamic objects: Supporting fast and easy run-time reconfiguration in FPGAs

Partial reconfiguration capabilities must be exploited to obtain the maximum benefits from dynamically reconfigurable FPGAs. Partial reconfiguration process management still faces a set of open problems that have thus far made it impossible to take full advantage of partial and dynamic reconfiguration. The work presented in this article proposes a novel architecture, development workflow, and modelling approach for dynamically reconfigurable systems management using an object model that offers a global solution. This solution is built on a system-level middleware that provides the infrastructure and tools for communication between different components in heterogeneous embedded systems. Several experiments were performed to test and evaluate each part of our proposed solution, and the obtained results are presented. These results demonstrate the excellent performance of our proposed solution.

Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities

In data security systems, general purpose processors (GPPs) are often extended by a cryptographic accelerator. The article presents three ways of extending GPPs for symmetric key cryptography applications. Proposed extensions guarantee secure key storage and management even if the system is facing protocol, software and cache memory attacks. The system is partitioned into processor, cipher, and key memory zones. The three security zones are separated at protocol, system, architecture and physical levels. The proposed principle was validated on Altera NIOS II, Xilinx MicroBlaze and Microsemi Cortex M1 soft-core processor extensions. We show that stringent separation of the cipher zone is helpful for partial reconfiguration of the security module, if the enciphering algorithm needs to be dynamically changed. However, the key zone including reconfiguration controller must remain static in order to maintain the high level of security required. We demonstrate that the principle is feasible in partially reconfigurable field programmable gate arrays (FPGAs) such as Altera Stratix V or Xilinx Virtex 6 and also to some extent in FPGAs featuring hardwired general purpose processors such as Cortex M3 in Microsemi SmartFusion FPGA. Although the three GPPs feature different data interfaces, we show that the processors with their extensions reach the required high security level while maintaining partial reconfiguration capability.

Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks

While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.