Abstract
Dynamically Reconfigurable FPGAs allow to accelerate the reconfiguration process downloading partial bitstreams to those areas created for that. The partial reconfiguration capability allows to share hardware resources between different tasks during the design lifecycle. In this paper we propose an algorithm based on Logic Score of preference (LSP) multicriteria decision method for floor planning, scheduling and order of deployment of these partial bitstreams during design lifecycle. The proposed method is well suited to be implemented in preemptive systems in which the deadline of a critical task can demand the preemption of a lower priority one.
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