Partial Bit Research Articles

On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers.

Novel hardware architectures for dynamic reconfigurable implementation of 64-bit MISTY1 and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips for secure IoT applications. The SRL32 primitive (Reconfigurable Look up Tables-RLUTs) and DPR (Dynamic Partial Reconfiguration) are employed to reconfigure single round MISTY1 / KASUMI algorithms on the run-time. The RLUT based architecture attains dynamic logic functionality without extra hardware resources by internally modifying the LUT contents. The proposed adaptive reconfiguration can be adopted as a productive countermeasure against malicious attacks with the added advantage of less reconfiguration time (RT). On the other hand, the block architecture reconfigures the core hardware by externally uploading the partial bit stream and has significant advantages in terms of low area implementation and power reduction. Implementation was carried out on FPGA, Xilinx Virtex 7. The results showed remarkable results with very low area of 668 / 514 CLB slices consuming 460 / 354 mW for RLUT and DPR architectures respectively. Moreover, the throughput obtained for RLUT architecture was found as 364 Mbps with very less RT of 445 nsec while DPR architecture achieved speed of 176 Mbps with RT of 1.1 msec. The novel architectures outperform the stand-alone existing hardware designs of MISTY1 and KASUMI implementations by adding the dynamic reconfigurability while at the same achieving high performance in terms of area and throughput. Design details of proposed unified architectures and comprehensive analysis is described.

A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier

A pipelined SAR ADC is proposed to achieve faster conversion by employing residue conversion and partial bit conversion in parallel to lessen timing constraints. Additionally, a varactor-based dynamic amplifier is adopted to improve linearity for a 10-b accuracy. The single-channel ADC achieves 1 GS/s with a peak SNDR 41.37 dB at a Nyquist input and consumes 9.4 mW.

Evolvable Hardware-Based Data Security System Using Image Steganography Through Dynamic Partial Reconfiguration

A highly secure communication method is essential for end users for the exchange of information which is not interpreted by an intruder. Cryptography plays a crucial role in the current and upcoming digital worlds, for secure data transmission in wired and wireless networks. Asymmetric and symmetric cryptographic algorithms encrypt data against vulnerable attacks and transfer to authenticated users. Steganography is a method for providing secure information with the help of a carrier file (text, video, audio, image, etc.). This paper proposes Deoxyribonucleic Acid (DNA)-based asymmetric algorithm which is used to encrypt the patient’s secret information and its performance is compared with ElGamal, RSA and Diffie–Hellman (DH) cryptographic algorithms. The proposed asymmetric algorithm is applied to image steganography which is used for encrypting and concealing the patient’s secret information in a cover image. The proposed method consumes less hardware resources with improved latency. Dynamic Partial Reconfiguration (DPR) allows to transform a selective area rather than complete shutdown of the entire system during bitstream configuration. Cryptosystem with DPR is designed, synthesized in Xilinx Vivado and simulated in Vivado simulator. The design is targeted at Basys3, Nexys4 DDR and Zync-7000 all-programmable SOC (AP SoC) architectures and programmed with secure partial bit files to avoid vulnerable attacks in the channel.

A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor

Energy consumption and data stability are vital requirement of cache in embedded processor. SRAM is a natural choice for cache memory owing to their speed and energy efficiency. Noise insertion to the SRAM cell during read is a serious problem which reduces its stability. A read disturbance free differential SRAM cell consisting of seven transistors is proposed here which increases cell stability along with maintaining the most desirable differential read technique for faster read. The read SNM of the proposed cell is 154%, 31% and 58% large than that of the conventional 6T-SRAM cell and 2 other 7T-SRAM cells [5,6] compared here. Various factors such as short circuit current reduction, use of single write access transistor, partial bit line swing etc. reduces the overall energy consumption of the proposed cell by 41% compared to 6T-SRAM cell. The proposed cell is also compared with an eight transistor based read disturbance free SRAM cell. The cell delay of the proposed cell is around 55% lesser than that of the 8T-SRAM cell. Besides CMOS the performance achievement of the proposed 7T-SRAM cell is also validated at miniaturized dimension of 20nm using FinFET based predictive technology model library.

RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS

DSP Application requires a fast computations & flex ibility of the design. Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. In this paper we are using mi croblaze soft core processor & ICAP Port to reconfi gure the FPGA at runtime. ICAP is accessed through a light-weight custom IP w hich requires bit stream length, go, and done signa l to interface to a system that provides partial bit stream data. The partial bit s tream is provided by the processor system by readin g the partial bit files from the compact flash card. Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules at run time. To change the partial bit stream we in terfaces a microblaze Soft processor & using a UART interface.ISE13.1 & PlanAhead is used for partial reconfiguration of FP GA .EDK is used for microblaze soft processor desig n & ICAP Interface .The simulation is done using Chip Scope Logic Analyzer & the complete hardware implementation is done on X ilinx VIRTEX -6 ML605 Platform.

Bit plane modification for improving MSE-near optimal DPCM-based block truncation coding

Abstract A hybrid method of block truncation coding (BTC) and differential pulse code modulation (DPCM) offers better visual quality than the standard BTC for small block sizes due to its inherent multitone representation. Recently, a two-level quantizer design method has been proposed to increase the coding performance of the DPCM-BTC framework. However, the design method is near optimal in the sense that its coding performance depends on the initial bit plane patterns. In this paper, we propose a bit plane modification (BPM) algorithm to achieve further performance improvement. The BPM algorithm, inspired by error diffusion, effectively distributes large quantization error at a certain pixel to its neighboring pixels having small quantization errors by changing partial bit patterns. Experimental results show that the proposed algorithm successfully achieves much higher coding performance than various conventional BTC methods. The average PSNR performance of the proposed method is 2.31 dB, 5.15 dB, and 5.15 dB higher than that of BTC, DPCM-BTC, and a recently developed BTC scheme using error diffusion and bilateral filtering, respectively.

Partial Bit Strings Pruning Channel Assignment in Multi-Rate Multi-Channel Wireless Networks

IEEE 802.11 based wireless networks are extensively used in mesh, ad hoc, and sensor networks due to less expense and easier deployment. IEEE 802.11a/b/g standard supports multi-rate and multi-channel settings to facilitate network transmissions. Many researchers focus on maximizing network throughput and propose channel assignment algorithms in IEEE based multi-rate multi-channel (M2) wireless networks. Less works are devoted to the study of network capacity in M2 wireless networks. In our observation, static channel assignment algorithms for maximizing network throughput may limit network capacity, and the improvement on network capacity comes mainly from higher data rate communication links. Therefore, we model the optimization problem and derive the optimization formula in detail. Subsequently, we propose an efficient channel assignment algorithm, Partial Bit Strings Pruning (PBSP) channel assignment to maximize network capacity. The results of associated simulations show that the performance of our PBSP channel assignment algorithm is superior to the algorithm based on the well-know minimum-interference approach.

Indifferentiable deterministic hashing to elliptic and hyperelliptic curves

At Crypto 2010, Brier et al. proposed the first construction of a hash function into ordinary elliptic curves that was indifferentiable from a random oracle, based on Icart’s deterministic encoding from Crypto 2009. Such a hash function can be plugged into any cryptosystem that requires hashing into elliptic curves, while not compromising proofs of security in the random oracle model. However, the proof relied on relatively involved tools from algebraic geometry, and only applied to Icart’s deterministic encoding from Crypto 2009. In this paper, we present a new, simpler technique based on bounds of character sums to prove the indifferentiability of similar hash function constructions based on essentially any deterministic encoding to elliptic curves or curves of higher genus, such as the algorithms by Shallue, van de Woestijne and Ulas, or the Icart-like encodings recently presented by Kammerer, Lercier and Renault. In particular, we get the first constructions of well-behaved hash functions to Jacobians of hyperelliptic curves. Our technique also provides more precise estimates on the statistical behavior of those deterministic encodings and the hash function constructions based on them. Additionally, we can derive pseudorandomness results for partial bit patterns of such encodings.

An efficient scalable intra coding algorithm for spatial scalability in enhancement layer

Scalable video coding (SVC) is attractive due to the capability of reconstructing lower resolution or lower quality signals from partial bit streams, which allows for simple solutions adaptted to network and terminal capabilities. This article addresses the spatial scalability of SVC and proposes an efficient H.264-based scalable intra coding algorithm. In comparison with precious single layer intra prediction (SLIP) method, the proposed algorithm aims to improve the intra coding performance of the enhancement layer by a new inter layer intra prediction (ILIP) method. The main idea of ILIP is that up-sampled and reconstructed pixels of the base layer are very useful to predict and encode those pixels of the enhancement layer, especially when those neighbouring pixels are not available. Experimental results show that the peak signal to noise ratio (PSNR) data of luminance component of encoded frames are improved, and both bit-rates and computation complexity are maintained very well. For sequence Football, the average increase of PSNR is up to 0.21 dB, while for Foreman and Bus, they are 0.14 dB and 0.17 dB, respectively.

Bit-Based SLM Schemes for PAPR Reduction in QAM Modulated OFDM Signals

In this paper, we propose two bit-based selected mapping (SLM) schemes for reducing peak to average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) signals with quadrature amplitude modulation (QAM), called bitwise SLM (BSLM) and partial bit inverted SLM (PBISLM). Contrary to the conventional SLM which rotates the phases of QAM symbols in the frequency domain, the proposed schemes change the magnitudes as well as the phases of QAM symbols by applying binary phase sequences to the binary data sequence before mapped to QAM symbols. Simulation results show that the proposed schemes have better PAPR reduction performance with shaping gain than the conventional SLM scheme for the QAM modulated OFDM signals, especially for the small number of subcarriers.

Low-Power Embedded Processor Design Using Branch Direction

This paper presents a wordline gating logic for reducing unnecessary BTB accesses. Partial bit of the branch predictor was simultaneously recorded in the middle of BTB to prevent further SRAM operation. Experimental results with embedded applications showed that the proposed mechanism reduces around 38% of BTB power consumption.

Robust low bit‐rate transmission using multiple‐PBDBS (MPBDBS) approach

Recently, Gao and Tu presented an efficient algorithm for robust low bit‐rate video transmission by using a partial backward decodable bit stream (PBDBS) approach. In this paper, we first present a multiple‐PBDBS (MPBDBS) approach to improve on the previous PBDBS approach. Next a mathematical theory is provided to minimize the error propagation length in each group of blocks (GOB). Further, a novel MPBDBS‐based algorithm is presented for robust video transmission. Experimental results demonstrate that our proposed MPBDBS‐based algorithm has better image quality when compared to the previous PBDBS‐based algorithm, but has some bit‐rate and execution‐time degradation. In our experiments, both single and two‐bit error models are investigated.

Partial bit delay correlative modulation used to improve the dispersion tolerance of an optical duobinary system

Phase effect of the optical duobinary (ODB) modulation on the chromatic dispersion (CD) tolerance is more important than the ODB modulation-induced bandwidth effect. To show this, we evaluate, respectively, the filter bandwidth effect and the phase effect of the partial bit delay correlative modulation (PBDCM) on the CD tolerance. Due to the cancellation between the CD-induced and the PBDCM-induced phase effects, the PBDCM method can increase the CD-limited transmission to 2 ??? 3 times of that using standard 1-bit delay modulation, while the optimized filter bandwidth method can increase the transmission by 50% or less, depending on the input signal format. The PBDCM can be physically realized by adjusting the delay time of the delay-and-add circuit in the conventional duobinary transmitter (without lower-pass filter). These conclusions are also valid for systems having non-negligible polarization-mode dispersion (PMD) and polarization dependent loss (PDL).

A Partition Decoding for Reed-Solomon Codes Based on Partial Bit Reliability

This study presents a partition decoding algorithm for an (mN, mK) binary image of an (N, K) Reed Solomon code over GF(2 m ). A proposed partition decoding algorithm includes several steps. Firstly we compute m's segmental reliability values of a received subvector of length N and determine which one with the least segmental reliability value. A permutation is performed on a binary generator matrix of an RS code and a received vector, which are then partitioned into two submatrices and two subvectors. The first subvector of length N(m - 1) associate with the first submatrix and the second subvector with the least segmental reliability value relates to the second submatrix. Secondly, an MLD algorithm based on the first submatrix is employed to decode the first subvector. Thirdly, an MLD algorithm based on a BCH generator matrix is employed to decode the second subvector. A codeword is finally outputted after performing the inverse permutation on a concatenation of code vectors decoded from these two decoding. The error coefficient and minimum Hamming distance of the code sequences generated in the first submatrix are fewer than those of a corresponding binary image. Simulation results show that at low and medium SNRs, the effect of error coefficient becomes more significant than that of minimum Hamming distance. Minimum Hamming distances and error coefficients of code sequences generated in the first submatrices and their corresponding binary images have been explored in this work. For (60,36,7)RS (b) , (155,125,7)RS (b) , (155,105,11)RS (b) and (889, 847,7))RS (b) being binary images of (15,9,7)RS, (31,25,7)RS, (31,21,11)RS and (127,121,7)RS codes respectively, with BPSK signaling over AWGN channels, the decoding performances of proposed partition decoding algorithm are a little poorer than those of MLD [10] by 1.0 to 1.4dB at BER 10 -5 , but better than those of GMD decoding [1] by 0.8 to 1.1 dB. For SNR of 5 dB, proposed partition decoding algorithm only takes 50% to 60% amount of bit operations of an MLD [10]. Under a constraint of decoding complexity, proposed partition decoding algorithm may be a solution to decode binary images of long RS codes, which provides superior performance to GMD decoding with much lower complexity than an MLD.

Overview of the Scalable Video Coding Extension of the H.264/AVC Standard

With the introduction of the H.264/AVC video coding standard, significant improvements have recently been demonstrated in video compression capability. The Joint Video Team of the ITU-T VCEG and the ISO/IEC MPEG has now also standardized a Scalable Video Coding (SVC) extension of the H.264/AVC standard. SVC enables the transmission and decoding of partial bit streams to provide video services with lower temporal or spatial resolutions or reduced fidelity while retaining a reconstruction quality that is high relative to the rate of the partial bit streams. Hence, SVC provides functionalities such as graceful degradation in lossy transmission environments as well as bit rate, format, and power adaptation. These functionalities provide enhancements to transmission and storage applications. SVC has achieved significant improvements in coding efficiency with an increased degree of supported scalability relative to the scalable profiles of prior video coding standards. This paper provides an overview of the basic concepts for extending H.264/AVC towards SVC. Moreover, the basic tools for providing temporal, spatial, and quality scalability are described in detail and experimentally analyzed regarding their efficiency and complexity.

Independent and Simultaneous Monitoring of Chromatic and Polarization-Mode Dispersion in OOK and DPSK Transmission

We propose and demonstrate a novel technique for a simultaneous chromatic and first-order polarization-mode-dispersion (PMD) monitoring method using a partial bit delay Mach-Zehnder interferometer (MZI) with radio-frequency (RF) clock tone monitoring. RF clock tones at the output of the two branches of the MZI behave oppositely with increasing chromatic dispersion (CD) which improves the sensitivity of the measurement. The technique increases CD monitoring sensitivity over standard clock tone methods by a factor of two for a nonreturn-to-zero intensity modulation format and a factor of five for a differential-phase-shift-keying modulation format. The accuracy of PMD monitoring is also enhanced. Moreover, the partial bit delay allows the signal to pass through the constructive branch of the MZI with no observable degradation of the signal quality, allowing it to be normally detected by a receiver

Average-Case and Smoothed Competitive Analysis of the Multilevel Feedback Algorithm

In this paper, we introduce the notion of smoothed competitive analysis of online algorithms. Smoothed analysis has been proposed by Spielman and Teng [25] to explain the behavior of algorithms that work well in practice while performing very poorly from a worst-case analysis point of view. We apply this notion to analyze the multilevel feedback algorithm (MLF) to minimize the total flow time on a sequence of jobs released over time when the processing time of a job is only known at time of completion. The initial processing times are integers in the range [1, 2K]. We use a partial bit randomization model, i.e., the initial processing times are smoothed by changing the k least significant bits under a quite general class of probability distributions. We show that MLF admits a smoothed competitive ratio of O((2k/σ)3 + (2k/σ)2 2K-k), where σ denotes the standard deviation of the distribution. In particular, we obtain a competitive ratio of O(2K-k) if σ = Θ(2k). We also prove an Ω(2K-k) lower bound for any deterministic algorithm that is run on processing times smoothed according to the partial bit randomization model. For various other smoothing models, including the additive symmetric smoothing one, which is a variant of the model used by Spielman and Teng [25], we give a higher lower bound of Ω(2K). A direct consequence of our result is also the first average-case analysis of MLF. We show a constant expected ratio of the total flow time of MLF to the optimum under several distributions including the uniform one.

Advances in Scalable Video Coding

Scalable video coding is attractive due to the capability of reconstructing lower resolution or lower quality signals from partial bit streams. This allows for simple solutions in adaptation to network and terminal capabilities. Different modalities of scalability are specified by video coding standards like MPEG-2 and MPEG-4. This paper gives a short overview over these techniques and analyzes in more detail the encoder/decoder drift problem, which is the major reason why scalable coding has been significantly less efficient than single-layer coding in most of these implementations. Only recently, new scalable video coding technology has evolved, which seems to close the gap of compression performance compared to state of the art single-layer video coding. New methods of efficient enhancement layer prediction were developed to improve traditional (motion-compensated hybrid) scalable coders, providing more flexible compromises on the drift problem. As a new technology trend, motion-compensated spatiotemporal wavelet coding has matured which entirely discards the drift and allows most flexible combinations of spatial, temporal, and signal-to-noise ratio (SNR) scalability with fine granularity over a broad range of data rates.