Parity Circuits Research Articles

Grammatical Evolution of Complex Digital Circuits in SystemVerilog

The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit times 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up–Down Counter circuits at a more abstract level other than gate level—register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit times 64-bit and 128-bit times 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit times N-bit multiplier. The Adder (6.4times), Multiplier (10.7times) and Selective Parity (6.7times) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog.

An energy efficient high-speed quantum-dot based full adder design and parity gate for nano application

Quantum-dot cellular automata (QCA) are novel prominent emerging nano-computational nanoelectronics technology at the nanoscale. It facilitated computation paradigms and promises an alternative good solution to traditional transistor CMOS technology with faster speed, very low energy dissipation, higher scale integration, small size, low latency/delay of circuits, and higher switching frequency. It is one of the most valuable nanotechnologies (or Nanotech) that effort to fabricate general computational at the nanoscopic-scale by commanding the position of electrons. In this paper, we have proposed the design of novel robust full adder, testable even and odd parity circuits using coplanar single layer in quantum-dots cellular automata nanotechnology. The proposed design of full adder circuits used only 36 quantum dots cells, occupied a design area of 0.04 µm2, and minimum delay count is 0.75 clock cycles. The proposed circuit’s investigated by novel QCADesigner-E (Energy) tool on using coherence vector (w/Energy) engine and optimized the energy-dissipation (ED) of full adder circuit. In the proposed design do not use coplanar multilayer and 45-degree rotated cells but used regular synchronized clock cycle and minimum quantum-dots cells. Therefore overall manufacturability of the robust full adder circuits significantly more improves as compared to the existing design. The presented robust full adder design have been calculated the total ED (Sum_Ebath) is 1.70e−002 eV (Error: +/- −1.63e−003 eV), and average ED/cycle (Avg_Ebath) is 1.54e−003 eV (Error: +/- −1.48e−004 eV).

Implementation of Even Parity Circuit with Strong Signal Based on Quantum-Dot Cellular Automata

Implementation of Even Parity Circuit with Strong Signal Based on Quantum-Dot Cellular Automata

Designing efficient QCA even parity generator circuits with power dissipation analysis

In the era of modern digital technology, highly scaled and ultra-low power consuming devices have drawn a considerable attention. Quantum-dot Cellular Automata (QCA) are such an emerging nanotechnology that dispenses a highly dense and ultra-low power consuming binary information encoding paradigm. This potential merit instigated the QCA to be an excellent alternative to the conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this paper, we are going to introduce highly scaled and ultra-low power consuming 4, 8, 16 and 32-bit even parity generator circuits. The proposed 4-bit even parity circuit requires 72% fewer cells and occupies 78% less area as compared to previous best designs. Besides, the proposed 32-bit even parity design occupies only 0.283µm2 whereas the previous best reported design occupies 2.08µm2 area. The simulation outcomes reveal that our presented designs have considerable enhancements in terms of cell counts, area and power consumption aspects. In addition, to design and verify the proposed layout, QCADesigner is employed and power dissipation is estimated using QCAPro.

All-Optical Parity Circuits Using Nonlinear Directional Coupler

Since in the previous existing optical designs, the electronic-optic-electronic conversion has not been completely eliminated. Construction of the optical circuits with nonlinear waveguides can overcome this drawback. We have developed a nonlinear directional coupler theory to describe novel all-optical parity circuits. By using three channels, appropriate adjusting of the refractive indices, and selecting the correct length for coupling event, even/odd parity circuits can be obtained. The operation of these circuits is simulated with the aid of RSoft CAD-Layout (BeamPROP) simulator. Towards the end of the work, we compared the speed of our proposed novel circuit with the existing optical designs and also electronic structure of which we have a better result. Index Terms—Optical computing, Parity circuit, Network security, nonlinear behaviour, Coupled mode theory

Boolean autoencoders and hypercube clustering complexity

We introduce and study the properties of Boolean autoencoder circuits. In particular, we show that the Boolean autoencoder circuit problem is equivalent to a clustering problem on the hypercube. We show that clustering m binary vectors on the n-dimensional hypercube into k clusters is NP-hard, as soon as the number of clusters scales like \({m^\epsilon (\epsilon >0 )}\) , and thus the general Boolean autoencoder problem is also NP-hard. We prove that the linear Boolean autoencoder circuit problem is also NP-hard, and so are several related problems such as: subspace identification over finite fields, linear regression over finite fields, even/odd set intersections, and parity circuits. The emerging picture is that autoencoder optimization is NP-hard in the general case, with a few notable exceptions including the linear cases over infinite fields or the Boolean case with fixed size hidden layer. However learning can be tackled by approximate algorithms, including alternate optimization, suggesting a new class of learning algorithms for deep networks, including deep networks of threshold gates or artificial neurons.

Combining ESOP minimization with BDD-based decomposition for improved FPGA synthesis

This paper proposes a novel method to improve the utilization efficiency and performance of field-programmable gate arrays (FPGAs). The proposed method, ExorBDD, uses a stage of exclusive-sum-of-product (ESOP) minimization, followed by a stage of decomposition using binary decision diagrams (BDDs). For exclusive OR (XOR)-intensive circuits, experiments were conducted on 19 MCNC benchmark parity circuits (ranging from 5 to 25 inputs), as they are the most representative case of XOR-intensive circuits. The results using the proposed approach show significant improvements over Exorcism4, BDS, and commercial tools. On average, the new approach uses only 30.3% as many look-up tables as are used by Xilinx tools (and only 16.4% in comparison to Altera). On average, the new approach has a maximum combinational path delay of 89.2% compared to the delay with Xilinx tools (80.3% compared to Altera). Experiments were also conducted on non-XOR-intensive circuits. These results show that ExorBDD also performs well for arbitrary circuits.

Random oracles separate PSPACE from the polynomial-time hierarchy

By confirming a conjecture of First, Saxe, and Sipser (1981) on the size of constant-depth parity circuits, Yao (1985) has completed the proof that PSPACE is separated from the polynomial-time hierarchy by some oracle. Cai (1986) modified Yao's complex argument to prove that this separation occurs relative to almost every oracle. We prove that this result actually follows immeadiately from Yao's theorem, using a simple construction of Ajtai and Ben-Or (1984) to eliminate randomization in bounded-depth Boolean circuits.