Parasitic Series Resistance Research Articles

Engineering vertical morphology with nanoparticulate organic photovoltaic devices

Sequential deposition of monolayers, composed of nanoparticles with varied donor-acceptor concentration ratios, has allowed the fabrication of organic photovoltaic (OPV) active layers with engineered vertical morphology. The performance of polymer-polymer poly(9,9-dioctylfluorene-co-bis-N,N-phenyl-1,4-phenylenediamine):poly[(9,9-di-n-octylfluorenyl-2,7-diyl)-alt-(benzo[2,1,3]thiadiazol-4,8-diyl)] (PFB:F8BT) and polymer-fullerene poly(3-hexylthiophene):phenyl C61 butyric acid methyl ester (P3HT:PCBM) nanoparticulate (NP), graded nanoparticulate (GNP) and bulk heterojunction (BHJ) OPV devices have been studied. For both material systems the highest device VOC is observed for the graded structure. Furthermore, thermal treatments can be used to alleviate parasitic series resistance in the GNP devices, thus improving device JSC and efficiency. Overall, this work shows that the nanoparticle approach provides a new experimental lever for morphology control in OPV devices.

A new unified mobility extraction technique of In0.7Ga0.3As QW MOSFETs

Conventional methods to extract an effective mobility ( $\mu _{\mathrm {eff}}$ ) in a metal–oxide–semiconductor field-effect-transistor (MOSFET) tend to ignore the portions of parasitic components of the device. This can cause a substantial error in the extracted value of the effective mobility. In this letter, we have proposed a unified procedure that enables to accurately capture each portion of parasitic series resistance ( $R_{{\mathrm {SD}}}$ ) and parasitic gate capacitance ( $C_{g\_{}{\mathrm {par}}}$ ) components. Then, we have investigated the impact of the parasitic components on the extracted value of the effective mobility in a gate-last surface-channel In0.7Ga0.3As quantum-well MOSFET. We have found that the extracted effective mobility using our method turns out to be independent upon gate length ( $L_{{\mathrm {g}}}$ ) from 10 to $4~\mu \text{m}$ , which verifies the accuracy of the approach proposed in this letter.

Outwitting the series resistance in scanning spreading resistance microscopy

The performance of nanoelectronics devices critically depends on the distribution of active dopants inside these structures. For this reason, dopant profiling has been defined as one of the major metrology challenges by the international technology roadmap of semiconductors. Scanning spreading resistance microscopy (SSRM) has evolved as one of the most viable approaches over the last decade due to its excellent spatial resolution, sensitivity and quantification accuracy. However, in case of advanced device architectures like fins and nanowires a proper measurement of the spreading resistance is often hampered by the increasing impact of parasitic series resistances (e.g. bulk series resistance) arising from the confined nature of the aforementioned structures. In order to overcome this limitation we report in this paper the development and implementation of a novel SSRM mode (fast Fourier transform-SSRM: FFT-SSRM) which essentially decouples the spreading resistance from parasitic series resistance components. We show that this can be achieved by a force modulation (leading to a modulated spreading resistance signal) in combination with a lock-in deconvolution concept. In this paper we first introduce the principle of operation of the technique. We discuss in detail the underlying physical mechanisms as well as the technical implementation on a state-of-the-art atomic force microscope (AFM). We demonstrate the performance of FFT-SSRM and its ability to remove substantial series resistance components in practice. Eventually, the possibility of decoupling the spreading resistance from the intrinsic probe resistance will be demonstrated and discussed.

Effect of CdS Processing Conditions on the Properties of CdS/Si Diodes and CdS/CdTe Thin-Film Solar Cells

Thermally evaporated n-type CdS thin films were studied to determine the influence of substrate deposition temperature and postdeposition thermal annealing on their electrical, optical, and structural properties. It is shown that although increasing substrate temperature during deposition from room temperature to 200 $^{\circ }$ C results in CdS films exhibiting high optical transmittance as well as large grain size, deposition temperatures above 50 $^{\circ }$ C lead to significant degradation in carrier concentration and mobility. Postdeposition thermal annealing of CdS films deposited at room temperature is shown to yield CdS films with superior electrical and optical characteristics, resulting in an electron mobility of 17.45 cm $^{2}$ /Vs for films annealed at 200 $^{\circ }$ C. The electrical characteristic of n-CdS/p-Si heterojunction diodes indicated that postdeposition thermal annealing reduced parasitic series resistance and decreased the diode ideality factor to a value of 1.384 for films annealed at 300 $^{\circ }$ C, suggesting a reduction in recombination centers in the vicinity of the CdS/Si interface. In n-CdS/p-CdTe heterojunction solar cells, the photovoltaic cell parameters indicated that the deposition of CdS films at room temperature produces better performing cells with the substrate temperature required during the thermal deposition of CdTe acting as postdeposition annealing for the underlying CdS thin film.

Coupled inductance design for grid‐connected photovoltaic inverters

The coupled inductor with larger inductance is beneficial to improve the inverter output current quality but instead of causing additional power loss due to the increased series parasitic resistance. Conversely, once the inductance is turned down, the part of the filter power loss caused by the growing ripple current becomes gathering. To clarify the ratio of the ripple and fundamental current on the coupled inductor power loss, a generalised algebraic formula based on the LC filter model is presented to predict the ripple current magnitude at specific fundamental current in each switching cycle. The coupled inductor power loss contributed by the ripple current and the fundamental current can be, respectively, predicted under various inductances and thus in favour of choosing appropriate inductor parameter for power efficiency optimisation. Although this approach is derived based on the LC filter, it is also available for the LCL filter by using the model reduction technique. A guideline of a unity inductance split factor for the LCL filter is proven with maximum fundamental current gain and is adopted for choosing the grid-side and inverter-side inductances of the LCL filter in this study. Experimental results from various ratings of the grid-tied single phase inverter validate the feasibility of the proposed strategy with satisfactory power efficiency.

The Study of 0.34 THz Monolithically Integrated Fourth Subharmonic Mixer Using Planar Schottky Barrier Diode

A planar Schottky barrier diode with the designed Schottky contact area of approximately 3 μm2 is developed on gallium arsenide (GaAs) material. The measurements of the developed planar Schottky barrier diode indicate that the zero-biased junction capacitance Cj0 is 11.0 fF, the parasitic series resistance RS is 3.0 Ω, and the cut off frequency fT is 4.8 THz. A monolithically integrated fourth subharmonic mixer with this diode operating at the radio frequency (RF) signal frequency of 0.34 THz with the chip area of 0.6 mm2 is implemented. The intermediate frequency (IF) bandwidth is from DC to 40 GHz. The local oscillator (LO) bandwidth is 37 GHz from 60 to 97 GHz. The RF bandwidth is determined by the bandwidth of the on chip antenna, which is 28 GHz from 322 to 350 GHz. The measurements of the mixer demonstrated a conversion loss of approximately 51 dB.

Fast Fourier transform scanning spreading resistance microscopy: a novel technique to overcome the limitations of classical conductive AFM techniques

A new atomic force microscopy (AFM)-based technique named fast Fourier transform scanning spreading-resistance microscopy (FFT-SSRM) has been developed. FFT-SSRM offers the ability to isolate the local spreading resistance (Sr) from the parasitic series resistance (probe, bulk, and back contact). The parasitic series resistance limits the use of classical SSRM in confined volumes and on very highly doped materials, two increasingly important situations in nanoelectronic components. This is realized via a force modulation at controlled frequency (affecting the SR component) and the extraction of the resistance amplitude at the modulation frequency, performing an FFT-based lock-in deconvolution. A systematic evaluation of the FFT-SSRM performances (i.e., resolution, dynamic range, sensitivity, and repeatability) is presented. The impact of various parameters (i.e., modulation frequency and amplitude or cutoff frequency of the current amplifier) on the performances of FFT-SSRM has been evaluated. We demonstrate the possibility to overcome sensitivity losses due to tip saturation in highly doped material and the utility of the technique in two different structures, presenting isolated and confined volumes.

An analytical mathematical modeling to extract the parameters of solar cell from implicit equation to explicit form

It was developed a new mathematical model to simplify the nonlinearity and complexity of mathematical equation of solar cell. Due of the complex characteristics the researcher used the iterative calculations to determine the maximum power point, fill factor, ideality factor, and parasitic series and shunt resistances of solar cell. We proposed a mathematical study based on derivation of basically nonlinear model of solar cell and normalized the current density and voltage to simplify the equation model. The new proposed model is applicable to a large variety of solar cells. Due to its mathematical simplicity the model will be suitable and easy for analytical modeling of complex current–voltage equation of solar cell on two and three dimensionals. The new analytical model equation have been tested and compared with the experimental results to add validity to the model.

Accurate Modeling of the Polysilicon-Insulator-Well (PIW) Capacitor in CMOS Technologies

Abstract. A practical method enabling rapid development of an accurate device model for the PIW MOS capacitor is introduced. The simultaneous improvement in accuracy and development time can be achieved without having to perform extensive measurements on specialized test structures by taking advantage of the MOS transistor model parameters routinely extracted in support of analog circuit design activities. This method affords accurate modeling of the voltage coefficient of capacitance over the entire range of operating voltages. Furthermore, a compact subcircuit representation is proposed, which takes the distributed parasitic series resistance associated with the PIW capacitor into account, thereby allowing modeling of the limitations imposed on high-frequency performance as well as the quality factor. The validity of the proposed method is verified based on capacitance versus voltage measurements performed using a test vehicle fabricated in a submicron CMOS technology.

A three-mask process for fabricating vacuum-sealed capacitive micromachined ultrasonic transducers using anodic bonding.

This paper introduces a simplified fabrication method for vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays using anodic bonding. Anodic bonding provides the established advantages of wafer-bondingbased CMUT fabrication processes, including process simplicity, control over plate thickness and properties, high fill factor, and ability to implement large vibrating cells. In addition to these, compared with fusion bonding, anodic bonding can be performed at lower processing temperatures, i.e., 350°C as opposed to 1100°C; surface roughness requirement for anodic bonding is more than 10 times more relaxed, i.e., 5-nm rootmean- square (RMS) roughness as opposed to 0.5 nm for fusion bonding; anodic bonding can be performed on smaller contact area and hence improves the fill factor for CMUTs. Although anodic bonding has been previously used for CMUT fabrication, a CMUT with a vacuum cavity could not have been achieved, mainly because gas is trapped inside the cavities during anodic bonding. In the approach we present in this paper, the vacuum cavity is achieved by opening a channel in the plate structure to evacuate the trapped gas and subsequently sealing this channel by conformal silicon nitride deposition in the vacuum environment. The plate structure of the fabricated CMUT consists of the single-crystal silicon device layer of a silicon-on-insulator wafer and a thin silicon nitride insulation layer. The presented fabrication approach employs only three photolithographic steps and combines the advantages of anodic bonding with the advantages of a patterned metal bottom electrode on an insulating substrate, specifically low parasitic series resistance and low parasitic shunt capacitance. In this paper, the developed fabrication scheme is described in detail, including process recipes. The fabricated transducers are characterized using electrical input impedance measurements in air and hydrophone measurements in immersion. A representative design is used to demonstrate immersion operation in conventional, collapse-snapback, and collapse modes. In collapsemode operation, an output pressure of 1.67 MPa pp is shown at 7 MHz on the surface of the transducer for 60-Vpp, 3-cycle sinusoidal excitation at 30-V dc bias.

Realization of low contact resistance close to theoretical limit in graphene transistors

Realizing low contact resistance between graphene and metal electrodes remains a well-known challenge for building high-performance graphene devices. In this work, we attempt to reduce the contact resistance in graphene transistors and further explore the resistance limit between graphene and metal contacts. The Pd/graphene contact resistance at room temperature is reduced below the 100 Ω·μm level both on mechanically exfoliated and chemical-vapor-deposition graphene by adopting high-purity palladium and high-quality graphene and controlling the fabrication process to not contaminate the interface. After excluding the parasitic series resistances from the measurement system and electrodes, the retrieved contact resistance is shown to be systematically and statistically less than 100 Ω·μm, with a minimum value of 69 Ω·μm, which is very close to the theoretical limit. Furthermore, the contact resistance shows no clear dependence on temperature in the range of 77–300 K; this is attributed to the saturation of carrier injection efficiency between graphene and Pd owing to the high quality of the graphene samples used, which have a sufficiently long carrier mean-free-path. Open image in new window

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs

In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) for the sub-10 nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara). Compared with low-κ spacers, high-κ spacers exhibit a higher on/off-current ratio with a lower RSD, but show severe degradation in their AC performance owing to a higher Cpara. Considering the trade-off between RSD and Cpara, optimal geometry-dependent κsp values at various supply voltages (VDD) are determined using gate delay (CV/I) and current-gain cutoff frequency (fT). We found that as LEXT and VDD decrease and Dnw increases, the optimal κsp value shifts from the high-κ to low-κ regime.

Effect of thermal annealing on the optical and electrical properties of boron doped a-SiOx:H for thin-film silicon solar cell applications

The p-type layer in a p-i-n thin-film solar cell plays a crucial role in determining efficiency. The requirements for p-type layer films are high optical band gap (Eg), narrow valence band tail to minimize optical absorption, high dark conductivity, and low activation energy to reduce the parasitic series resistance of the solar cell. We investigated the effects of temperature during film growth and post-deposition thermal annealing on the optical and electronic properties of p-type amorphous silicon oxide films (p-a-SiOx:H) for thin-film silicon solar cell applications. The activation energy of thermally annealed p-a-SiOx:H film prepared at low substrate temperature decreased from 0.72eV to 0.56eV with similar Eg. Our improvements are explained in the changed ratio of conjugation with the three- and four-fold coordinated boron atoms by the shift of the B (1s) X-ray photoelectron spectrum. Taking into account the reversible electrical change by thermal annealing while maintaining high optical properties, we propose necessary process-procedure conditions for obtaining high photovoltaic performance in thin-film-Si solar cells with high-quality p-a-SiOx:H. We carried out device modeling of p-i-n junction amorphous silicon solar cells by employing a thermal annealing effect on p-type a-SiOx:H layer, using an advanced semiconductor analysis simulator. Due to reduced Ea with high Eg of p-type a-SiOx:H layer after thermal annealing, the solar cell performance of the open circuit voltage, fill factor, and conversion efficiency improved by 11.1%, 60.42%, and 53.75%, respectively.

Cold isostatic pressing of screen-printed dielectric for power electronics passive component integration

This paper focuses on the study of high-capacitance embedded capacitors for power electronics applications, manufactured by the screen-printing technique. Thick film ferroelectric ceramic was printed on Ag/Al2O3 substrates and dried at 120 °C, then a pre-treatment was applied by cold isostatic pressing (CIP) before sintering. A comparison of the physico-chemical and electrical properties of the non-CIP and CIP samples is made. The results show that the thick film samples pre-treated by CIP have higher permittivity and higher dielectric strength compared to the untreated ones. The capacitor samples with CIP pre-treatment also exhibit higher capacitances, lower parasitic equivalent series inductance and series resistance; all key intrinsic dielectric properties relevant for applications. We propose the use of this process for obtaining the embedded capacitors that allow for high-capacitance values for decoupling and filtering in power electronics applications.

Effects of tunnelling current on millimetre-wave IMPATT devices

In this paper, the influence of tunnelling on the RF performance of millimetre-wave (mm-wave) impact ionisation avalanche transit time (IMPATT) diodes operating in mixed tunnelling and avalanche transit time mode is studied by taking into account the parasitic series resistance of the device. The results show that the parasitic resistance of mm-wave IMPATTs increases and consequently the power delivered by the device decreases due to the consequence of band-to-band tunnelling. The critical background doping concentration and operating frequency are found to be 5.0 × 1023 m−3 and 260 GHz, respectively, above which the influence of tunnelling on the RF performance of the device becomes predominant.

Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current

Strained-Ge is a promising channel material for future CMOS nodes due to its very high hole mobility [1] and compatibility with existing processes. In comparison to Si, high quality dielectric interfaces for Ge are challenging due to the lack of an ideal native oxide. In this work, for the first time, we show an extremely-scaled (EOT < 5 Å), high quality dielectric on s-Ge. CV measurements of a MOS capacitor structure show areal capacitance scaling, little hysteresis, and low gate leakage current (< 0.2 A/cm2).The epitaxial structure (shown in Fig. 1(a)) was grown by low-pressure CVD, and the s-Ge layer is compressively strained (2.3% biaxial) due to the lattice mismatch with the relaxed Si0.55Ge0.45 virtual substrate. The epitaxial wafer was cleaved into pieces, and a 5-minute 1:10 (HCl:H2O) clean was performed prior to atomic layer deposition (ALD) of 1 minute O3/~3 nm HfO2 (both at 250 °C), followed by ~10 nm of TiN at 300 °C. After ALD, Al contacts were sputtered and patterned followed by a 30-minute forming gas anneal at 450 °C. The final MOS capacitor structure (Fig. 1(a)) reflects the loss in the s-Ge due to the HCl clean and O3 oxidation.CV measurements of a 100×100 µm MOS capacitor show a CET of 8.6 Å (Fig. 2). Large frequency dispersion exists for frequencies > 50 kHz due to large series resistance likely caused by a 500 meV valence band offset [2] between s-Ge and Si0.55Ge0.45 (Fig. 1(b)). The IV measurements (Fig. 3) show small gate leakage current (< 0.2 A/cm2), which translates to IG < 20 pA/µm for LG = 10 nm, well below ITRS requirements [3].Quasistatic one-dimensional self-consistent coupled Poisson-Schrödinger electrostatic simulations were performed in order to extract EOT. A strain-dependent 6×6 k∙p Hamiltonian (with deformation potentials from [2]) was used to calculate hole quantization in the s-Ge layer. In accordance with [4], a 2.1 eV valence band offset between Ge and GeOx was used in the simulations (Fig. 1(b)). The 500 meV valence band offset between between s-Ge and Si0.55Ge0.45creates a deep quantum well confining most of the holes in the s-Ge layer.Fig. 5 shows the 10 kHz experimental CV in addition to simulated quasistatic CV curves for structures with varying EOT. The mismatch of the simulated and experimental curves in strong hole accumulation is due to both a large series resistance (Rs ~ 0.1 Ω∙cm2) and gate leakage, which causes a sizable error when transforming the measured impedance to a two-element parallel capacitance CP , parallel conductance GP circuit model [5]. A circuit model (inset Fig. 6) incorporating parasitic gate tunneling conductance Gt and series resistance Rs is applied to an ideal simulated CV in order to recover the measured CV result, yielding an extracted EOT of 4.9 Å (Fig. 6). This is the smallest known EOT for a high quality dielectric on s-Ge published to date. Other recent results include a 7-Å EOT on s-Ge [6], and an 8-Å CET on unstrained Ge [7].

Improved current spreading performance of a GaN-based light-emitting diode with a stair-like ITO layer

A GaN-based light-emitting diode (LED) with a stair-like ITO layer is studied. The stair-like ITO structure is achieved by using a simple wet etching process. The current distribution could be adjusted by the different thickness of each step in this stair-like ITO layer. The current injected from p-pad is forced to be spread outside by the thicker ITO layer below the p-pad, which exhibits larger parasitic series resistance, instead of flowing downward directly. The current spreading effect could be enhanced. As compared with a conventional LED, at 20mA, the studied device with a stair-like ITO layer shows 13.8% improvement in light output power. A lower turn-on voltage is also achieved.

Temperature dependant electrical properties of formyl-TIPPCu(II)/p-Si heterojunction diode

This paper reports the temperature dependent electrical characterization of formyl- TIPPCu (II)/p- Si heterojunction diode which was fabricated by growing thin films of formyl- TIPPCu (II) on the p-type silicon substrate by thermal sublimation technique. The variation in electrical characteristics of the fabricated devices has been systematically investigated as the function of temperature by using current–voltage (I–V) measurements in the temperature range 299–339 K. The diode parameters like ideality factor, zero bias barrier height and parasitic series resistance have been found to be strongly temperature dependant. The zero bias barrier height increases while ideality factor and series resistance decreases with increasing temperature.

From Process to Modules: End-to-End Modeling of CSS-Deposited CdTe Solar Cells

In this paper, we develop an end-to-end modeling framework to explore how various multiscale phenomena in solar cells translate from materials to module level. Specifically, the model captures the physics related to 1) the pressure-dependent grain growth of polycrystalline thin films (nanometers to micrometers), 2) averaging of the effects of grain-size distribution at the centimeter scale, and 3) effects of parasitic series and shunt resistance distributions on the efficiency of thin-film solar cell modules (centimeter to meter scale). As an idealized illustrative example, we consider a number of puzzling features that are associated with close space sublimated CdTe solar cells. The model explains both the increase in the grain size with deposition pressure, as well as the saturation of cell efficiency beyond a critical grain size. The analysis shows that grain geometry and grain-size distribution are unimportant for average grain sizes larger than 1 μm. The model attributes the significant efficiency loss at the module level to the series resistance and the operating point inhomogeneity caused by parasitic shunts. Overall, the model identifies opportunities for significant improvement at all length scales of thin-film solar cell technologies.

Backgating effect in GaAs FETs with a channel—semi-insulating substrate boundary

This study focuses on modeling the effects of deep hole traps, mainly the effect of the substrate (backgating effect) in a GaAs transistor MESFT. This effect is explained by the existence, at the interface, of a space charge zone. Any modulation in this area leads to response levels trapping the holes therein to the operating temperature. We subsequently developed a model treating the channel substrate interface as an N—P junction, allowing us to deduce the time dependence of the component parameters of the total resistance Rds, the pinch-off voltage VP, channel resistance, fully open Rco and the parasitic series resistance RS to bind the effect trap holes H1 and H0. When compared with the experimental results, the values of the RDS (tS) model for both traps show that there is an agreement between theory and experiment; it has inferred parameter traps, namely the density and the time constant of the trap. This means that a space charge region exists at the channel—substrate interface and that the properties can be approximated to an N—P junction.