Parasitic Charge Research Articles

Effects of localized gate stack parasitic charge on current-voltage characteristics of double-gate MOSFETs with high-permittivity dielectrics and Ge-channel

In this paper we investigate the effects of localized gate stack parasitic charges on the current-voltage characteristics of double-gate (DG) MOSFET with metal/high-permittivity/Ge-channel using two-dimensional (2-D) numerical simulation. For this purpose a simulation code is developed, solving the Poisson equation on the entire device coupled self-consistently with the drift-diffusion transport equation. We show that the charges trapped at grain boundaries in the high-permittivity (high-κ) layer induce 2-D potential fluctuations in the structure, not only in the high-κ layer, but also in the underlying oxide and semiconductor regions. These potential fluctuations are shown to significantly degrade the subthreshold behavior of the drain current. The off-state drain current and the subthreshold slope increase with respect to the case where no charge is present in the gate stack. The influence of the location of the charged grain boundaries in the stack on the subthreshold parameters is also investigated using the 2-D numerical simulation code.

Five years follow-up of schoolchildren infected with schistosomiasis in Niger: evidence of the benefit of a regular praziquantel administration on the reinfection

Background The WHO’s objective regarding schistosomiasis control is to maintain a low burden by maintaining lower parasitic charges in endemic regions. The schistosomiasis and helminthiasis control program was launched in 2004 in Niger. Although yearly praziquantel treatment does not clear entirely schistosomiasis worms in people, it allows reducing parasitic loads and thus avoids serious renal complications. A study was carried out to estimate the annual prevalence of Schistosoma haematobium infection and its related morbidity among schoolchildren living in 5 endemic villages between 2004 and 2009.

Vibration-Based Monitoring and Diagnosis of Dielectric Charging in RF-MEMS Switches

Dielectric charging due to metal-dielectric contact is one of the major modes of failure in capacitive radio frequency microelectromechanical systems (MEMS) switches, and it leads to actuation voltage fluctuations and, eventually, to device failure. Failure prognostics for such devices require novel methods to monitor the extent and location of trapped parasitic charges on or in the dielectric layer. Motivated by the success of resonant electrostatic force microscopy for mapping local trapped charges, we present in this paper a technique that monitors the resonance frequencies of multiple eigenmodes of the bridge conductor of the switch as a means to detect parasitic charges and nonuniformities in electric fields in the switch that could arise from nonuniform parasitic charge distribution. Both theory and experiments are presented to demonstrate the technique. Moreover, its potential advantages and limitations as a new diagnostic tool for MEMS health monitoring are discussed.

Simulation of AlGaN/GaN high-electron-mobility transistor gauge factor based on two-dimensional electron gas density and electron mobility

The gauge factor of AlGaN/GaN high-electron-mobility transistor was determined theoretically, considering the effect of stress on the two-dimensional electron gas (2DEG) sheet carrier density and electron mobility. Differences in the spontaneous and piezoelectric polarization between the AlGaN and GaN layers, with and without external mechanical stress, were investigated to calculate the stress-altered 2DEG density. Strain was incorporated into a sp3d5–sp3 empirical tight-binding model to obtain the change in electron effective masses under biaxial and uniaxial stress. The simulated longitudinal gauge factor (−7.9±5.2) is consistent with experimental results (−2.4±0.5) obtained from measurements eliminating parasitic charge trapping effects through continuous subbandgap optical excitation.

Observation and mechanism explanation of the parasitic charge pumping current

A parasitic charge pumping current ( I PCP ) is observed and extracted properly. While charge pumping current after correction ( I COCP ) contributes to threshold voltage shift, this transient I PCP does not contribute and should be extracted from CP current ( I CP ). This I PCP is shown to be unable to be extracted by conventional low–high multi-frequency CP method (LHMF). It could only be extracted effectively enough by a high–high multi-frequency charge pumping (CP) method (HHMF). In HHMF, a high frequency is employed to measure I PCP ; while in LHMF, a low frequency is used to measure the current out of I COCP . Without eliminating I PCP , large noise tail in LHMF method distorts the shape of I COCP curve and even masks maximum I COCP current ( I CPmax ). This is because I PCP is due to transient charge-trapping and -detrapping. Therefore, I PCP is frequency dependent and its value can be obtained sufficiently only when frequency is no lower than 1 MHz. Regarding both the value of I CPmax and the shaping of I COCP curve, HHMF is more recommended for CMOS devices with SiON and high- κ dielectrics with high transient trap density.

Charge Carriers Injection/Extraction at the Metal-Polymer Interface and Its Influence in the Capacitive Microelectromechanical Systems-Switches Actuation Voltage

Opposite results concerning the sign of the parasitic charge accumulated at the metal dielectric contact in RF microelectromechanical systems (MEMS) capacitive switches are found in the literature. The mechanism concerning charge injection/extraction at the metal-dielectric contact and its influence on the pull-in voltage needs to be further clarified. A model-switch, for which only one dimension is in the microns range, is used to study the behaviour of a capacitive RF MEMS switch. The aim is to analyze how the electric charge is injected/extracted into or from the dielectric material under the applied field and to obtain realistic data to understand how this parasitic charge influences the pull-in voltage Vpi and the pull-off voltage Vpo. A triangle voltage is employed to measure Vpi and Vpo, by measuring the isothermal charging/discharging currents. Our results demonstrate that Vpi is strongly dependent on the injected/extracted charge on the free surface of the dielectric. The charge injected/extracted at the bottom side of the dielectric has no influence on the actuation voltage. The charge injected/extracted on the free surface of the dielectric determines an increase of the modulus of Vpi and, eventually, the switch can fail to actuate. An estimation of the charge stored into the material was obtained (i) by measuring the charging current and the discharging current and (ii) from the value of the Vpi. The parasitic charge necessary to keep the bridge stick to the insulator is 5.3 x 10(-4) C m(-2) for our experimental conditions. The modification of the Vpi determined by the stored charge in the dielectric is analyzed. An increase of the relative dielectric permittivity by a factor of 2 produces a decrease of the actuation voltage of 10%. A variation of 30% in the elastic constant determines a variation of about 20% in the Vpi. A voltage threshold for charge injection/extraction was not observed.

Host-parasite relationships between Porichthys porosissimus (Pisces) and cestode larvae of the Scolex group

Abstract Larvae of tetraphyllidean cestodes have been recorded in several species of marine teleosts. However, little is known on parasite-host interactions. In view of this, the present study aims at i) determining the localization sites of a larval type, belonging to the Scolex group, in the digestive tract mucose; ii) describing the anatomo-pathological features of the larval lesions produced; and iii) evaluating the potential effect of parasite intensity on the body condition of the host. Our findings reveal that parasitic charges were more intense in the second portion of the digestive tract. In the area of contact between the parasite and the epithelium a compressive atrophy of the cells was observed with a marked lowering and disappearance of the epithelial layer. The condition factor of the samples analyzed was significantly affected by infection intensity, thus revealing an adverse effect on the growth and physical condition of the host.

Charge shielding in the In-situ Storage Image Sensor for a vertex detector at the ILC

The Linear Collider Flavour Identification (LCFI) collaboration has successfully developed the first prototype of a novel particle detector, the In-situ Storage Image Sensor (ISIS). This device ideally suits the challenging requirements for the vertex detector at the future International Linear Collider (ILC), combining the charge storing capabilities of the Charge-Coupled Devices (CCD) with readout commonly used in CMOS imagers. The ISIS avoids the need for high-speed readout and offers low power operation combined with low noise, high immunity to electromagnetic interference and increased radiation hardness compared to typical CCDs. The ISIS is one of the most promising detector technologies for vertexing at the ILC. In this paper we describe the measurements on the charge-shielding properties of the p-well, which is used to protect the storage register from parasitic charge collection and is at the core of device's operation. We show that the p-well can suppress the parasitic charge collection by almost two orders of magnitude, satisfying the requirements for the application.

Effects of dielectric charging on MEMS-based grating light modulator

Silicon dioxide and silicon nitride coatings are preferably used as dielectric layers for short-circuit protection in capacitive silicon MEMS based Grating Light Modulator (GLM). However, their tendency to electrostatic charging can diminish the device reliability. The influence of dielectric charges on GLM was discussed. Gas discharges and charges in the air gap of silicon cantilever GLM have been modeled and observed, resulting in surface charge accumulation on the electrode passivation of the devices. The impact of parasitic surface charges on the deflection versus voltage characteristics of bulk micromachined silicon cantilever GLM is investigated and measurements of the charge decay are shown in experimental results. Experimental results agree with the theoretical calculation well, which illustrates the influence of charging and discharging processing. One method is proposed to reduce the influence of dielectric charges.

Contact etch stop a-SixNy:H layer: A key factor for single polysilicon flash memory data retention

The silicon nitride (a-SixNy:H) contact etch stop layer strongly affects data retention performances in single polysilicon nonvolatile memories by acting on the initial charge loss phenomenon. Its improvement has required an analysis of influent plasma enhanced chemical vapor deposition process parameters through a design of experiment approach. The a-SixNy:H physico-electrical analysis points out that silicon rich compositions especially of its interfacial layer must be avoided to reduce a-SixNy:H charge amount and as a result to improve the data retention. Indeed, the a-SixNy:H being near the floating gate, its charges modulation could act as a parasitic memory screening charges stored in the floating gate by capacitive effects.

Comparing Therapeutic Efficacy between Ivermectin, Selamectin, and Moxidectin in Canaries during Natural Infection with Dermanyssus gallinae

The aim of this study was to compare the efficacy of three spot-on drugs on canaries during Dermanyssus gallinae natural infections and during the breeding season. Three groups of canary couples (seven couples each) were included: group A was treated with ivermectin, B with selamectin, and C with moxidectin. All the drugs were administered topically infrascapularly. The parasitic charge was estimated before the treatment (t(0)) and after 8 (t(1)), 16 (t(2)), 24 (t(3)), and 32 (t(4)) days following the initial treatment. No significant differences were detected among the three tested drugs for the five repeats for each of the four mite stages (egg, larva, nymphs, and fed and unfed adults). With regard to the decrease in the mean numbers of red mites, ivermectin and selamectin exerted their efficacy at t(2), contrary to moxidectin at t(3).

Analysis and Design of Voltage Regulator With Adaptive FET Modulation Scheme and Improved Efficiency

This paper presents a load adaptive voltage regulator that achieves high efficiency extended to light and heavy load regions. The presented method is named as adaptive field effect transistor modulation (AFM) since multiple field effect transistors (FETs) with different characteristics (different sizes) are applied in parallel such that the number of driven FETs and their respective gate driving voltage are adaptive to load current. The capability of adaptive modulation of FETs' parasitic charges and resistances along with adaptive gate driving voltage allows the optimization of equivalent FET characteristics over a wide load range. Moreover, the AFM operation under load dynamic conditions is studied and a scheme is proposed. The AFM operates at a fixed switching frequency for almost the entire load range. Therefore, it has no impact on the operation and the dynamic performance of a conventional buck VR, and it is easy to implement. In this paper, the concept, design and theoretical analysis of the AFM are discussed and verified experimentally. Even though the simulation and experimental works design example given in this paper is for lower power and low voltage converter with discrete components for demonstration purposes, the AFM may have better improvement in higher power and/or higher voltage applications and in integrated voltage regulators.

Anomalous behavior of AlGaN∕GaN heterostructure field-effect transistors at cryogenic temperatures: From current collapse to current enhancement with cooling

While current collapse affects AlGaN∕GaN heterojunction field-effect transistors (HFETs) around room temperature, it gradually gives place to a current enhancement with cooling—below 200K, electrically stressed devices do show higher currents than in their prestressed state. This behavior can be explained by increased levels of channel impact ionization at lower temperatures. The positive hole charge generated by impact ionization compensates (and eventually dominates) the parasitic negative charge that is responsible for current collapse at higher temperatures (i.e., the “virtual gate charge”). Cooling of AlGaN∕GaN HFETs may potentially alleviate some of the nonidealities that have so far plagued this technology.

Materials Challenges in Automotive Embedded Non-Volatile Memories

AbstractSilicon-based nonvolatile memory modules are widely used in microcontrollers, where they are embedded into a monolithic system on a chip (SoC) which also includes high speed logic transistors, cache SRAM, and peripheral circuits for communicating with the external world. The physical principle most widely exploited for nonvolatile code and data storage is charge storage in floating gates. Recently, charge storage in nitride traps and nanocrystals also has been explored.The most demanding use profiles with respect to temperatures, data retention times, and low failure rates are encountered in automotive engine control applications, where junction temperatures up to 150°C are common, for 1000's of hours. Starting with the 130nm technology node, embedded Flash technology has been integrated with copper interconnects, and at the 90nm node, low dielectric constant interlevel dielectrics are also employed to increase circuit performance. To achieve automotive reliability, the materials surrounding the silicon floating gate, nanocrystal, or nitride charge storage area must be evaluated for parasitic charge storage, write/erase stress-induced leakage current, and other parameters important for reliability. Any movement of parasitic charge, potentially over a long period of time, can reduce the sensing window of the Flash EEPROM bitcell.

Effects of dielectric charging on fundamental forces and reliability in capacitive microelectromechanical systems radio frequency switch contacts

Microelectromechanical systems (MEMS) radio frequency switches hold great promise in a myriad of commercial, aerospace, and military applications. In particular, capacitive-type switches with metal-to-dielectric contacts (typically gold-on-silicon nitride) are suitable for high frequency (⩾10GHz) applications. However, the devices are known to be unstable in their performance due to parasitic dielectric charging. Although several authors have previously reported the switch failure along with shifts in pull-down and release voltages due to charging, there is some disagreement and lack of understanding among the various reports. This study uses a switch simulator capable of measuring microscale electrostatic and adhesive forces to investigate charging and its effect on reliability and fundamental forces acting within MEMS capacitive switches. An important advantage of the switch simulator is that it can be actuated with or without a bias voltage. Electrostatic force and dielectric charging increased as surfaces were worn smooth by cycling. This is because the surface smoothening decreases separation and increases the electric field strength inside the dielectric. A simple analytical model was developed using electromagnetic theory for the electrostatic force in terms of bias voltage and the areal density of parasitic charge. Using the model and experimental data, it was determined that “charging” (net charge is zero) with the same polarity as the bias voltage resulted in reduced electrostatic force (under bias voltage) when a worn-in switch was actuated repeatedly at constant bias voltage ⩾40V. Small electrostatic force under bias voltage can explain failure in the “up” position (failure to actuate and self-release). Reversing the polarity of the bias voltage between actuations prevented charge buildup and doubled the electrostatic force, which can help explain the effectiveness of bipolar actuation. The charging time constant for parasitic dielectric charge is about 30s under typical MEMS contact conditions. In the specific case of parasitic charge being present, high electrostatic and adhesion forces were measured at zero volts bias. This can explain failure in the down position under zero bias voltage due to self-actuation or adhesion.

Converter circuit design, semiconductor device selection and analysis of parasitics for micropower electrostatic Generators

For various medical monitoring and sensing applications it is desirable to power the electronics by scavenging energy from any locally available source. An electrostatic motion-driven generator for low-frequency (human body) motion has been developed by the authors using microelectromechanical system technology. The prototype generates pulses of 250V on a 10-pF capacitor. This paper examines the design of a circuit and semiconductor devices to convert this energy to a low voltage. Because of the very small charge involved, the effects of leakage and parasitic stored charge are important. Converters for this application using silicon-on-insulator metal-oxide-semiconductor field-effect transistors and insulated gate bipolar transistors are compared using physics-based finite-element simulation. The overall effectiveness of the generation process is shown to be composed of several terms which are functions of system parameters such as generator flight time, semiconductor device area, and circuit inductance. It is shown that device area is a compromise between leakage current, charge storage, and on-state voltage. It can, for a given generator and inductance, be optimized to provide the maximum energy yield. Parasitic series inductance is shown to be of little importance to the circuit efficiency; however, parasitic capacitance has a significant influence.

Performance Degradation Induced by Fringing Field-Induced Barrier Lowering and Parasitic Charge in Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with High-κ Dielectrics

The electrical behavior of a decananometer double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) with high-permittivity (high-κ) and stacked-gate dielectrics has been investigated using two-dimensional (2D) quantum numerical simulation. We show that in spite of a quasi-ideal control of the channel by the gates in the double-gate structure, the device performances can be significantly degraded when using high-κ dielectrics due to two important electrostatic limitations of high-κ materials: i) the fringing field-induced barrier lowering effect (FIBL) and ii) the presence of discrete fixed charges in the gate stack. The FIBL compromises the performance of short-channel devices when simultaneously increasing the dielectric constant and its physical thickness, whereas the charges trapped in the high-κ layer induce 2D potential fluctuations in the structure and degrades the subthreshold behaviour of the drain current.

Adhesive behavior of DNA molecules on silicon wafers treated by argon and oxygen plasma

The adhesion of Deoxyribose Nuclei Acid (DNA) on an electrode surface such as silicon is a key issue in the sensitivity of DNA chips, in order to maximize the DNA concentration on the electrodes of DNA chips and increase the detected signal, the chip should have good adhesion of DNA to its electrodes. In our study, several pieces of silicon wafer were treated by argon and oxygen plasma, respectively. We analyzed the DNA content on the different silicon surfaces using the X-ray photoelectron spectroscopy (XPS). The results indicate that the content of DNA molecules adhered on the silicon surface treated with an oxygen plasma is higher than that on the surface treated with an Ar plasma. This can be interpreted in terms of the interaction of parasitic charges and van der Waals forces on silicon oxide surfaces.

Compensation of temperature effects on the pull-in voltage of microstructures

The pull-in voltage of a suspended microstructure has been investigated for use as on-chip voltage reference in a compatible MEMS-IC process. Pull-in is detected using capacitive displacement measurement. The stability is affected by an initial parasitic charge build-up and a temperature sensitivity of −149 μV/K. A burn-in procedure is required to minimize the first effect. The temperature coefficient is compensated for by applying additional temperature dependent electrostatic energy to the microstructure. Devices fabricated in an epi-poly process and designed for a nominal pull-in voltage at 5 V have a measured value at 4.7424 V. Drift becomes negligible after 120 h of operation. The temperature reproducibility is within the resolution of the readout at 100 μV over a temperature range between 20 and 60 °C.

Simple estimation of the effect of hot-carrier degradation on scaled nMOSFETs

The influence of parasitic charge at the Si–SiO2 interface on the characteristics of n-channel metal oxide semiconductor field effect transistors (nMOSFETs) scaled down to a feature size of 25 nm is studied. The results are that the impact of parasitic charge on threshold voltage and drain current degradation significantly decreases. Additionally, as the hot-electron injection current densities are lowered for scaled-down nMOS transistors, less charge build-up occurs. This opens the perspective to make use of alternative gate dielectrics even if they have a higher interface trap density. These materials offer the advantage of greater dielectric constants than silicon oxide, so that a physically thicker dielectric will limit the gate tunnelling current.