Parasitic Capacitance Model Research Articles

A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays.

Design Criteria for Transformers in High Voltage Output, High Frequency Power Converter Applications

SummaryWhen a dc high voltage needs to be obtained from low voltage inputs (main voltage), the necessary power converter needs a high value for its transformation ratio; consequently, a large number of turns is often necessary for secondary windings and some parasitics appear (large leakage inductance and large capacitance). Thus, it is usual to design a resonant converter to include both inductance and capacitance in the power topology. However, as the parasitics are used to obtain the resonance, their value (and their spreads) are critical. The present paper proposes several criteria in order to establish an adequate method for constructing the transformer, and a new topology for transformers and a model for parasitic capacitances are also presented taking into account high voltage and high frequency problems and limitations of materials.

Experimental and theoretical investigation of parameter evolution of ultra-short gate standard and pseudomorphic HEMTs

We present a coordinated experimental and theoretical investigation of the parameter evolution of ultra-short gate HEMTs down to 0.1μm gate-length, and of the physical and electrical limitations to performance improvements. The study encompasses a broad range of well qualified situations allowing comparisons with previous investigations[1–4]. The main features are,- the exploitation of two reliable technological processes namely planar-doped double-recessed AlGaAs/GaAs HEMT (S-HEMT) and planar-doped pseudomorphic AlGaAs/GaInAs/GaAs HEMT with T-shaped and rectangular gate (PM-HEMT), represented in Fig.1 and 2), - coherent evolutions of full electrical parameter extractions from dc and 0.1– 40GHz HF coplanar probe on-chip measurements, including capacitances versus gate length down to 0.1μm, - physical modeling based on a quasibidimensional hydrodynamic approach (Q-2D), allowing systematic parametrisation of HEMTs, completed with electromagnetic finite element 2-D modeling of electrostatic parasitic capacitances,- physical modeling based on Monte Carlo simulations (MC) for the investigation of short 1 g transistors. For the gate width 1g≤0,1μm this analysis shows that the optimization of S- and PM-HEMT depends on three parameters: - a weak influence of V ds on the diffusion under the gate, — a low parasitic electrostatic capacitance, - a high carrier velocity.

A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer

Conventionally, ultrahigh-speed 2:1 multiplexers and 1:2 demultiplexers have been demonstrated with HBTs, MESFETs, and Si BJTs. Multiplexers and demultiplexers with a high number of bits are desirable to simplify a system. Si bipolar circuits and package design technology for a 5-Gb/s 8:1 multiplexer and a 4.2 Gb/s 1:8 demultiplexer are described. These multigigabit LSIs have been achieved mainly by switching current optimization within the limit of keeping a maximum unity unilateral gain frequency (f/sub max/), by careful circuit and layout design considering accurate parasitic capacitance modeling, and by using a high-speed Si bipolar technology. These LSIs are housed in a newly developed 56-pin six-layer ceramic package with chip resistors for ECL termination and chip capacitors for good RF grounding. >

A `missing neighbor model' for capacitive loading in VLSI interconnect channels

The authors describe and justify a model of parasitic interconnect capacitance that enables the compilation of succinct numerical capacitance-per-unit-length tables for use in the parasitic extraction routines of layout and simulation software. The course of an interconnect line is divided into successive segments at planes where any parallel neighboring line begins or terminates. Parasitic capacitance is the sum of segment capacitances, each of which is found from a table entry appropriate to the local configuration of missing neighbor lines. Thus, CAD software with access to these tables and a routing database can accurately compute parasitic interconnection capacitance.