Effect Of Parasitic Capacitance Research Articles

Modeling and experimental validation of parasitic capacitance effects on emulated bioimpedance measurements with high‐impedance residuals

SummaryParasitic capacitances and high‐residual impedances (typical of electrode/tissue interfaces) have significant effects on estimated electrical impedances of tissues under study. This leads to deviations (especially at high frequency) from the true tissue impedance. This work outlines the circuit theory describing estimation errors occurring when one and two parasitic capacitances are present in tetrapolar electrode configurations typical for bioimpedance measurements. The described circuit theory was validated using both simulations and measurements of a fabricated printed circuit board that implemented the tetra‐polar model. Using the presented model, correction procedures using (a) measurements of the source and sink excitation currents and (b) averaging measurements of forward and reverse electrode configurations have been validated in simulation showing reductions in the estimation errors at frequencies greater than 1 MHz.

Effect of fringing field capacitances in RF and small signal parameters of surrounding gate MOSFET

A small signal equivalent model of surrounding gate MOSFET incorporating fringing capacitances has been proposed and detailed in this paper. Detail modeling of the fringing (outer and inner both) capacitances of surrounding gate MOSFETs are considered here. Considering fringing capacitance, also the gate to drain/source and effective gate capacitances have been calculated for the proposed model. Low frequency Y-parameters (admittance parameters) of the SRG MOSFET are derived from the proposed model and expressed using real/imaginary function for different biasing condition. RF/analog performance parameters like Gate input capacitance (CGG), transport time delay (τ), input resistance (Rin), trans-conductance (gm), channel conductance (gds) etc have been evaluated. Figure of Merit (FOM) parameters like cut off frequency, gmRo, maximum oscillation frequency etc of the proposed model has been evaluated to study the effect of parasitic capacitances on the RF performances in depth. Extensive simulations using Silvaco ATLAS have been done to verify the proposed models. Matching of the simulated results with the model data demonstrate the correctness of the proposed model. It has been observed that the fringing capacitances can deteriorate the ac characteristics of the nano dimensional surrounding/cylindrical gate MOSFET.

Superior performance area changing capacitive MEMS accelerometer employing additional lateral springs for low frequency applications

This paper introduces an effective and efficient microstructure of a differential area changing capacitive accelerometer to ensure low cross-axis sensitivity, high linearity and low noise figure for low frequency applications like Structural Health Monitoring and seismic sensing. The major design concern in an area dependent capacitance structure is that even small magnitude of cross axis displacement can drastically affect the sensitivity and linearity. The authors first focused their effort to obtain the guidelines for the best performance in the conventional structure of area changing capacitive sensors. The results clearly demonstrated that the existing structures used conventionally cannot meet the stringent requirements for low frequency applications. Subsequently, the various studies on the new structure proposed in this work were presented and the results are compared with latest reports for benchmarking. It has been estimated that the new structure can give cross-axis displacement as low as 0.5%, linearity of 2.53% and noise figure of 4.89 ng/ $$\sqrt {\text{Hz}}$$ , the best achieved in so for. These studies clearly demonstrate that the ill effects of parasitic capacitance on voltage sensitivity and linearity can be suppressed by the new design. These results further show that the area changing capacitive structure employing additional lateral springs is a promising candidate for low frequency applications like seismography. The other major advantage of this structure is that the fabrication process flow need not be changed in the production line.

Electromagnetic Characteristics of Shape Memory Spring

Electric impedance is widely used in imaging and detection techniques. The applications range from non-destructive testing, structural health monitoring, and geophysical imaging to medical imaging. The frequency of the signal used for the measurement ranges from less than 1 Hz to about 1 GHz. This paper addresses the measurement and evaluation of the phase dependent electrical resistance, inductance, capacitance, and impedance of a shape memory alloy (SMA) spring (BMX 150, Toki Corporation). The material characteristics can be obtained by means of their electromechanical impedance. Experimental procedures are implemented and the electrical characteristics are obtained for a wide range of frequency. The electrical resistance, inductance, impedances of the austenite and martensite phase are determined, also the quality factor of the Bio Metal coil to be (9.465 – 9.95) Ω and (10.358 – 10.8) Ω, (0.458 – 0.38) μH and (0.458 – 0.36) μH and, (9.47 – 10.24) Ω and (10.36 – 11.11) Ω respectively for the frequency range of 100 kHz - 1MHz. The quality factor of the Bio Metal ranges between 0.03 and 0.2 during heating and, 0.028 and 0.022 during the cooling phase. The experimental results herein show that an equivalent circuit of the SMA spring is a series resistor-inductor circuit with a parasitic capacitance effect. The electromagnetic behaviour of SMA is determined using a finite element tool.

Analytical Dead-Band Compensation for ZCS Modulation Applied to Hybrid Si-SiC Dual Active Bridge

This paper proposes a triangular modulation with zero current switching (ZCS) for a hybrid Si-SiC isolated bidirectional DC-DC converter (IBDC). Three of the four legs in the IBDC operate at ZCS and use Si IGBTs, while the fourth operates at zero voltage switching (ZVS) and uses SiC MOSFET. In that case, the turn-off switching losses are concentrated regardless of the direction of the power. The main contribution of this paper resides in the proposed dead-band compensation mechanism. This dead-band compensation is crucial when addressing ZCS modulation and improves the overall efficiency of the full operating range. As a co-benefit, the proposed mix of semiconductor technologies can result in an effective cost reduction compared with a full SiC IBDC. The paper contains a detailed explanation of the implemented modulation applied to an IBDC. The paper contributes to deploy a theoretical implementation where the effect of parasitic capacitance on semiconductors during the dead-band is analytically considered. The presented method results are validated on a laboratory set-up using a 20 kW - 40 kHz hybrid Si-SiC IBDC.

A 0.3V 10b 3MS/s SAR ADC With Comparator Calibration and Kickback Noise Reduction for Biomedical Applications.

This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were +0.83/-0.54 and +0.84/-0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 μW at a figure of merit of 4.065 fJ/conv.-step.

Analysis and Improvement of Capacitance Effects in 360–800 Hz Variable On-Time Controlled CRM Boost PFC Converters

In critical conduction mode (CRM) boost power factor correction (PFC) converters, the input filter capacitor (IFC) is used to limit the propagation of switching noise into the ac line and the inherently existing parasitic capacitance of power semiconductor devices resonates with the boost inductor to achieve soft switching, which is voltage dependent and nonlinear. However, IFC leads to the crossover distortion of the rectified input voltage and thus the zero-crossing distortion of input current, which is ignored at the utility line frequency (50-60 Hz) since the effect of IFC is relatively small in this case. However, for wide variable frequency (360-800 Hz) power system, the effect of IFC becomes severe and unnegligible, which causes the deterioration of input current total harmonics distortion (THD). Besides, the nonlinearity of the parasitic capacitance is ignored and an equivalent constant linear capacitance is used in existing variable on-time (VOT) controls, which will cause the inaccuracy of VOT control, and thus, exacerbates the input current distortion. In order to improve the input current THD at high line frequency, this article proposes the IFC compensation method to minimize the effect of IFC and a variable parameter control is also achieved to suppress the effect of nonlinear parasitic capacitance. The experimental results of an 115-Vac-input 160-W/270-Vdc-output CRM boost PFC prototype are presented to verify the effectiveness and advantages of the proposed VOT methods. With the proposed methods, the input current THD is only 2.04% at 360 Hz input with full load and 3.14% at 800 Hz input with full load.

Analysis of the Effect of Switch Parasitic Resistance and Capacitance on N-Path Filters Using State Space Representation

This brief suggests a new method for analyzing the effects of nonideal properties of CMOS switches on N-path filters by expanding the linear periodically time-variant (LPTV) method to state space equations. The proposed technique provides an algorithm for analytical derivation of the harmonic transfer functions (HTF) and the noise figure (NF) of the N-path filter across all frequencies and harmonics. The analysis results show that for constant switch resistance and shunt capacitance product, a trade-off exists between out of band rejection, NF and insertion loss.

Analysis and Modeling of Conducted EMI from an AC–DC Power Supply in LED TV up to 1 MHz

Critical conduction mode (CRM) boost power factor correction (PFC) converter is widely used in ac–dc power supplies to achieve high power factor. The switching frequency varies in a half-line cycle. In this article, both the differential-mode (DM) and common-mode (CM) electromagnetic interference (EMI) noises below 1 MHz from the ac–dc power supply in a LED TV are analyzed and modeled. The power supply consists of two parts: CRM boost PFC converter and LLC resonant converter. The conducted EMI noise and noise source voltages are measured in the time domain and then converted to the frequency domain via short-time fast Fourier transform (STFFT). Through the joint time-frequency analysis using STFFT, the drain-to-source voltage of the power MOSFET in the PFC converter is identified as the dominant noise source of both CM and DM EMI noises below 1 MHz from the power supply. The EMI current path is different during different periods of a cycle of the line voltage. During most time of a cycle, two diodes of the bridge rectifier are forward biased, and the bridge rectifier can be treated as short circuit. The current paths of DM and CM EMI noises are explained and modeled by a linear equivalent circuit model. Three parasitic capacitances need to be considered to model the CM EMI noise in this device under test. From the circuit model, transfer functions relating DM and CM EMI spectra to noise source voltage spectrum are obtained. The conducted EMI spectra are predicted by multiplying the spectrum of noise source voltage by the transfer functions. The prediction matches with measurement. The effects of parasitic capacitances on CM EMI noise are analyzed by simulation and then validated by measurement. The analysis results can help with EMI design to reduce the CM EMI.

A New Design Approach to Mitigating the Effect of Parasitics in Capacitive Wireless Power Transfer Systems for Electric Vehicle Charging

This paper introduces a new design approach to mitigate the effect of parasitic capacitances and achieve high performance in large air-gap capacitive wireless power transfer (WPT) systems for electric vehicle (EV) charging. In a capacitive WPT system for EVs, the vehicle chassis and roadway introduce multiple parasitic capacitances that can overwhelm the coupling capacitance and severely degrade power transfer and efficiency. The proposed approach addresses this challenge by employing split-inductor matching networks, which allow the complex network of parasitic capacitances to be simplified into an equivalent four-capacitance model. The shunt capacitances of this model are directly utilized as the matching network capacitors, hence, absorbing the parasitic capacitances and eliminating the need for discrete high-voltage capacitors. A systematic procedure is developed to accurately measure the equivalent capacitances of the model, enabling the system’s performance to be reliably predicted. The proposed approach is used to design two 6.78–MHz 12-cm air-gap prototype capacitive WPT systems with capacitor-free matching networks. The first system transfers up to 590 W using 150-cm2 square coupling plates and achieves an efficiency of 88.4%. The second prototype system transfers up to 1217 W using 118-cm2 circular coupling plates, achieving a power transfer density of 51.6 kW/m2. The measured output power profiles of the two systems match well with their predicted counterparts, validating the proposed design approach.

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier

A temperature-stabilized 12-bit single-channel successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC) running at 1 GS/s with Nyquist signal to noise and distortion ratio (SNDR) above 60 dB is presented. The ADC uses a three-stage (4 b-4 b-6 b) SAR-assisted pipeline hybrid architecture to achieve an attractive energy efficiency along with an extended sampling rate. A high-linearity open-loop Gm-R-based residue amplifier (RA) with both complete-settled and dynamic features improves the residue amplification efficiency and speed, while reducing the gain variation over a temperature drift. The inter-stage gain variation over the temperature is compensated through complementary temperature coefficients (TCs) from the inner devices of the RA. Furthermore, a cascade amplification topology in the backend RA alleviates the effect of the input parasitic capacitance to its front-end capacitor DAC (CDAC), thus leading to a small CDAC size to accelerate amplification and conversion. The prototype ADC was fabricated in a 28-nm CMOS process and consumes 7.6 mW from a 1-V power supply at 1 GS/s. The measured inter-stage gain variation is less than 2.3% with a temperature range from 0 °C to 80 °C. The SNDR and SFDR are 60 and 74.6 dB with a Nyquist input, respectively, achieving a Walden figure-of-merit (FoM) of 9.3 fJ/conversion-step and a Schreier FoM of 168.2 dB.

High Gain Single Ended Primary Inductor Converter With Ripple Free Input Current for Solar Powered Water Pumping System Utilizing Cost-Effective Maximum Power Point Tracking Technique

This paper presents a new configuration of high gain (HG) single ended primary inductor converter (SEPIC) with a ripple-free input current to maximize the efficiency of the PV panel for standalone water pumping system (WPS). The ripple eliminating circuit combined with the HG SEPIC converter to achieve reduced ripples in photovoltaic (PV) current is independent to the duty cycle control and hence, it can be easily integrated to the main power circuit of configuration. This circuit does not need any active switches, control, or drive circuit for its execution. The ripple eliminating circuit yields a complete removal of the electrolytic capacitor connected across the PV array and significantly reduces the inductance of the HG SEPIC converter. It also improves the response and power density of the dc–dc converter. The large gain of dc–dc converter enables the use of low-voltage PV panel and minimizes the partial shading and parasitic capacitance effects on PV array source. Due to the substantial compatibility between natural characteristics of switched reluctance motor (SRM) drive and WPS, a four-phase SRM drive is utilized in the proposed scheme. In addition, a single current sensor based maximum power point tracking technique is utilized in the proposed system, which helps to reduce the cost and improve the accuracy of the overall system. Analytical, simulated, and experimental results of the developed system are presented to demonstrate the performance of the system.

A VCII-Based Stray Insensitive Analog Interface for Differential Capacitance Sensors

In this paper, a novel approach to implement a stray insensitive CMOS interface for differential capacitive sensors is presented. The proposed circuit employs, for the first time, second-generation voltage conveyors (VCIIs) and produces an output voltage proportional to differential capacitor changes. Using VCIIs as active devices inherently allows the circuit to process the signal in the current domain, and hence, to benefit from its intrinsic advantages, such as high speed and simple implementation, while still being able to natively interface with voltage mode signal processing stages at necessity. The insensitiveness to the effects of parasitic capacitances is achieved through a simple feedback loop. In addition, the proposed circuit shows a very simple and switch-free structure (which can be used for both linear and hyperbolic sensors), improving its accuracy. The readout circuit was designed in a standard 0.35 μm CMOS technology under a supply voltage of ±1.65 V. Before the integrated circuit fabrication, to produce tangible proof of the effectiveness of the proposed architecture, a discrete version of the circuit was also prototyped using AD844 and LF411 to implement a discrete VCII. The achieved measurement results are in good agreement with theory and simulations, showing a constant sensitivity up to 412 mV/pF, a maximum linearity error of 1.9%FS, and acknowledging a good behavior with low baseline capacitive sensors (10 pF in the proposed measurements). A final table is also given to summarize the key specs of the proposed work comparing them to the available literature.

Transmission Lines and Metamaterials Based on Quantum Hall Plasmonics

The characteristic impedance of a microwave transmission line is typically constrained to a value $Z_0$ = 50 $ \Omega$, in-part because of the low impedance of free space and the limited range of permittivity and permeability realizable with conventional materials. Here we suggest the possibility of constructing high-impedance transmission lines by exploiting the plasmonic response of edge states associated with the quantum Hall effect in gated devices. We analyze various implementations of quantum Hall transmission lines based on distributed networks and lumped-element circuits, including a detailed account of parasitic capacitance and Coulomb drag effects, which can modify device performance. We additionally conceive of a meta-material structure comprising arrays of quantum Hall droplets and analyze its unusual properties. The realization of such structures holds promise for efficiently wiring-up quantum circuits on chip, as well as engineering strong coupling between semiconductor qubits and microwave photons.

An Analytical Differential Resistance Pulse System Relying on a Time Shift Signal Analysis-Applications in Coulter Counting.

Improving the sensitivity and ultimately the range of particle sizes that can be detected with a single pore extends the versatility of the Coulter counting technique. Here, to enable a pore to have greater sensitivity, we have developed and tested a novel differential resistive pulse sensing (DiS) system for sizing particles. To do this, the response was generated through a time shift approach utilizing a "self-servoing regime" to enable the final signal to operate with a zero background in the absence of particle translocation. The detection and characterization of a series of polystyrene particles, forced to translocate through a cylindrical glass microchannel (GMC) by a suitable static pressure difference using this approach, is demonstrated. An analytical response, which scales with the size of the particles employed, was verified. Parasitic capacitive effects are discussed; however, translocations on the millisecond time scale can be detected with high sensitivity and accuracy using the approach described.

An Energy-Based Analysis for High Voltage Low Power Flyback Converter Feeding Capacitive Load

Generally, battery-fed capacitive loads are charged to high voltages in series of switching cycles with smaller fragments of energy delivered to the load in every cycle to ensure an efficient charging process. In high voltage low power (HVLP) flyback charging circuit, significant portion of input energy drawn from the source in a cycle is utilized by the effective parasitic capacitance of the HV transformer and semiconductor devices and circulated back to the source at the end of the cycle. This reduces the energy delivered to the load per cycle and hence the net energy delivered in the charging process. In this paper, an energy-based analysis and simplified energy-based model for HVLP charging circuits is derived. An energy-based approach is appropriate to describe and define the HVLP converter behavior in terms of load energy component and circulating energy component. The derived energy-based model is extended to obtain analytical closed-form expressions governing the essential parameters of the charging circuit. The proposed energy-based model and analytical formulation of essential parameters are experimentally validated on a 0–2.5 kV programmable high voltage charging circuit prototype fed from 12 V input battery source.

Dual-Band Millimeter-Wave Quadrature LO Generation With a Common-Centroid Floorplan

This brief presents a dual-band millimeter-wave (mm-Wave) quadrature signal generation network comprising an RC-CR polyphase filter (PPF) and two quarter-wave coupled-line couplers. A common-centroid layout is proposed to improve the phase and amplitude matching of quadrature signals. The effects of interconnects and parasitic capacitances on PPFs are investigated, and design guidelines are provided to achieve low insertion loss and broad bandwidth. A proof-of-concept image-reject mixer is implemented in a 0.13 $ \mu \text{m}$ SiGe BiCMOS technology, which achieves a mean image-rejection ratio of 34 dB over a wide frequency range of 36 – 100 GHz. To the best of authors’ knowledge, this design achieves the widest bandwidth of any mm-Wave mixer having a mean image rejection ratio above 30 dB, and accomplishes this without calibration or tuning.

Energy Feedback Control of Light-Load Voltage Regulation for LLC Resonant Converter

An LLC resonant converter would have light-load voltage regulation problems due to the effect of parasitic capacitances in a high-frequency range. In this paper, an energy feedback control method is proposed to improve the light-load regulation capacity by using synchronous rectifiers (SRs). The SR bridges are controlled ahead of the primary inverter bridges to deliver the energy from load to source, reducing the output voltage independent of the load. Then the desired voltage can be achieved even in no-load conditions by regulating the operation time of the energy feedback mode. The gain, voltage ripple, and efficiency performances of the proposed control method are discussed based on the precise analysis and an accurate model of the converter. Moreover, the light-load operations of the LLC resonant converter are analyzed deriving the critical load condition. Finally, the proposed control method is verified by the experiments of a 12 V/8 A LLC resonant converter prototype.

Small-Signal Compact Circuit Modeling of Group IV Material-Based Heterojunction Phototransistors for Optoelectronic Receivers

This paper presents an optoelectronics-based compact equivalent circuit model of an n-Ge/p-Ge1– x Sn x /n-Ge1– x Sn x heterojunction phototransistor (HPT). This paper includes the static electrical and optical characteristics of the device, Gummel characteristics, effect of temperature, and overall noise analysis of HPT based on various parametric variations. We then investigate the effect of parasitic capacitance on the noise performance of the HPT. The estimated results show that the signal-to-noise ratio (SNR) is strongly dependent on not only the operating frequency but also the operating temperature and applied base-bias voltage. Estimated performance shows that SNR of HPT >90 dB up to 100 GHz and >80 dB up to 50 °C can be achieved, which ensured the operation of the device as high-speed and low-noise detector.

A High Gain Low Noise Figure Double Balanced Down Conversion Mixer for Band 1 of WiMedia System

Objective: To propose an improved double balanced down conversion mixer for band 1 of WiMedia system at RF frequency of 3.432 GHz and IF frequency of 264 MHz. Method/Analysis: The proposed mixer is based on the Gilbert cell architecture. It uses switch bias technique to improve the noise figure and resistive current injection technique to improve the conversion gain and linearity. A resonating inductor is used to cancel out the effects of parasitic capacitances. Moreover, T type impedance matching, LC impedance matching and output buffer are used at RF trans conductance stage, LO switching stage and load stage respectively for matching purpose. Mixer is simulated in 0.18 μm CMOS technology using keysight Advanced Design System (ADS) software. Findings: Simulation results show that mixer achieves maximum conversion gain of 8.057 dB, third order Input Intercept Point (IIP3) of -10.88 dBm, Double Sideband (DSB) noise figure of 3.515 dB and S11 of -22.926 dB at 1.8 V dc supply voltage. Novelty/Improvement: A high gain, low noise figure double balanced down conversion mixer with low value of input reflection coefficient and suitable linearity is proposed for band 1 of Wimedia system. Keywords: Current Injection Technique, Double Balanced, Down Conversion Mixer, L and T Type Matching Networks, Switch Bias Technique, Wimedia System