Operational Amplifier Parameters Research Articles

Operation of colpitts oscillator based on wide band gap operational amplifiers

ABSTRACT The present work is concerned with studying and analysing the operation of the Colpitts oscillator based on operational amplifier with different technologies. During the study, two different operational amplifier types, TLV2374IEN and TL084ACN were used. First, the different operational amplifier parameters including; input offset voltage, input bias current, offset current, voltage gain, input impedance, and output impedance, as well slew rate were measured. Second, the effect of oscillator circuit inductance values (L) on the circuit parameters including; quality factor, signal frequency, inductor impedance, oscillator output impedance, amplification factor and output voltage gain were investigated, whenever the two proposed operational amplifiers were used. The quality factor, signal frequency, inductor impedance, and oscillator output impedance were observed to be affected by L variation. While, both the attenuation and amplification factors were shown to be affected by L till the value of around 860 µH, after this value a semi-saturation for the parameter values wasobserved.

Thermal Reliability of a CMOS-OTA Versus Improving Its Parameters

In this study, the relationship between thermal sensitivity of a CMOS operational transconductance amplifier (OTA) and other parameters of the OTA such as gain bandwidth (GBW), DC gain, settling time, slew rate (SR), etc. is analyzed and discussed. For the first time, it is shown that although some techniques such as adaptive biasing and DC gain enhancement can be utilized to improve the transient response of a CMOS-OTA by increasing the input stage’s gain, DC gain, GBW and SR, yet this causes a significant increase in the thermal sensitivities of the CMOS-OTA, so that, the reliability of accurate operation of the CMOS-OTA under variation in ambient temperature effectively decreases. This paper concludes that a reconciliation of the thermal reliability with improvement of the CMOS-OTA parameters should be considered when the CMOS-OTA is designed and implemented. This point is the contribution of this work that has not been considered and addressed in any other works. Simulated results performed using 0.18[Formula: see text][Formula: see text]m SILTERRA CMOS process technology and real experimental results are presented that explicitly verify the theoretical results.

Improving the Signal to Noise Ratio of QTF Preamplifiers Dedicated for QEPAS Applications

The signal-to-noise ratio (SNR) is a major factor that limits the detection sensitivity of quartz-enhanced photoacoustic spectroscopy (QEPAS) sensors. The higher the electrical signal level compared to the noise amplitude is the lower the concentration of gases that can be detected. For this reason the preamplifier circuits used in QEPAS should be optimized for low-frequency narrow-band applications. Moreover, special care should be taken when choosing a particular operational amplifier in either a transimpedance or voltage (differential) configuration. It turns out that depending on the preamp topology different operational amplifier parameters should be carefully considered when a high SNR of the whole QEPAS system is required. In this article we analyzed the influence of the crucial parameters of low-noise operational preamplifiers used in QEPAS applications and show the resulting limitations of transimpedance and voltage configurations.

Negative Group Delay Theory of a Four-Port RC-Network Feedback Operational Amplifier

An innovative negative group delay (NGD) theory based on a unity direct chain feedback (UDCF) circuit topology is developed in this paper. This NGD circuit is an active cell constituted by an operational amplifier in feedback with a four-port RC-network. This NGD circuit theory is developed based on the S-parameter model analytically established from the equivalent impedance matrix. The UDCF group delay frequency response is expressed as a function of the feedback RC-cell and the operational amplifier parameters. The NGD analysis of the developed UDCF cell is introduced. According to theoretical analysis, under a certain condition, the UDCF topology is susceptible to behave as a low-pass NGD function. The UDCF cell NGD characteristics are defined theoretically. The theoretical prediction is verified numerically and experimentally in both the frequency- and time-domain by designing and fabricating an active PCB prototype. The simulations and experimentations show that the UDCF circuit exhibits an NGD of approximately -38 ns with NGD cut-off frequency of about 5.5 MHz. More importantly, it is demonstrated in the time-domain that the low-pass NGD effect enables the UDCF cell to generate advanced output with sinc waveform input voltages.

OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

ABSTRACTIn this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen–Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.

Analysis and Calibration of Sources of Electronic Error in PSD Sensor Response.

In order to obtain very precise measurements of the position of agents located at a considerable distance using a sensor system based on position sensitive detectors (PSD), it is necessary to analyze and mitigate the factors that generate substantial errors in the system’s response. These sources of error can be divided into electronic and geometric factors. The former stem from the nature and construction of the PSD as well as the performance, tolerances and electronic response of the system, while the latter are related to the sensor’s optical system. Here, we focus solely on the electrical effects, since the study, analysis and correction of these are a prerequisite for subsequently addressing geometric errors. A simple calibration method is proposed, which considers PSD response, component tolerances, temperature variations, signal frequency used, signal to noise ratio (SNR), suboptimal operational amplifier parameters, and analog to digital converter (ADC) quantitation SNRQ, etc. Following an analysis of these effects and calibration of the sensor, it was possible to correct the errors, thus rendering the effects negligible, as reported in the results section.

Modeling operation amplifier based on VHDL-AMS for TID effect

A model of the operational amplifier based on VHDL-AMS is proposed. According to needs of simulating the total ionizing dose (TID) radiation effect, parameters of operational amplifier are taken into account when the performance is specified. The operational amplifier model used for the TID radiation effect simulation is completed after verifying each modeled parameter. And a parameter for describing the external environment is introduced to make the model combined with TID. Finally, an example is used to illustrate the TID effect on the operational amplifier of MC14573, proving the validity of the model.

OPERATIONALAMPLIFIER ANALYSIS WHEN MIGRATING FROM 0.18 ΜM TO 65 ΜM CMOS TECHNOLOGY / OPERACINIŲ STIPRINTUVŲ PARAMETRŲ TYRIMAS 0,18 ΜM IR 65 NM KMOP TECHNOLOGIJOSE

The article offers the analysis of operational amplifier parameter changes, when circuits are scaled from 0.18 μm to 65 nm CMOS technology. Two two-stage operational amplifiers were designed for this purpose: first uses n-MOS input differential pair; second uses cascaded active loads structure and p-MOS type input differential pair. The operational amplifiers were designed in 0.18 μm CMOS technology and scaled to 65 nm CMOS. Other scaling methods were also analysed when redesigning circuits from one IC technology to another. Results of the original and scaled operational amplifier parameters are presented and analysed. Article in Lithuanian. Santrauka Nagrinėjami pagrindiniai operacinių stiprintuvų parametrai, jų pokytis pereinant iš 0,18 μm į 65 nm KMOP technologiją. Tyrimui atlikti suprojektuoti ir panaudoti du skirtingi dviejų pakopų operaciniai stiprintuvai: pirmas su n-MOP tipo įėjimo diferencine pakopa; antras – su p-MOP tipo įėjimo diferencine pakopa ir kaskodine aktyviųjų apkrovų sandara. Operaciniai stiprintuvai projektuoti naudojant 0,18 μm KMOP procesą kaip pagrindinę technologiją ir vėliau, nustatant mastelį, perkelti į 65 nm KMOP technologiją. Kitos perkėlimo procedūros naudojamos pereinant iš vienos integrinės technologijos į kitą. Sumodeliuoti ir palyginti suprojektuotų operacinių stiprintuvų parametrai.

Simulink Behavioral Modeling of a 10- bit Pipelined ADC

The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters (ADCs). All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages). Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.

A design method in CMOS operational amplifier optimization based on adaptive genetic algorithm

A new method based on adaptive GA(genetic algorithm) for optimizing the parameters of CMOS operational amplifier is presented in this paper. The synthesis of the Op-amp (operational amplifier) can ...

Influence of noise parameters of integral operational amplifiers and voltage comparators and their nonlinear distortions on presentation accuracy of signals being processed

Influence of noisy signals of integral operational amplifiers (IOAs) and voltage comparators (IVCs) on accurate parameters of low-noise preamplifiers, discriminators, and analog-to-digital converters (ADCs) is considered. Methods aimed at increasing the noise factor of the above devices are discussed. Influence of nonlinear distortions resulting from signal representation is taken into consideration

Performance Analysis of a Robust Photometer Circuit

In this brief, the performance analysis of a photometer circuit based on a robust two degrees-of-freedom controller is presented. Here, the closed-loop transfer function of the complex feedback system is shown as a function of the operational amplifier parameters. Also, the stability region of the robust photometer circuit is calculated, and the performance of this circuit is compared against the performance of a photometer circuit based on a basic current-to-voltage converter connection. Both the simulation and experimental results are satisfactory and show the importance of applying robust control techniques to the design of photometer circuits.

Behavioral modeling of switched-capacitor sigma-delta modulators

This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed set of blocks takes into account most of the SC /spl Sigma//spl Delta/ modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC /spl Sigma//spl Delta/ modulator.

Relaxation of operational amplifier parameters after pulsed electron beam irradiation

The relaxation of operational amplifier parameters (offset voltage and differential gain) with time after pulsed electron beam irradiation has been studied as a function of total dose and amplifier type. Four types of operational amplifiers were studied viz., general purpose bipolar input (μA 741), super-beta transistor input (LM 308), JFET input (LF 356) and MOSFET input (CA 3140) from different vendors. The experiments were carried out mainly using 500 ns pulses from a Linear Accelerator. The study, the first of its kind, shows that while the electrical transient at the output of the operational amplifier recovers in a few milliseconds, relaxation of parameters can take several to several tens of seconds. This relaxation is attributed to the build up and/or anneal of damage in the oxide or at the interface of the internal transistor structures. The change and relaxation of parameters depend on operational amplifier type and total dose, and can have significant effects in certain application domains as illustrated by the response of a thermocouple amplifier after pulsed irradiation.

Wien-Bridge Oscillators with Composite Operational Amplifiers: Comparison und Stability Considerations

The paper presents a theoretical and experimental comparison of Wien-Bridge Oscillators realized by some composite operational amplifiers. Emphasis is given to stability limitations, due to the composite operational amplifier parameters, and to the frequency response of the individual operational amplifiers used to construct the composite operational amplifiers. Experimental results are presented

New Measurement Methods of Dominant-Pole-Type Operational Amplifier Parameters

New simple and easy methods measuring the parameters of operational amplifiers (OA's) are presented with newly constructed testing circuits and setups. Firstly, it is shown that the transition frequency and dominant-pole frequency are derived from a relaxation or harmonic oscillator in which the OA under test is used as an element of the circuit. Secondly, it is shown that other parameters such as the open-loop gain, the input and output resistance, the input offset voltage, the input bias current, and the input offset current are obtained easily from the new circuits.

Standardization of methods of measuring the electrical parameters of operational amplifiers

Standardization of methods of measuring the electrical parameters of operational amplifiers

Recent advances in monolithic operational amplifier design

The state of the art in monolithic operational amplifier design is surveyed. A set of large- and small-signal performance parameters are defined and discussed. Relationships between the important operational amplifier parameters of slew rate, offset voltage, and unity gain bandwidth are demonstrated. The dependence of settling time upon the fine structure of the open-loop frequency response is discussed, and the recent technological and circuit design approaches to the minimization of settling time are reviewed.