Parallel Execution Of Tasks Research Articles

Parallel Execution of Structural Mechanic Tasks with Use of Small Supercomputers

The paper deals with selected approaches to speed-up numerical solutions of particular civil engineering mechanics problems. A short overview of common approaches is given and one particular approach is discussed in detail. The use of the selected approach is demonstrated on numerical examples.

Hardware Implementation on FPGA for Task-Level Parallel Dataflow Execution Engine

Heterogeneous multicore platform has been widely used in various areas to achieve both power efficiency and high performance. However, it poses significant challenges to researchers to uncover more coarse-grained task level parallelization. In order to support automatic task parallel execution, this paper proposes a FPGA implementation of a hardware out-of-order scheduler on heterogeneous multicore platform. The scheduler is capable of exploring potential inter-task dependency, leading to a significant acceleration of dependence-aware applications. With the help of renaming scheme, the task dependencies are detected automatically during execution, and then task-level Write-After-Write (WAW) and Write-After-Read (WAR) dependencies can be eliminated dynamically. We extended the instruction level renaming techniques to perform task-level out-of-order execution, and implemented a prototype on a state-of-art Xilinx Virtex-5 FPGA device. Given the reconfigurable characteristic of FPGA, our scheduler supports changing accelerators at runtime to improve the flexibility. Experimental results demonstrate that our scheduler is efficient at both performance and resources usage.

Parallel image computation in clusters with task-distributor.

Distributed systems, especially clusters, can be used to execute ray tracing tasks in parallel for speeding up the image computation. Because ray tracing is a computational expensive and memory consuming task, ray tracing can also be used to benchmark clusters. This paper introduces task-distributor, a free software solution for the parallel execution of ray tracing tasks in distributed systems. The ray tracing solution used for this work is the Persistence Of Vision Raytracer (POV-Ray). Task-distributor does not require any modification of the POV-Ray source code or the installation of an additional message passing library like the Message Passing Interface or Parallel Virtual Machine to allow parallel image computation, in contrast to various other projects. By analyzing the runtime of the sequential and parallel program parts of task-distributor, it becomes clear how the problem size and available hardware resources influence the scaling of the parallel application.

Refactor Business Process Models with Maximized Parallelism

With the broad use of business process management technology, there are more and more business process models. Since the ability of different modelers is different, the quality of these models varies. A question arises here is that, can we refactor these models to improve the quality as practised in software engineering? Business process modeling can be regarded as declarative programming, and business process models can be used to drive the process aware information systems, which are generally developed with model driven architecture, so business process models are crucial for the efficiency of process aware information systems. In this paper, we propose a novel approach on how to systematically refactor business process models with parallel structures for sequence structures for the first time. More specifically, we analyze the real causal relations between business tasks based on data operation dependency analysis, and refactor business process models with process mining technology. After comprehensive model refactoring, parallel execution of business tasks can be maximized, so the efficiency of business processing can be improved, that is, the quality of business process models can be improved. Analysis and experiments show that our approach is effective and efficient.

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems

This paper proposes an N-modular redundancy (NMR) technique with low energy-overhead for hard real-time multi-core systems. NMR is well-suited for multi-core platforms as they provide multiple processing units and low-overhead communication for voting. However, it can impose considerable energy overhead and hence its energy overhead must be controlled, which is the primary consideration of this paper. For this purpose the system operation can be divided into two phases: indispensable phase and on-demand phase. In the indispensable phase only half-plus-one copies for each task are executed. When no fault occurs during this phase, the results must be identical and hence the remaining copies are not required. Otherwise, the remaining copies must be executed in the on-demand phase to perform a complete majority voting. In this paper, for such a two-phase NMR, an energy-management technique is developed where two new concepts have been considered: i ) Block-partitioned scheduling that enables parallel task execution during on-demand phase, thereby leaving more slack for energy saving, ii ) Pseudo-dynamic slack, that results when a task has no faulty execution during the indispensable phase and hence the time which is reserved for its copies in the on-demand phase is reclaimed for energy saving. The energy-management technique has an off-line part that manages static and pseudo-dynamic slacks at design time and an online part that mainly manages dynamic slacks at run-time. Experimental results show that the proposed NMR technique provides up to 29 percent energy saving and is 6 orders of magnitude higher reliable as compared to a recent previous work.

Water-Level scheduling for parallel tasks in compute-intensive application components

The development of complex simulations with high computational demands often requires an efficient parallel execution of a large number of numerical simulation tasks. Exploiting heterogeneous compute resources for the execution of parallel tasks can be achieved by integrating dedicated scheduling methods into the complex simulation code. In this article, the efforts for developing an application from the area of engineering optimization consisting of various individual components are described. Several scheduling methods for distributing parallel simulation tasks among heterogeneous compute nodes are presented. Performance results and comparisons are shown for two novel scheduling methods and several existing scheduling algorithms for parallel tasks. A heterogeneous compute cluster is used to demonstrate the scheduling and execution of benchmark tasks and FEM simulation tasks.

Auto-tuning for large-scale image processing by dynamic analysis method on multicore platforms

This paper describes a general-purpose method of improving execution performance of the in-memory data, particularly in the case of large-scale image processing on different multicore platforms. To process large-scale arrays, the method of tiling is widely used to achieve high performance. However, frequently accessing the memory system by multithreads is bound to cause system bottleneck. Our optimisation strategies are automatic thread scheduling and data/task partitioning. Those methods that attempt to take advantage of spatial and temporal locality can reduce memory traffic remarkably. According to the hardware configurations, a scheduler automatically partitions the images into tiled blocks of pre-determined size. Then it fuses all the operations for the same blocks to reduce the rate of cache miss. The parallel task execution is more effective than other traditional parallel libraries, such as openMP. Moreover, the optimisation on space-filling curves that optimises the locality of neighbouring tiled blocks can also contribute to the fast memory access.

Large-Scale Schema-Free Data Deduplication Approach with Adaptive Sliding Window Using MapReduce

Data deduplication is the task of identifying all groups of objects within one or several data sets, respectively. However, this task will become difficult in the context of big data. To address this limitation, we propose a new schema-free data deduplication approach in parallel in the aspect of breeding data deduplication related to food safety. Although MapReduce framework enables efficient parallel execution of data-intensive tasks, it cannot find duplicates in adjacent block. Furthermore, current deduplication approaches with MapReduce are restricted to fixed sliding window. Therefore, we investigate possible solutions to improve current deduplication approaches with MapReduce, to make sliding window size adaptive using adaptive multiple duplicate count strategy with alterable window step, and find duplicates by overlapping boundary objects in adjacent blocks. Moreover, we propose a multi-pass Partition-Sort-Map-Reduce approach with adaptive sliding window to speed up the deduplication process. Finally, our experimental evaluation based on the breeding data on large datasets shows the high effectiveness and efficiency of the proposed approaches.

Balancing task- and data-level parallelism to improve performance and energy consumption of matrix computations on the Intel Xeon Phi

The emergence of new manycore architectures, such as the Intel Xeon Phi, poses new challenges in how to adapt existing libraries and applications to this type of systems. In particular, the exploitation of manycore accelerators requires a holistic solution that simultaneously addresses time-to-response, energy efficiency and ease of programming. In this paper, we adapt the SuperMatrix runtime task scheduler for dense linear algebra algorithms to the many-threaded Intel Xeon Phi, with special emphasis on the performance and energy profile of the solution. From the performance perspective, we optimize the balance between task- and data-parallelism, reporting notable results compared with Intel MKL. From the energy-aware point of view, we propose a methodology that relies on core-level event counters and aggregated power consumption samples to obtain a task-level accounting for the energy. In addition, we introduce a blocking mechanism to reduce power and energy consumption during the idle periods inherent to task parallel executions.

Pteros 2.0: Evolution of the fast parallel molecular analysis library for C++ and python.

Pteros is the high-performance open-source library for molecular modeling and analysis of molecular dynamics trajectories. Starting from version 2.0 Pteros is available for C++ and Python programming languages with very similar interfaces. This makes it suitable for writing complex reusable programs in C++ and simple interactive scripts in Python alike. New version improves the facilities for asynchronous trajectory reading and parallel execution of analysis tasks by introducing analysis plugins which could be written in either C++ or Python in completely uniform way. The high level of abstraction provided by analysis plugins greatly simplifies prototyping and implementation of complex analysis algorithms. Pteros is available for free under Artistic License from http://sourceforge.net/projects/pteros/.

Petri Net Reliability Models for CORBA Wireless Networks

Since the dynamic behavior of wireless networks inherits different communication patterns for the execution processes of the desired parallel tasks and the occurrence processes of handoff operations, the available reliability metrics are not applicable to study and analyze such networks. Therefore, in this paper, we propose a novel Petri net modeling methodology for accurately calculating the reliability of wireless networks that incorporate theses aspects, such as wireless CORBA network. The proposed reliability methodology is developed based on using the End-to-End Expected Instantaneous Reliability (EIR) measure. The EIR has the capability to measure the reliability of wireless networks that incorporate the handoff processes as well as the service processes. In the proposed technique, we firstly build Generalized Stochastic Petri Net (GSPN) performance model for describing the different communication pattern that can occur among the various network resources under the execution of parallel tasks. Secondly, we build GSPN performance model for describing the handoff communication processes among the various network resources. Finally, we build generic reliability model consists of the following parts: the first part describes the execution of the desired parallel tasks, the second part illustrates the mobility characteristic introduced by handoff processes, and the third part describes the dynamic behavior of failure processes of network resources. The developed model has the capability to accurately describe the occurrence of many handoff processes in CORBA network. We study and analyze the various reliability results as well as the performance results obtained from the developed GSPN models under the effect of communication distance among the CORBA network resources.

A Parallel Sparse Direct Solver via Hierarchical DAG Scheduling

We present a parallel sparse direct solver for multicore architectures based on Directed Acyclic Graph (DAG) scheduling. Recently, DAG scheduling has become popular in advanced Dense Linear Algebra libraries due to its efficient asynchronous parallel execution of tasks. However, its application to sparse matrix problems is more challenging as it has to deal with an enormous number of highly irregular tasks. This typically results in substantial scheduling overhead both in time and space, which causes overall parallel performance to be suboptimal. We describe a parallel solver based on two-level task parallelism: tasks are first generated from a parallel tree traversal on the assembly tree; next, those tasks are further refined by using algorithms - by - blocks to gain fine-grained parallelism. The resulting fine-grained tasks are asynchronously executed after their dependencies are analyzed. Our approach is distinct from others in that we adopt two-level task scheduling to mirror the two-level parallelism. As a result, we reduce scheduling overhead, and increase efficiency and flexibility. The proposed parallel sparse direct solver is evaluated for the particular problems arising from the hp -Finite Element Method where conventional sparse direct solvers do not scale well.

Dynamic Visual Servoing With Chaos Control for Redundant Robots

This paper presents a new dynamic visual control system for redundant robots with chaos compensation. In order to implement the visual servoing system, a new architecture is proposed that improves the system maintainability and traceability. Furthermore, high performance is obtained as a result of parallel execution of the different tasks that compose the architecture. The control component of the architecture implements a new visual servoing technique for resolving the redundancy at the acceleration level in order to guarantee the correct motion of both end-effector and joints. The controller generates the required torques for the tracking of image trajectories. However, in order to guarantee the applicability of this technique, a repetitive path tracked by the robot-end must produce a periodic joint motion. A chaos controller is integrated in the visual servoing system and the correct performance is observed in low and high velocities. Furthermore, a method to adjust the chaos controller is proposed and validated using a real three-link robot.

Designing and Implementing Control Flow Graph for Magic 4th Generation Language

A good compiler which implements many optimizations during its compilation phases must be able to perform several static analysis techniques such as control flow or data flow analysis. Besides compilers, these techniques are common for static analyzers as well to retrieve information from source code, for example for code auditing, quality assurance or testing purposes. Implementing control flow analysis requires handling many special structures of the target language. In our paper we present our experiences in implementing control flow graph (CFG) construction for a special 4th generation language called Magic. While we were designing and implementing the CFG for this language, we identified dierences compared to 3rd generation languages mostly because of the unique programming technique of Magic (e.g. data access, parallel task execution, events). Our work was motivated by our industrial partner who needed precise static analysis tools (e.g. for quality assurance or testing purposes) for this language. We believe that our experiences for Magic, as a representative of 4GLs, might be generalized for other languages too.

A markov prediction model for data-driven semi-structured business processes

In semi-structured case-oriented business processes, the sequence of process steps is determined by case workers based on available document content associated with a case. Transitions between process execution steps are therefore case specific and depend on independent judgment of case workers. In this paper, we propose an instance-specific probabilistic process model (PPM) whose transition probabilities are customized to the semi-structured business process instance it represents. An instance-specific PPM serves as a powerful representation to predict the likelihood of different outcomes. We also show that certain instance-specific PPMs can be transformed into a Markov chain under some non-restrictive assumptions. For instance-specific PPMs that contain parallel execution of tasks, we provide an algorithm to map them to an extended space Markov chain. This way existing Markov techniques can be leveraged to make predictions about the likelihood of executing future tasks. Predictions provided by our technique could generate early alerts for case workers about the likelihood of important or undesired outcomes in an executing case instance. We have implemented and validated our approach on a simulated automobile insurance claims handling semi-structured business process. Results indicate that an instance-specific PPM provides more accurate predictions than other methods such as conditional probability. We also show that as more document data become available, the prediction accuracy of an instance-specific PPM increases.

Decentralized task scheduling for a fixed priority multicore embedded RTOS

Parallel task execution on multiple cores is increasingly the norm in high-performance embedded systems. Many multicore real-time operating systems (RTOSes) support a fixed task priority policy, and many applications that execute on such platforms require high performance while adhering to the fixed task priority policy. This paper proposes a decentralized task scheduling problem for a fixed-priority multicore RTOS running a mix of sequential and parallel tasks. Since aggressive decentralized task scheduling can result in task priority inversions, a high-performance priority-preserving solution to the proposed problem is challenging. To address this problem, 32 possible candidate solutions are considered and simulation studies are used to evaluate them. From extensive evaluations based on carefully prepared performance metrics, it is found that policies based on number of tasks, waiting time and priority (NTWP) for sequential tasks and small subtask first, then minimum number of tasks (MIN---MNT) for parallel tasks significantly outperform other possible candidates.

Heterothread

In this paper, we introduce middleware architecture to support hybrid thread level parallelism on heterogeneous multicore architectures, called Heterothread. Heterothread constructs a hierarchical level model for user programming and parallel task execution dataflow. Heterothread can provide unified programming interfaces which allow applications remain the same when the physical hardware (CPU, GPU, DSP and FPGA) is reconfigured or migrated. Consequently it can meet the real-time demands more efficiently than most state-of-the-art operating systems. A prototype has been built on FPGA to demonstrate Heterothread can achieve significant speedups against Linux kernels.

MP-Tomasulo

This article presents MP-Tomasulo, a dependency-aware automatic parallel task execution engine for sequential programs. Applying the instruction-level Tomasulo algorithm to MPSoC environments, MP-Tomasulo detects and eliminates Write-After-Write (WAW) and Write-After-Read (WAR) inter-task dependencies in the dataflow execution, therefore to operate out-of-order task execution on heterogeneous units. We implemented the prototype system within a single FPGA. Experimental results on EEMBC applications demonstrate that MP-Tomasulo can execute the tasks out-of-order to achieve as high as 93.6% to 97.6% of ideal peak speedup. A comparative study against a state-of-the-art dataflow execution scheme is illustrated with a classic JPEG application. The promising results show MP-Tomasulo enables programmers to uncover more task-level parallelism on heterogeneous systems, as well as to ease the burden of programmers.

MethylPCA: a toolkit to control for confounders in methylome-wide association studies

BackgroundIn methylome-wide association studies (MWAS) there are many possible differences between cases and controls (e.g. related to life style, diet, and medication use) that may affect the methylome and produce false positive findings. An effective approach to control for these confounders is to first capture the major sources of variation in the methylation data and then regress out these components in the association analyses. This approach is, however, computationally very challenging due to the extremely large number of methylation sites in the human genome.ResultWe introduce MethylPCA that is specifically designed to control for potential confounders in studies where the number of methylation sites is extremely large. MethylPCA offers a complete and flexible data analysis including 1) an adaptive method that performs data reduction prior to PCA by empirically combining methylation data of neighboring sites, 2) an efficient algorithm that performs a principal component analysis (PCA) on the ultra high-dimensional data matrix, and 3) association tests. To accomplish this MethylPCA allows for parallel execution of tasks, uses C++ for CPU and I/O intensive calculations, and stores intermediate results to avoid computing the same statistics multiple times or keeping results in memory. Through simulations and an analysis of a real whole methylome MBD-seq study of 1,500 subjects we show that MethylPCA effectively controls for potential confounders.ConclusionsMethylPCA provides users a convenient tool to perform MWAS. The software effectively handles the challenge in memory and speed to perform tasks that would be impossible to accomplish using existing software when millions of sites are interrogated with the sample sizes required for MWAS.

Work-stealing with configurable scheduling strategies

Work-stealing systems are typically oblivious to the nature of the tasks they are scheduling. They do not know or take into account how long a task will take to execute or how many subtasks it will spawn. Moreover, task execution order is typically determined by an underlying task storage data structure, and cannot be changed. There are thus possibilities for optimizing task parallel executions by providing information on specific tasks and their preferred execution order to the scheduling system. We investigate generalizations of work-stealing and introduce a framework enabling applications to dynamically provide hints on the nature of specific tasks using scheduling strategies . Strategies can be used to independently control both local task execution and steal order. Strategies allow optimizations on specific tasks, in contrast to more conventional scheduling policies that are typically global in scope. Strategies are composable and allow different, specific scheduling choices for different parts of an application simultaneously. We have implemented a work-stealing system based on our strategy framework. A series of benchmarks demonstrates beneficial effects that can be achieved with scheduling strategies.