Parallel Sorting Research Articles

A 4K-Capable FPGA Implementation of Single Image Haze Removal Using Hazy Particle Maps

This paper presents a fast and compact hardware implementation using an efficient haze removal algorithm. The algorithm employs a modified hybrid median filter to estimate the hazy particle map, which is subsequently subtracted from the hazy image to recover the haze-free image. Adaptive tone remapping is also used to improve the narrow dynamic range due to haze removal. The computation error of the proposed hardware architecture is minimized compared with the floating-point algorithm. To ensure real-time hardware operation, the proposed architecture utilizes the modified hybrid median filter using the well-known Batcher’s parallel sort. Hardware verification confirmed that high-resolution video standards were processed in real time for haze removal.

Performance Evaluation of Parallel Bubble Sort Algorithm on Supercomputer IMAN1

Parallel sorting algorithms order a set of elements USING MULTIPLE processors in order to enhance the performance of sequential sorting algorithms. In general, the performance of sorting algorithms are EVALUATED IN term of algorithm growth rate according to the input size. In this paper, the running time, parallel speedup and parallel efficiency OF PARALLEL bubble sort is evaluated and measured. Message Passing Interface (MPI) IS USED for implementing the parallel version of bubble sort and IMAN1 supercomputer is used to conduct the results. The evaluation results show that parallel bubble sort has better running time as the number of processors increases. On other hand, regarding parallel efficiency, parallel bubble sort algorithm is more efficient to be applied OVER SMALL number of processors.

Engineering Algorithms for Scalability through Continuous Validation of Performance Expectations

Many libraries in the HPC field use sophisticated algorithms with clear theoretical scalability expectations. However, hardware constraints or programming bugs may sometimes render these expectations inaccurate or even plainly wrong. While algorithm and performance engineers have already been advocating the systematic combination of analytical performance models with practical measurements for a very long time, we go one step further and show how this comparison can become part of automated testing procedures. The most important applications of our method include initial validation, regression testing, and benchmarking to compare implementation and platform alternatives. Advancing the concept of performance assertions, we verify asymptotic scaling trends rather than precise analytical expressions, relieving the developer from the burden of having to specify and maintain very fine-grained and potentially non-portable expectations. In this way, scalability validation can be continuously applied throughout the whole development cycle with very little effort. Using MPI and parallel sorting algorithms as examples, we show how our method can help uncover non-obvious limitations of both libraries and underlying platforms.

Performance Evaluation of Parallel Bubble Sort Algorithm on Supercomputer IMAN1

Parallel sorting algorithms order a set of elements USING MULTIPLE processors in order to enhance the performance of sequential sorting algorithms. In general, the performance of sorting algorithms are EVALUATED IN term of algorithm growth rate according to the input size. In this paper, the running time, parallel speedup and parallel efficiency OF PARALLEL bubble sort is evaluated and measured. Message Passing Interface (MPI) IS USED for implementing the parallel version of bubble sort and IMAN1 supercomputer is used to conduct the results. The evaluation results show that parallel bubble sort has better running time as the number of processors increases. On other hand, regarding parallel efficiency, parallel bubble sort algorithm is more efficient to be applied OVER SMALL number of processors

25‐4: Late‐News Paper: Xerographic MicroAssembly Printer for LEDs and Beyond

We are building a deterministic massively parallel sorting, assembly and transfer system for microLEDs and other applications. It uses programmable directed electrostatic assembly and transfer (stamp or roller). Small chips (10 um – 500 um), fine registration (<1um, <1°), heterogeneity, and 162 chiplet prints over an inch are demonstrated.

Total angular momentum sorting in the telecom infrared with silicon Pancharatnam-Berry transformation optics.

Parallel sorting of orbital angular momentum (OAM) and polarization has recently acquired paramount importance and interest in a wide range of fields ranging from telecommunications to high-dimensional quantum cryptography. Due to their inherently polarization-sensitive optical response, optical elements acting on the geometric phase prove to be useful for processing structured light beams with orthogonal polarization states by means of a single optical platform. In this work, we present the design, fabrication and test of a Pancharatnam-Berry optical element in silicon implementing a log-pol optical transformation at 1310 nm for the realization of an OAM sorter based on the conformal mapping between angular and linear momentum states. The metasurface is realized in the form of continuously variant subwavelength gratings, providing high-resolution in the definition of the phase pattern. A hybrid device is fabricated assembling the metasurface for the geometric-phase control with multi-level diffractive optics for the polarization-independent manipulation of the dynamic phase. The optical characterization confirms the capability to sort orbital angular momentum and circular polarization at the same time.

Optical orbital-angular-momentum-multiplexed data transmission under high scattering

Multiplexing multiple orbital angular momentum (OAM) channels enables high-capacity optical communication. However, optical scattering from ambient microparticles in the atmosphere or mode coupling in optical fibers significantly decreases the orthogonality between OAM channels for demultiplexing and eventually increases crosstalk in communication. Here, we propose a novel scattering-matrix-assisted retrieval technique (SMART) to demultiplex OAM channels from highly scattered optical fields and achieve an experimental crosstalk of –13.8 dB in the parallel sorting of 24 OAM channels after passing through a scattering medium. The SMART is implemented in a self-built data transmission system that employs a digital micromirror device to encode OAM channels and realize reference-free calibration simultaneously, thereby enabling a high tolerance to misalignment. We successfully demonstrate high-fidelity transmission of both gray and color images under scattering conditions at an error rate of <0.08%. This technique might open the door to high-performance optical communication in turbulent environments.

ОБЧИСЛЮВАЛЬНА СКЛАДНІСТЬ МЕРЕЖЕВОЇ МОДЕЛІ СОРТУВАННЯ ЛІНІЙНОГО МАСИВУ ЧИСЕЛ

In the development of advanced software and hardware for modern computing, the interest is the improvement of methods of associative processing of information such as procedures of sorting and selection. That ensures the realization of effective search for the required information in the data arrays. The need for parallel non-processing of large amounts of information entails the appropriate organization of associative memory, as well as the development and using of perspective technical devices. The sorting is important procedure in such application areas as solving economic problems, managing databases, sorting of IP addresses in computer networks, processing signals and images (for example, in nonlinear median image filtering). The analysis of known sorting methods have shown that the most effective method of parallel sorting, taking into account its hardware implementation by the sorting network, is the pairwise exchange. At the same time, the degree of parallelism of any sorting method for its hardware implementation directly depends on the number of comparison schemes that work in parallel in each view. For a pairwise exchange method, the degree of parallelism is determined by the value ]n/2[, where n is the number of input numerical values ​​or the dimension of the input linear number array. In this article methods of implementing of the sorting algorithm by the method of pairwise exchange with the link topology between elements of the number array in the form of tape and ring are analyzed. For example, the parallel sorting algorithm using the pairwise exchange method is described. The simulation at a high-level C ++ language is done. The obtained statistical and graphic results of modeling are analyzed. The analysis of graphical modeling results shows the dependence of the form O(n) between the number of sort cycles and the dimensionality n of the input array. That confirms the effectiveness of the hardware implementation of sorting by pairwise exchange on the sorting network due to the regularity of the structure and connections in the sorting process. The ability to statistically determine not only the number of sorting cycles with a given dimension of the number array, but also the corresponding number of comparisons and transposition greatly extends the possibilities of improving the known and creating new ways of synchronous sorting of elements of a linear array by hardware in the form of a sorting network.

BulkSort: System Design and Parallel Hardware Implementation Considerations

Algorithms are commonly perceived as difficult subjects. Many applications today require complex algorithms. However, the researchers look for ways to make them as simple as possible. In high time demanding fields, the process of sorting represents one of the foremost issues in the data structure for searching and optimization algorithms. In parallel processing, we divide program instructions among multiple processors by breaking problems into modules that can be executed in parallel, to reduce the execution time. In this paper, we proposed a novel parallel, re-configurable and adaptive sorting network of the BulkSort algorithm. Our architecture is based on simple and elementary operations such as comparison and binary shifting. The main strength of the proposed solution is the ability to sort in parallel without memory usage. Experimental results show that our proposed model is promising according to the required resources and its ability to perform a high-speed sorting process. In this study, we take into account the analysis result of the Simulink design to establish the required hardware resources of the proposed system.

Cell sorting actuated by a microfluidic inertial vortex.

The sorting of specific cell populations is an established tool in biological research, with new applications demanding greater cell throughput, sterility and elimination of cross-contamination. Here we report 'vortex-actuated cell sorting' (VACS), a new technique that deflects cells individually, via the generation of a transient microfluidic vortex by a thermal vapour bubble: a novel mechanism, which is able to sort cells based on fluorescently-labelled molecular markers. Using in silico simulation and experiments on beads, an immortal cell line and human peripheral blood mononuclear cells (PBMCs), we demonstrate high-purity and high-recovery sorting with input rates up to 104 cells per s and switching speeds comparable to existing techniques (>40 kHz). A tiny footprint (1 × 0.25 mm) affords miniaturization and the potential to achieve multiplexing: a crucial step in increasing processing rate. Simple construction using biocompatible materials potentially minimizes cost of fabrication and permits single-use sterile cartridges. We believe VACS potentially enables parallel sorting at throughputs relevant to cell therapy, liquid biopsy and phenotypic screening.

Parallel construction of binary tree based on sorting

Introduction. Algorithms for the parallel binary tree construction are developed. The algorithms are based on sorting and described in a constructive form. For the Nelement set, the time complexity has T(R) = O(1) and T(R) = O(log2 N) estimates, where R = (N2-N)/2 is the number of processors. The tree is built with the uniqueness property. The algorithms are invariant with respect to the input sequence type. The work objective is to develop and study ways of accelerating the process of organizing and transforming the tree-like data structures on the basis of the stable maximum parallel sorting algorithms for their application to the basic operations of information retrieval on databases.Materials and Methods. A one-to-one relation between the input element set and the binary tree built for it is established using a stable address sorting. The sorting provides maximum concurrency, and, in an operator form, establishes a one-to-one mapping of input and output indices. On this basis, methods for the mutual transformation of the binary data structures are being developed.Research Results. An efficient parallel algorithm for constructing a binary tree based on the address sorting with time complexity of T(N2) = O(log2 N) is obtained. From the well-known analogues, the algorithm differs in structure and logarithmic estimation of time complexity, which makes it possible to achieve the acceleration of O(Nα), α≥1 order analogues. As an advanced version, an algorithm modification, which provides the maximum parallel construction of the binary tree based on a stable address sorting and a priori calculation of the stored subtree root indices is suggested. The algorithm differs in structure and estimation of T(1) = O(1) time complexity. A similar estimate is achieved in a sequential version of the modified algorithm, which allows obtaining the acceleration of known analogs O(Nα), α&gt;1 order.Discussion and Conclusions. The results obtained are focused on the creation of effective methods for the dynamic database processing. The proposed methods and algorithms can form an algorithmic basis for an advanced deterministic search on the relational databases and information systems.

A Study of Integer Sorting on Multicores

Integer sorting on multicores and GPUs can be realized by a variety of approaches that include variants of distribution-based methods such as radix-sort, comparison-oriented algorithms such as deterministic regular sampling and random sampling parallel sorting, and network-based algorithms such as Batcher’s bitonic sorting algorithm. In this work we present an experimental study of integer sorting on multicore processors. We have implemented serial and parallel radix-sort for various radixes, deterministic regular oversampling, and random oversampling parallel sorting, including new variants of ours, and also some previously little explored or unexplored variants of bitonic-sort and odd-even transposition sort. The study uses multithreading and multiprocessing parallel programming libraries with the same C language code working under Open MPI, MulticoreBSP, and BSPlib. We first provide some general high-level observations on the performance of these implementations. If we can conclude anything is that accurate prediction of performance by taking into consideration architecture dependent features such as the structure and characteristics of multiple memory hierarchies is difficult and more often than not untenable. To some degree this is affected by the overhead imposed by the high-level library used in the programming effort. Another objective is to model the performance of these algorithms and their implementations under the MBSP (Multi-memory BSP) model. Despite the limitations mentioned above, we can still draw some reliable conclusions and reason about the performance of these implementations using the MBSP model, thus making MBSP useful and usable.

The multiverse nature of epithelial to mesenchymal transition.

The epithelial mesenchymal transition (EMT) program is defined as a cellular transition from an epithelial to a mesenchymal state. This process occurs to provide the cell with new phenotypic assets and new skills to perform complex processes. EMT is regulated at multilayer levels, including transcriptional control of gene expression, regulation of RNA splicing, and translational/post-translational control. Although transcriptional regulation by EMT-inducing transcription factors (EMT-TFs), including Zeb, Snail and Slug members, is generally considered the master step in this process, emerging data indicate that all these regulatory networks may have a role in the control of EMT. There is a sort of parallelism between the biological and still unrevealed EMT complexity and the cosmological hypothesis that sustains the universe may exist as a multiverse. The presence of different EMT transition states together with the occurrence of multiple layers of regulation support the idea that EMT is just one on many out there. Is the activation of a single layer of regulation sufficient to initiate the whole EMT program? Can we postulate the activation of different EMT "dimensions"? If we think about these layers as multiple separate "universes", various scenarios can be revealed.

High-Throughput Separation, Trapping, and Manipulation of Single Cells and Particles by Combined Dielectrophoresis at a Bipolar Electrode Array.

Microfluidic systems have been developed widely in scaled-down processes of laboratory techniques, but they are usually limited in achieving stand-alone functionalities. It is highly desirable to exploit an integrated microfluidic device with multiple capabilities such as cell separation, single-cell trapping, and cell manipulation. Herein, we reported a microfluidic platform integrated with actuation electrodes, for separating cells and microbeads, and bipolar electrodes, for trapping, rotating, and propelling single cells and microbeads. The separation of cells and microbeads can be first achieved by deflective dielectrophoresis (DEP) barriers. Trapping experiments with yeast cells and polystyrene (PS) microbeads suspended in aqueous solutions with different conductivities were then conducted, showing that both cells and particles can be trapped at the center of wireless electrodes by negative DEP force. Upon application of a rotating electric field, yeast cells exhibit translational movement along the electrode edges, and self-rotation is seen at an array of bipolar electrodes when electrorotational torque and traveling wave DEP force are applied on the cells. The current approach allows us to switch the propulsion and rotation direction of cells by varying the frequency of the applied electric field. Beyond the achievements of single-cell manipulation, this system permits effective control of several particles or cells simultaneously. The integration of parallel sorting and single trapping stages within a microfluidic chip enables the prospect of high-throughput cell separation, single trapping, and large-scale cell locomotion and rotation in a noninvasive and disposable format, showing great potential in single-cell analysis, targeted drug delivery, and surgery.

Parallel non-dominated sorting genetic algorithm-II-based image encryption technique

ABSTRACTChaotic system requires parameters to generate random sequences. Recent studies show that the improper selection of parameter values make secret keys generated from chaotic system vulnerable. Meta-heuristic techniques have been introduced in the area of image encryption to improve the selection of chaotic system parameters. But, these techniques suffer from poor computational speed. To overcome this issue, in this paper, a parallel Non-Dominated Sorting Genetic Algorithm (NSGA-II)-based intertwining logistic map is proposed to encrypt the images. To implement NSGA-II in parallel fashion, master–slave environment is designed. Initially, the execution time analysis of NSGA-II is done to determine the computationally expensive operations. Thereafter, NSGA-II operators are divided into master and slave jobs. The Message Passing Interface (MPI) is used for intercommunication between master and slave nodes. The simulation results show that the parallel proposed technique provides a significant improvement in computational speed as compared to the existing techniques.

Design of a K-Winners-Take-All Model With a Binary Spike Train.

A continuous-time K -winners-take-all (KWTA) neural model that can identify the largest K of N inputs, where command signal is described. The model is given by a differential equation where the spike train is a sum of delta functions. A functional block-diagram of the model includes N feed-forward hard-limiting neurons and one feedback neuron, used to handle input dynamics. The existence and uniqueness of the model steady states are analyzed, the convergence analysis of the state variable trajectories to the KWTA operation is proven, the convergence time and number of spikes required are derived, as well as the processing of time-varying inputs and perturbations of the model nonlinearities are analyzed. The main advantage of the model is that it is not subject to the intrinsic convergence of speed limitations of comparable designs. The model also has an arbitrary finite resolution determined by a given parameter, low complexity, and initial condition independence. Applications of the model for parallel sorting and parallel rank-order filtering are presented. Theoretical results are derived and illustrated with computer-simulated examples that demonstrate the model's performance.

Apophatic Theology and Twentieth-Century Novels

Abstract Drawing on apophatic theology, this essay argues that some twentieth-century texts invite an apophatic approach by revealing the limits of language and hinting at some understanding of God, without doing so directly. First, Leif Enger’s Peace Like a River shows a divine encounter but, in the process, underscores the limits of language to describe this experience. Second, in a sort of parallel to negative theology, Walker Percy’s Lancelot points readers toward God by having Lancelot descend into sin and evil, an affirmation of God through negation. Finally, in Joseph Heller’s Catch-22, a novel without explicit Christian interests, characters parody prayer, rail against the world’s unfairness, and deny God, but in these interactions they actually reveal something about belief and God. These texts reveal that an apophatic understanding can enrich our reading of twentieth-century novels.

Parallel sorting of orbital and spin angular momenta of light in a record large number of channels.

Parallel sorting of orbital and spin angular momentum components of structured optical beams is demonstrated. Both spin channels are multiplexed within the novel orbital angular momentum (OAM) sorter, reducing the size, weight, and number of elements. The sorted states are linearly spaced over 70 topological charge values. We experimentally and theoretically evaluate the operational range and crosstalk between neighboring channels and find that 30 orbital angular momentum states are available per spin channel for quantum communication or cryptography. This is achieved using an angular momentum sorter that we developed based on geometric phase optical elements. We present two devices consisting of liquid crystal polymer films photoaligned with complex two-dimensional patterns.

A Framework for the Automatic Vectorization of Parallel Sort on x86-Based Processors

The continued growth in the width of vector registers and the evolving library of intrinsics on the modern x86 processors make manual optimizations for data-level parallelism tedious and error-prone. In this paper, we focus on parallel sorting, a building block for many higher-level applications, and propose a framework for the Automatic SIMDization of Parallel Sorting (ASPaS) on x86-based multi- and many-core processors. That is, ASPaS takes any sorting network and a given instruction set architecture (ISA) as inputs and automatically generates vector code for that sorting network. After formalizing the sort function as a sequence of comparators and the transpose and merge functions as sequences of vector-matrix multiplications, ASPaS can map these functions to operations from a selected “pattern pool” that is based on the characteristics of parallel sorting, and then generate the vector code with the real ISA intrinsics. The performance evaluation on the Intel Ivy Bridge and Haswell CPUs, and Knights Corner MIC illustrates that automatically generated sorting codes from ASPaS can outperform the widely used sorting tools, achieving up to 5.2x speedup over the single-threaded implementations from STL and Boost and up to 6.7x speedup over the multi-threaded parallel sort from Intel TBB.

Parallel kd-Tree Construction on the GPU with an Adaptive Split and Sort Strategy

We introduce a parallel kd-tree construction method for 3-dimensional points on a GPU which employs a sorting algorithm that maintains high parallelism throughout construction. Typically, large arrays in the upper levels of a kd-tree do not yield high performance when computing each node in one thread. Conversely, small arrays in the lower levels of the tree do not benefit from typical parallel sorts. To address these issues, the proposed sorting approach uses a modified parallel sort on the upper levels before switching to basic parallelization on the lower levels. Our work focuses on 3D point registration and our results indicate that a speed gain by a factor of 100 can be achieved in comparison to a naive parallel algorithm for a typical scene.