Parallel Network Simulator Research Articles

Parallel Simulation of Quantum Networks with Distributed Quantum State Management

Quantum network simulators offer the opportunity to cost-efficiently investigate potential avenues for building networks that scale with the number of users, communication distance, and application demands by simulating alternative hardware designs and control protocols. Several quantum network simulators have been recently developed with these goals in mind. As the size of the simulated networks increases, however, sequential execution becomes time-consuming. Parallel execution presents a suitable method for scalable simulations of large-scale quantum networks, but the unique attributes of quantum information create unexpected challenges. In this work, we identify requirements for parallel simulation of quantum networks and develop the first parallel discrete-event quantum network simulator by modifying the existing serial simulator SeQUeNCe. Our contributions include the design and development of a quantum state manager (QSM) that maintains shared quantum information distributed across multiple processes. We also optimize our parallel code by minimizing the overhead of the QSM and decreasing the amount of synchronization needed among processes. Using these techniques, we observe a speedup of 2 to 25 times when simulating a 1,024-node linear network topology using 2 to 128 processes. We also observe an efficiency greater than 0.5 for up to 32 processes in a linear network topology of the same size and with the same workload. We repeat this evaluation with a randomized workload on a caveman network. We also introduce several methods for partitioning networks by mapping them to different parallel simulation processes. We have released the parallel SeQUeNCe simulator as an open source tool alongside the existing sequential version.

A universal parallel simulation framework for energy pipeline networks on high-performance computers

Energy distribution networks represent crucial infrastructures for modern society, and various simulation tools have been widely used by energy suppliers to manage these intricate networks. However, simulation calculations include a large number of fluid control equations, and computational overhead limits the performance of simulation software. This paper proposes a universal parallel simulation framework for energy pipeline networks that takes advantages of data parallelism and computational independence between network elements. A non-pipe model of an energy supply network is optimized, and the input and output of the network model in the proposed framework are modified, which can reduce the development burden during the numerical computations of the pipeline network and weaken the computational correlation between different simulated components. In addition, independent computations can be performed concurrently through periodic data exchange procedures between component instances, improving the parallelism and efficiency of simulation computations. Further, a parallel water pipelines network simulation computing paradigm based on a heterogeneous computer hardware architecture is used to evaluate the proposed framework’s performance. A series of tests are conducted to verify the accuracy of the proposed framework, and simulation errors of less than 5% are achieved. The results of multi-threaded simulation experiments have demonstrated the feasibility of the proposed framework in a parallel computing approach. Moreover, an Advanced Micro Devices (AMD) Deep Computing Unit (DCU)-parallel program is implemented into a water supply network simulation system; the computational efficiency of this system is compared with that of its serial counterpart. The experimental results show that the proposed framework is appropriate for high-performance computer architectures, and the 18x speed-up ratio demonstrates that the parallel program based on the proposed universal framework outperforms the serial program. That provides the basis for the application of pipe network simulation on high-performance computers.

An efficient topology partitioning algorithm for system-level parallel simulation of mega satellite constellation communication networks

Satellite Internet, as an important component of the integrated space-ground information network, is a hot research hotspot nowadays. Many scholars have undertaken research in the areas of constellation networking design, network protocol design, and communication performance assessment, and their main research tool is software simulation. Traditional stand-alone network simulation simulators based on OPNET or NS3 are constrained in the simulation efficiency of mega satellite networks because of the limitations of computer hardware conditions and software performance. Based on the above characteristics, we propose a parallel network simulation architecture based on low correlation between different areas of the global satellite network, and in order to improve the parallel network simulation performance, the network topology needs to be divided effectively. Therefore, firstly we consider CPU and memory resource consumption as a measure of topology partitioning performance indicators, propose a resource assessment algorithm and use the result of this assessment as the topology partitioning optimization objective; secondly, we propose a load balancing based intelligent topology partitioning algorithm (LBTP); thirdly, we propose a time slice algorithm (TSA) for parallel simulation in each time cycle. To demonstrate the algorithm proposed in this paper, we built a simulation platform based on the combination of STK (Satellite Tool Kit), OPNET and Proxmox VE, and experimentally verified that the proposed architecture and algorithm significantly improve the simulation efficiency.

Asynchronous Background Processing for accelerated simulation of wireless communication on multi-core systems

Discrete event simulation (DES) is an important tool for the development and analysis of wireless networks. However, with increasing network size and complexity, the computational effort and simulation time increases significantly, often exponentially. This increase in response time may be critical if DES is interfacing real-time systems like Hardware in the Loop (HIL) or network emulation. It also slows down development cycles of users designing or debugging simulation models. Most popular DES software packages run single-threaded. Thus, they achieve only limited performance improvements from more modern multi-core CPUs. At the same time, existing approaches for parallel simulation of networks do not perform well on wireless systems or require complex paradigm shifts in simulation models. In this paper, we propose Asynchronous Background Processing (ABP) to accelerate the simulation of wireless communication on multi-core systems. By moving expensive computation from the main thread into asynchronous tasks computed by background threads, it accelerates the progression of events and thus reduces response time. Tasks are started as early as possible to exploit the time the main thread spends processing other events, ideally providing results before they are needed in the simulation. We showcase the application of ABP using Veins, a popular vehicular network simulator, demonstrating speedups of up to 3.5 on typical desktop platforms. We further perform an in-depth analysis using advanced profiling techniques to investigate the effectiveness of the parallelization and guide further optimizations.

A Scalable Quantum Key Distribution Network Testbed Using Parallel Discrete-Event Simulation

Quantum key distribution (QKD) has been promoted as a means for secure communications. Although QKD has been widely implemented in many urban fiber networks, the large-scale deployment of QKD remains challenging. Today, researchers extensively conduct simulation-based evaluations for their designs and applications of large-scale QKD networks for cost efficiency. However, the existing discrete-event simulators offer models for QKD hardware and protocols based on sequential event execution, which limits the scale of the experiments. In this work, we explore parallel simulation of QKD networks to address this issue. Our contributions lay in the exploration of QKD network characteristics to be leveraged for parallel simulation as well as the development of a parallel simulation framework for QKD networks. We also investigate three techniques to improve the simulation performance including (1) a ladder queue based event list, (2) memoization for computationally intensive quantum state transformation information, and (3) optimization of the network partition scheme for workload balance. The experimental results show that our parallel simulator is 10 times faster than a sequential simulator when simulating a 128-node QKD network. Our linear-regression-based network partition scheme can further accelerate the simulation experiments up to two times over using a randomized network partition scheme.

A compiler for biological networks on silicon chips.

The explosive growth in semiconductor integrated circuits was made possible in large part by design automation software. The design and/or analysis of synthetic and natural circuits in living cells could be made more scalable using the same approach. We present a compiler which converts standard representations of chemical reaction networks and circuits into hardware configurations that can be used to simulate the network on specialized cytomorphic hardware. The compiler also creates circuit–level models of the target configuration, which enhances the versatility of the compiler and enables the validation of its functionality without physical experimentation with the hardware. We show that this compiler can translate networks comprised of mass–action kinetics, classic enzyme kinetics (Michaelis–Menten, Briggs–Haldane, and Botts–Morales formalisms), and genetic repressor kinetics, thereby allowing a large class of models to be transformed into a hardware representation. Rule–based models are particularly well–suited to this approach, as we demonstrate by compiling a MAP kinase model. Development of specialized hardware and software for simulating biological networks has the potential to enable the simulation of larger kinetic models than are currently feasible or allow the parallel simulation of many smaller networks with better performance than current simulation software.

Parallel Closed-Loop Connected Vehicle Simulator for Large-Scale Transportation Network Management: Challenges, Issues, and Solution Approaches

The augmented scale and complexity of urban transportation networks have significantly increased the execution time and resource requirements of vehicular network simulations, exceeding the capabilities of sequential simulators. The need for a parallel and distributed simulation environment is inevitable from a smart city perspective, especially when the entire city-wide information system is expected to be integrated with numerous services and ITS applications. In this paper, we present a conceptual model of an Integrated Distributed Connected Vehicle Simulator (IDCVS) that can emulate real-time traffic in a large metro area by incorporating hardware-in-the-loop simulation together with the closed-loop coupling of SUMO and OMNET++. We also discuss the challenges, issues, and solution approaches for implementing such a parallel closed-loop transportation network simulator by addressing transportation network partitioning problems, synchronization, and scalability issues. One unique feature of the envisioned integrated simulation tool is that it utilizes the vehicle traces collected through multiple roadway sensors? DSRC onboard unit, magnetometer, loop detector, and video detector. Another major feature of the proposed model is the incorporation of hybrid parallelism in both transportation and communication simulation platforms. We identify the challenges and issues involved in IDCVS to incorporate this multi-level parallelism. We also discuss the approaches for integrating hardware-in-the-loop simulation, addressing the steps involved in preprocessing sensor data, filtering, and extrapolating missing data, managing large real-time traffic data, and handling different data formats.

Wirelength of embedding complete multipartite graphs into certain graphs

Graph embedding is an important technique that maps a guest graph into a host graph, usually an interconnection network. Many applications can be modeled as graph embedding. In architecture simulation, graph embedding has been known as a powerful tool for implementation of parallel algorithms or simulation of different interconnection networks. The quality of an embedding can be measured by certain cost criteria. One of these criteria is the wirelength and has been well studied by many authors (Lai and Tsai, 2010 [18]; Fan and Jia, 2007 [10]; Han et al., 2010 [15]; Fang and Lai, 2005 [11]; Park and Chwa, 2000 [23]; Rajasingh et al., 2004; Yang et al., 2010; Yang, 2009 [27]; Manuel et al., 2009; Bezrukov et al., 1998; Rostami and Habibi, 2008 [26]; Choudum and Nahdini, 2004 [7]; Guu, 1997 [14]). In this paper, we compute the exact wirelength of embedding complete multipartite graphs into certain graphs, such as path, cycle, wheel, hypertree, cylinder, torus and 3-regular circulant graphs.

Parallel simulation of adaptive random Boolean networks using the GPGPU technology

Parallel simulation of adaptive random Boolean networks using the GPGPU technology

Parallel Brain Simulator: A Multi-scale and Parallel Brain-Inspired Neural Network Modeling and Simulation Platform

The brain is naturally a parallel and distributed system. Reverse engineering a cognitive brain is considered to be a grand challenge. In this paper, we present the parallel brain simulator (PBS), a parallel and distributed platform for modeling the cognitive brain at multiple scales. Inspired by large-scale graph computation, PBS can be considered as a universal parallel execution engine, which is aimed at reducing the complexity of distributed programming and providing an easy to use programmable platform for computational neuroscientists and artificial intelligence researchers for modeling and simulation of large-scale neural networks. As illustrative examples and validations, three brain-inspired neural networks which are built on PBS are introduced, including the 1:1 human hippocampus network, the 1:1 mouse whole-brain network and the CASIA brain simulator built for cognitive robotics. We deploy PBS on both commodity clusters and supercomputers, and a scalable performance is achieved. In addition, we provide evaluations on the scalability and performance of both lumped synapse-based simulation and non-lumped synapse-based simulation with different data-graph distribution methods to show the effectiveness and usability of the PBS platform.

From GUI to GPU: A toolchain for GPU code generation for large scale Drosophila simulations using SpineML

From GUI to GPU: A toolchain for GPU code generation for large scale Drosophila simulations using SpineML

Parallel Simulation and Virtual-Machine-Based Emulation of Software-Defined Networks

The emerging software-defined networking (SDN) technology decouples the control plane from the data plane in a computer network with open and standardized interfaces, and hence opens up the network designers’ options and ability to innovate. The wide adoption of SDN in industry has motivated the development of large-scale, high-fidelity testbeds for evaluation of systems that incorporate SDN. In this article, we develop a framework to support OpenFlow-based SDN simulation and distributed emulation, by leveraging our prior work on a hybrid network testbed with a parallel network simulator and a virtual-machine-based emulation system. We show how to exploit typical SDN controller behaviors to handle performance issues caused by the centralized controller in parallel discrete-event simulation. In particular, we develop an asynchronous synchronization algorithm for passive SDN controllers and design a two-level architecture for active SDN controllers. We evaluate the system performance, showing good scalability. Finally, we present a case study, using the testbed, to evaluate network verification applications in an SDN-based data center network.

A parallel network simulation and virtual time-based network emulation testbed

To analyse large-scale systems with high fidelity, it is necessary for a network testbed to offer both realistic emulation (to represent software execution) and effective simulation (to model background computation and communication). We present a network testbed that integrates a lightweight emulation system (modified earlier to operate in virtual time) with a parallel discrete event network simulator. Our contributions lie in the design of a global synchronization algorithm to manage virtual time as it transitions from emulation to simulation, and back. In particular, we optimize our previous algorithm to reduce overhead of synchronizations across simulation and emulation. We also address the unavoidable uncertainties introduced by the emulation by obtaining analytical bounds for the error, and produce empirical data showing that the error is as small as the minimum system execution unit. In addition, we observe excellent system scalability with large-scale network experiments, and demonstrate the performance improvement of the optimized global synchronization algorithm.

Layout of Embedding Circulant Networks into Linear Hexagons and Phenylenes

Circulant network has been used for decades in the design of computer and telecommunication networks due to optimal fault-tolerance and routing capabilities. Further, it has been used in VLSI design and distributed computation. Hexagonal chains are of great importance of theoretical chemistry because they are the natural graph representations of benzenoid hydrocarbons, a great deal of investigations in mathematical chemistry has been developed to hexagonal chains. Hexagonal chains are exclusively constructed by hexagons of length one. Phenylenes are a class of chemical compounds in which carbon atoms form 6 and 4 membered cycles. Graph embedding has been known as a powerful tool for implementation of parallel algorithms or simulation of different interconnection networks. An embedding f of a guest graph G into a host graph H is a bijection on the vertices such that each edge of G is mapped into a path of H. The wirelength (layout) of this embedding is defined to be the sum of the length of the paths corresponding to the edges of G. In this paper we obtain the minimum wirelength of embedding circulant networks into linear hexagonal chains and linear phenylenes. Further we discuss the embedding of faulty circulant networks into linear hexagonal chains and linear phenylenes.

EMBEDDING VARIANTS OF HYPERCUBES WITH DILATION 2

Graph embedding has been known as a powerful tool for implementation of parallel algorithms and simulation of interconnection networks. In this paper, we introduce a technique to obtain a lower bound for the dilation of an embedding. Moreover, we give algorithms for embedding variants of hypercubes with dilation 2 proving that the lower bound obtained is sharp. Further, we compute the exact wirelength of embedding folded hypercubes and augmented cubes into hypercubes.

A parallel simulator for network terminal packet buffer

In this paper we present the design and implementation of a parallel network simulator to manipulate the shared-memory packet buffer in a network interface card (NIC) for a network terminal. The proposed simulator consists of two components, input generator and buffer management simulator. The simulator flexibly accommodates either a dynamic or a static packet buffer management algorithm for a high-speed Ethernet to deliver fast and accurate clock-cycle level data analysis. In addition, it is transparent to trace and analyze the concurrent operations in the packet buffer and, thus, the simulator contributes to developing efficient buffer management algorithms.

Flexible and efficient recording of neuronal properties in large network simulations: The NEST Multimeter

In computer simulations, all quantities are known and thus in principle available for recording and analysis. Collecting data from large simulations in an efficient and flexible manner is still challenging. Dumping all available data to file generates huge amounts of data, requiring significant post-processing to extract relevant information. Instrumenting all parts of a complex simulator for recording is also not trivial, especially with respect to file management and data collection in parallel simulations. We have developed the NEST Multimeter to facilitate flexible and efficient data recording from large-scale parallel neuronal network simulations with the NEST simulator [1]. Design goals were to: (i) allow users to selectively record neuron properties, e.g., membrane potential; (ii) provide a unified user interface for all types of recordings; (iii) support recording in parallel simulations; (iv) minimize the computation time overhead; and (v) provide an API that allows model developers to make any scalar quantity in a model neuron available for recording. From NEST version 2.0.0-RC1 onward (available from http://www.nest-initiative.org), all NEST neuron models support multimeter recording and the user can easily enquire the recordable quantities: reveals that the conductance-based adaptive exponential integrate-and-fire neuron model [2] supports recording of the membrane potential (V_m), excitatory and inhibitory synaptic conductances (g_ex, g_in) and the adaptation current (w). We record membrane potential and adaptation current by connecting a properly configured multimeter: After simulating for 5ms, we obtain the recorded values from the multimeter: Data can also be recorded to files, with one file per virtual process, ensuring conflict-free recording in parallel simulations. When data is retrieved as illustrated above, it is combined across threads, but not MPI processes. A multimeter can record from an arbitrary number of neurons. Model developers instrument a model for recording by adding a small amount of boilerplate code to models: a UniversalDataLogger (UDL) member collecting recorded values temporarily, and a RecordablesMap (RM): When the multimeter is connected to a neuron, it informs the UniversalDataLogger about which entries of the RM shall be recorded. Once per time step, the model neuron calls UDL::record_data(), which collects the required data using the access functions specified in the RM. Once per minimal delay interval, the multimeter collects the data from the UDLs of all connected neurons and stores it in memory or writes it to file.

ArchSim: A System-Level Parallel Simulation Platform for the Architecture Design of High Performance Computer

High performance computer (HPC) is a complex huge system, of which the architecture design meets increasing difficulties and risks. Traditional methods, such as theoretical analysis, component-level simulation and sequential simulation, are not applicable to system-level simulations of HPC systems. Even the parallel simulation using large-scale parallel machines also have many difficulties in scalability, reliability, generality, as well as efficiency. According to the current needs of HPC architecture design, this paper proposes a system-level parallel simulation platform: ArchSim. We first introduce the architecture of ArchSim simulation platform which is composed of a global server (GS), local server agents (LSA) and entities. Secondly, we emphasize some key techniques of ArchSim, including the synchronization protocol, the communication mechanism and the distributed checkpointing/restart mechanism. We then make a synthesized test of some main performance indices of ArchSim with the phold benchmark and analyze the extra overhead generated by ArchSim. Finally, based on ArchSim, we construct a parallel event-driven interconnection network simulator and a system-level simulator for a small scale HPC system with 256 processors. The results of the performance test and HPC system simulations demonstrate that ArchSim can achieve high speedup ratio and high scalability on parallel host machine and support system-level simulations for the arhitecture design of HPC systems.

An Efficient Statistical Synchronization Method For Parallel Simulation

In this paper, we propose the improved Statistical Synchronization Method (SSM-T) for parallel discrete event simulation. Criteria are given for the time-driven approach (SSM-T). It is proven that the level of the output error can be guaranteed. SSM-T is implemented in the OMNeT++ discrete event simulation tool, which is a useful and widespread framework for creating various simulation models to evaluate the performance of telecommunication networks. Case studies have been performed, which shows that SSM-T is a very efficient synchronization method for the parallel simulation of communication networks.

Neuron splitting in compute-bound parallel network simulations enables runtime scaling with twice as many processors

Neuron tree topology equations can be split into two subtrees and solved on different processors with no change in accuracy, stability, or computational effort; communication costs involve only sending and receiving two double precision values by each subtree at each time step. Splitting cells is useful in attaining load balance in neural network simulations, especially when there is a wide range of cell sizes and the number of cells is about the same as the number of processors. For compute-bound simulations load balance results in almost ideal runtime scaling. Application of the cell splitting method to two published network models exhibits good runtime scaling on twice as many processors as could be effectively used with whole-cell balancing.