EREW Research Articles

Unifying lower bounds for algebraic machines, semantically

We present a new abstract method for proving lower bounds in computational complexity based on the notion of topological and measurable entropy for dynamical systems. It is shown to generalise several previous lower bounds results from the literature in algebraic complexity, thus providing a unifying framework for “topological” proofs of lower bounds. We further use this method to prove that maxflow, a ▪ complete problem, is not computable in polylogarithmic time on parallel random access machines (prams) working with real numbers. This improves on a result of Mulmuley since the class of machines considered extends the class “prams without bit operations”, making more precise the relationship between Mulmuley's result and similar lower bounds on real prams.

Triangle Centrality

Triangle centrality is introduced for finding important vertices in a graph based on the concentration of triangles surrounding each vertex. It has the distinct feature of allowing a vertex to be central if it is in many triangles or none at all. Given a simple, undirected graph \(G=(V,E)\) with \(n=|V|\) vertices and \(m=|E|\) edges, let \(\triangle(v)\) and \(\triangle(G)\) denote the respective triangle counts of \(v\) and \(G\) . Let \(N(v)\) be the neighborhood set of \(v\) . Respectively, \(N_{\triangle}(v)\) and \(N_{\triangle}[v]=\{v\}\cup N_{\triangle}(v)\) denote the set of neighbors that are in triangles with \(v\) and the closed set including \(v\) . Then the triangle centrality for a vertex \(v\) is \(\begin{align*}TC(v)=\frac{\frac{1}{3}\sum_{u\in N_{\triangle}[v]}\triangle(u)+\sum_{w\in\{N(v)\setminus N_{\triangle}(v)\}}\triangle(w)}{\triangle(G)}.\end{align*}\) We show experimentally that triangle centrality is broadly applicable to many different types of networks. Our empirical results demonstrate that 30% of the time triangle centrality identified central vertices that differed with those found by five well-known centrality measures, which suggests novelty without being overly specialized. It is also asymptotically faster to compute on sparse graphs than all but the most trivial of these other measures. We introduce optimal algorithms that compute triangle centrality in \(O(m\overline{\delta})\) time and \(O(m+n)\) space, where \(\overline{\delta}\leq O(\sqrt{m})\) is the average degeneracy introduced by Burkhardt, Faber, and Harris (2020). In practical applications, \(\overline{\delta}\) is much smaller than \(\sqrt{m}\) so triangle centrality can be computed in nearly linear time. On a Concurrent Read Exclusive Write (CREW) Parallel Random Access Machine (PRAM), we give a near work-optimal parallel algorithm that takes \(O(\log n)\) time using \(O(m\sqrt{m})\) CREW PRAM processors. In MapReduce, we show it takes four rounds using \(O(m\sqrt{m})\) communication bits and is therefore optimal. We also derive a linear algebraic formulation of triangle centrality which can be computed in \(O(m\overline{\delta})\) time on sparse graphs.

Imperative Process Algebra and Models of Parallel Computation

Studies of issues related to computability and computational complexity involve the use of a model of computation. Central in such a model are computational processes. Processes of this kind can be described using an imperative process algebra based on ACP (Algebra of Communicating Processes). In this paper, it is investigated whether the imperative process algebra concerned can play a role in the field of models of computation. It is demonstrated that the process algebra is suitable to describe in a mathematically precise way models of computation corresponding to existing models based on sequential, asynchronous parallel, and synchronous parallel random access machines as well as time and work complexity measures for those models.

Constrained read-once refutations in UTVPI constraint systems: A parallel perspective

AbstractIn this paper, we analyze two types of refutations for Unit Two Variable Per Inequality (UTVPI) constraints. A UTVPI constraint is a linear inequality of the form: $a_{i}\cdot x_{i}+a_{j} \cdot x_{j} \le b_{k}$ , where $a_{i},a_{j}\in \{0,1,-1\}$ and $b_{k} \in \mathbb{Z}$ . A conjunction of such constraints is called a UTVPI constraint system (UCS) and can be represented in matrix form as: ${\bf A \cdot x \le b}$ . UTVPI constraints are used in many domains including operations research and program verification. We focus on two variants of read-once refutation (ROR). An ROR is a refutation in which each constraint is used at most once. A literal-once refutation (LOR), a more restrictive form of ROR, is a refutation in which each literal ( $x_i$ or $-x_i$ ) is used at most once. First, we examine the constraint-required read-once refutation (CROR) problem and the constraint-required literal-once refutation (CLOR) problem. In both of these problems, we are given a set of constraints that must be used in the refutation. RORs and LORs are incomplete since not every system of linear constraints is guaranteed to have such a refutation. This is still true even when we restrict ourselves to UCSs. In this paper, we provide NC reductions between the CROR and CLOR problems in UCSs and the minimum weight perfect matching problem. The reductions used in this paper assume a CREW PRAM model of parallel computation. As a result, the reductions establish that, from the perspective of parallel algorithms, the CROR and CLOR problems in UCSs are equivalent to matching. In particular, if an NC algorithm exists for either of these problems, then there is an NC algorithm for matching.

Tunnel: Parallel-inducing sort for large string analytics

The suffix array is a crucial data structure for efficient string analysis. Over the course of twenty-six years, sequential suffix array construction algorithms have achieved O(n) time complexity and in-place sorting. In this paper, we present the Tunnel algorithm, the first large-scale parallel suffix array construction algorithm with a time complexity of Onp based on the parallel random access machine (PRAM) model. The Tunnel algorithm is built on three key ideas: dividing the problem of size O(n) into p sub-problems of reduced size Onp by replacing long suffixes with shorter prefixes of size at most a constant D; introducing a Tunnel mechanism to efficiently induce the order of a set of suffixes with long common prefixes; developing a strategy to transform a partially ordered suffix set into a total order relation by iteratively applying the Tunnel inducing method. We provide a detailed description of the algorithm, along with a thorough analysis of its time and space complexity, to demonstrate its correctness and efficiency. The proposed Tunnel algorithm exhibits scalable performance, making it suitable for large string analytics on large-scale parallel systems.

Sorting Real Numbers in Constant Time Using n^2/log^cn Processors

We study the sorting of real numbers into a linked list on the PRAM (Parallel Random-Access Machine) model. We show that n real numbers can be sorted into a linked list in constant time using n2 processors. Previously n numbers can be sorted into a linked list using n2 processors in O(loglogn) time. We also study the time processor trade-off for sorting real numbers into a linked list on the PRAM (Parallel Random Access Machine) model. We show that n real numbers can be sorted into a linked list with n2/t processors in O(logt) time. Previously n real numbers can be sorted into a linked list using n3 processors in constant time and n2 processors in O(loglogn). And then we show that input array of n real numbers can be sorted into linked list in constant time using n2/logcn processors for any positive constant c. We believe that further reduction on the number of processors for sorting real numbers in constant time will be very difficult if not impossible.

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks

Spiking neural networks (SNNs) compute in an event-based manner to achieve a more efficient computation than standard neural networks. In SNNs, neuronal outputs are not encoded as real-valued activations but as sequences of binary spikes. The motivation of using SNNs over conventional neural networks is rooted in the special computational aspects of spike-based processing, especially the high degree of sparsity of spikes. Well-established implementations of convolutional neural networks (CNNs) feature large spatial arrays of processing elements (PEs) that remain highly underutilized in the face of activation sparsity. We propose a novel architecture optimized for the processing of convolutional SNNs (CSNNs) featuring a high degree of sparsity. The proposed architecture consists of an array of PEs of the size of the kernel of a convolution and an intelligent spike queue that provides a high PE utilization. A constant flow of spikes is ensured by compressing the feature maps into queues that can then be processed spike-by-spike. This compression is performed at run-time, leading to a self-timed schedule. This allows the processing time to scale with the number of spikes. Also, a novel memory organization scheme is introduced to efficiently store and retrieve the membrane potentials of the individual neurons using multiple small parallel on-chip RAMs. Each RAM is hardwired to its PE, reducing switching circuitry. We implemented the proposed architecture on an FPGA and achieved a significant speedup compared to previously proposed SNN implementations (~10 times) while needing less hardware resources and maintaining a higher energy efficiency (~15 times).

SPARKs: Succinct Parallelizable Arguments of Knowledge

We introduce the notion of aSuccinct Parallelizable Argument of Knowledge(SPARK). This is an argument of knowledge with the following three efficiency properties for computing and proving a (non-deterministic, polynomial time) parallel RAM computation that can be computed in parallel timeTwith at mostpprocessors:—The prover’s (parallel) running time is\( T + \mathrm{poly}\hspace{-2.0pt}\log (T \cdot p) \). (In other words, the prover’s running time is essentiallyTfor large computation times!)—The prover uses at most\( p \cdot \mathrm{poly}\hspace{-2.0pt}\log (T \cdot p) \)processors.—The communication and verifier complexity are both\( \mathrm{poly}\hspace{-2.0pt}\log (T \cdot p) \).The combination of all three is desirable, as it gives a way to leverage a moderate increase in parallelism in favor of near-optimal running time. We emphasize that even a factor two overhead in the prover’s parallel running time is not allowed.Our main contribution is a generic construction of SPARKs from any succinct argument of knowledge where the prover’s parallel running time is\( T \cdot \mathrm{poly}\hspace{-2.0pt}\log (T \cdot p) \)when usingpprocessors, assuming collision-resistant hash functions. When suitably instantiating our construction, we achieve a four-round SPARK foranyparallel RAM computation assuming only collision resistance. Additionally assuming the existence of a succinctnon-interactiveargument of knowledge (SNARK), we construct a non-interactive SPARK that also preserves the space complexity of the underlying computation up to\( \mathrm{poly}\hspace{-2.0pt}\log (T\cdot p) \)factors.We also show the following applications of non-interactive SPARKs. First, they immediately imply delegation protocols with near optimal prover (parallel) running time. This, in turn, gives a way to construct verifiable delay functions (VDFs) from any sequential function. When the sequential function is also memory-hard, this yields the first construction of a memory-hard VDF.

An Improved Parallel Prefix Sums Algorithm

The prefix sums problem for an array [Formula: see text] is to compute all sums [Formula: see text], [Formula: see text]. In this paper, we introduce an improvement for the best previous algorithm that runs in [Formula: see text] time using [Formula: see text] processors on a Sum Concurrent Read Concurrent Write, Parallel Random Access Machine (Sum-CRCW PRAM). The improvements include (1) reducing the total number of operations and (2) reducing the amount of storage required by the algorithm.

Exploring the environmental efficiency of airlines through a parallel RAM approach.

Air pollution in the aviation industry is becoming increasingly severe worldwide, along with rapid economic development. Therefore, it is significant to pay close attention to airlines worldwide. Usually, the airlines contain passenger transportation and freight transportation on the operating move. This paper proposes a parallel range adjusted measure (PRAM) to comprehensively measure and evaluate the environmental efficiency of 18 airlines from 2014 to 2019. Different from existing models, the model can handle shared inputs, shared desirable outputs, and shared undesirable outputs simultaneously. We build a shared resource decomposition procedure to perform a comparative analysis of the highest subsystem efficiency, and the sensitivity analysis proves the validity of the results. The main findings are as follows: 1. The optimal efficiency can be achieved by most of the 18 airlines when sharing resources; 2. Operating costs in the freight system should be increased to achieve optimal efficiency; 3. Asian airlines show higher efficiency than the airlines in Europe.

Simple Concurrent Connected Components Algorithms

We study a class of simple algorithms for concurrently computing the connected components of an n -vertex, m -edge graph. Our algorithms are easy to implement in either the COMBINING CRCW PRAM or the MPC computing model. For two related algorithms in this class, we obtain Θ (lg n ) step and Θ (m lg n ) work bounds. 1 For two others, we obtain O (lg 2 n ) step and O (m lg 2 n ) work bounds, which are tight for one of them. All our algorithms are simpler than related algorithms in the literature. We also point out some gaps and errors in the analysis of previous algorithms. Our results show that even a basic problem like connected components still has secrets to reveal.

More Efficient Parallel Integer Sorting

We present a more efficient CREW PRAM algorithm for integer sorting. This algorithm sorts [Formula: see text] integers in [Formula: see text] in [Formula: see text] time and [Formula: see text] operations. It also sorts [Formula: see text] integers in [Formula: see text] in [Formula: see text] time and [Formula: see text] operations. Previous best algorithm [15] on both cases has time complexity [Formula: see text] but operation complexity [Formula: see text].

Taming the knight's tour: Minimizing turns and crossings

We introduce two new metrics of “simplicity” for knight's tours: the number of turns and the number of crossings. We give a novel algorithm that produces tours with 9.25n+O(1) turns and 12n+O(1) crossings on an n×n board, and we show lower bounds of (6−ϵ)n and 4n−O(1) on the respective problems of minimizing these metrics. Hence, our algorithm achieves approximation ratios of 9.25/6+o(1) and 3+o(1). Our algorithm takes linear time and is fully parallelizable, i.e., the tour can be computed in O(n2/p) time using p processors in the CREW PRAM model. We generalize our techniques to rectangular boards, high-dimensional boards, symmetric tours, odd boards with a missing corner, and tours for (1,4)-leapers. In doing so, we show that these extensions also admit a constant approximation ratio on the minimum number of turns, and on the number of crossings in most cases.

Graph Connectivity in Log Steps Using Label Propagation

The fastest deterministic algorithms for connected components take logarithmic time and perform superlinear work on a Parallel Random Access Machine (PRAM). These algorithms maintain a spanning forest by merging and compressing trees, which requires pointer-chasing operations that increase memory access latency and are limited to shared-memory systems. Many of these PRAM algorithms are also very complicated to implement. Another popular method is “leader-contraction” where the challenge is to select a constant fraction of leaders that are adjacent to a constant fraction of non-leaders with high probability, but this can require adding more edges than were in the original graph. Instead we investigate label propagation because it is deterministic, easy to implement, and does not rely on pointer-chasing. Label propagation exchanges representative labels within a component using simple graph traversal, but it is inherently difficult to complete in a sublinear number of steps. We are able to overcome the problems with label propagation for graph connectivity. We introduce a surprisingly simple framework for deterministic, undirected graph connectivity using label propagation that is easily adaptable to many computational models. It achieves logarithmic convergence independently of the number of processors and without increasing the edge count. We employ a novel method of propagating directed edges in alternating direction while performing minimum reduction on vertex labels. We present new algorithms in PRAM, Stream, and MapReduce. Given a simple, undirected graph [Formula: see text] with [Formula: see text] vertices, [Formula: see text] edges, our approach takes O(m) work each step, but we can only prove logarithmic convergence on a path graph. It was conjectured by Liu and Tarjan (2019) to take [Formula: see text] steps or possibly [Formula: see text] steps. Our experiments on a range of difficult graphs also suggest logarithmic convergence. We leave the proof of convergence as an open problem.

A Parallel Algorithm for Scheduling a Two-Machine Robotic Cell in Bicycle Frame Welding Process

Welding frames with differing geometries is one of the most crucial stages in the production of high-end bicycles. This paper proposes a parallel algorithm and a mixed integer linear programming formulation for scheduling a two-machine robotic welding station. The time complexity of the introduced parallel method is O(log2n) on an n3-processor Exclusive Read Exclusive Write Parallel Random-Access Machine (EREW PRAM), where n is the problem size. The algorithm is designed to take advantage of modern graphics cards to significantly accelerate the computations. To present the benefits of the parallelization, the algorithm is compared to the state of art sequential method and a solver-based approach. Experimental results show an impressive speedup for larger problem instances—up to 314 on a single Graphics Processing Unit (GPU), compared to a single-threaded CPU execution of the sequential algorithm.

Design and Implementation of Hardware to Perform Testing the Matching Packet Header Based on FPGA

The hardware architecture of the parallel process multiple RAM that emulates the behaviors of content addressable memory for packet classification is presents in this paper. With the increase in Internet networks’ speed, the speed of detection of intruders has become a basic requirement. In this work, a packet header field is used in a fast and efficient way to detect intruders to prevent them from accessing the data. The application test results were fast and compatible when used FPGA board technique from xilinx. Finally, the design, synthesis of this parallel process multiple RAM packet header detector has been achieved using Vivado 2018.2 simulator, and coding is written in Verilog HDL language and implemented on Virtex – 7 FPGA (Field Programmable Gate Array) kit.

Optimal Algebraic Breadth-First Search for Sparse Graphs

There has been a rise in the popularity of algebraic methods for graph algorithms given the development of the GraphBLAS library and other sparse matrix methods. An exemplar for these approaches is Breadth-First Search (BFS). The algebraic BFS algorithm is simply a recurrence of matrix-vector multiplications with the n × n adjacency matrix, but the many redundant operations over nonzeros ultimately lead to suboptimal performance. Therefore an optimal algebraic BFS should be of keen interest especially if it is easily integrated with existing matrix methods. Current methods, notably in the GraphBLAS, use a Sparse Matrix masked-Sparse Vector multiplication in which the input vector is kept in a sparse representation in each step of the BFS, and nonzeros in the vector are masked in subsequent steps. This has been an area of recent research in GraphBLAS and other libraries. While in theory, these masking methods are asymptotically optimal on sparse graphs, many add work that leads to suboptimal runtime. We give a new optimal, algebraic BFS for sparse graphs, thus closing a gap in the literature. Our method multiplies progressively smaller submatrices of the adjacency matrix at each step. Let n and m refer to the number of vertices and edges, respectively. On a sparse graph, our method takes O ( n ) algebraic operations as opposed to O ( m ) operations needed by theoretically optimal sparse matrix approaches. Thus, for sparse graphs, it matches the bounds of the best-known sequential algorithm, and on a Parallel Random Access Machine, it is work-optimal. Our result holds for both directed and undirected graphs. Compared to a leading GraphBLAS library, our method achieves up to 24x faster sequential time, and for parallel computation, it can be 17x faster on large graphs and 12x faster on large-diameter graphs.

A parallel naive approach for non-dominated sorting: a theoretical study considering PRAM CREW model

Pareto-based multi-objective evolutionary algorithms use non-dominated sorting as an intermediate step. These algorithms are easy to parallelize as various steps of these algorithms are independent of each other. Researchers have focused on the parallelization of non-dominated sorting in order to reduce the execution time of these algorithms. In this paper, we focus on one of the initial approaches for non-dominated sorting also known as naive approach, proposed by Srinivas et al. and explore the scope of parallelism in this approach. Parallelism is explored in the considered approach in three different ways considering Parallel Random Access Machine, Concurrent Read Exclusive Write model. The time and space complexities of three different parallel versions are also analyzed. Analysis of parallel algorithms is usually carried out under the assumption that an unbounded number of processors are available. Thus, the same assumption has been considered in our analysis too and we have obtained the maximum number of processors required for three parallel versions.

Optimization in Cost of Sorting by CRCW PRAM Model

This paper is aimed at studying and comparing the efficiency gained by various modes of embedding parallelism in the process of enumeration sort which calculates the position of each of the input values and places them accordingly to generate an output array containing the values in sorted order. Each of the parallel algorithms are individually analysed from the perspective of time complexity and the efficiency gained by each over the sequential method. Increase in the level of parallelism leads to decrease in the time demanded in generating output, at the cost of increase in the number of processing units. Time demanded could be minimized by maximizing the number of processing elements, but optimization in the overall cost, product of number of processing elements enrolled and time taken in generating the output, could be achieved at an intermediate level. We illustrate the scenario in which the product, which illustrates the overall cost, is minimized.

Sort Integers into a Linked List

We show that n integers in {0, 1, …, m-1} can be sorted into a linked list in constant time using nlogm processors on the Priority CRCW PRAM model, and they can be sorted into a linked list in O(loglogm/logt) time using nt processors on the Priority CRCW PRAM model.