Parallel Processing Applications Research Articles

An Innovative Topologies Based on Hypercube Network Interconnection

A parallel processing system's most crucial part is a network interconnection that links its processors. The hypercube topology has interesting features that make it a great option for parallel processing applications. This paper presents two innovative configurations of interconnection networks based on fractal Sierpinski and a hypercube. These are called the Sierpinski Triangle Topology (STT) and Sierpinski Carpet Topology (SCT). Compared to a hypercube, the Sierpinski Triangle topology (STT) noticed a significant decrease in the number of nodes and links as large networks grew. Hence, it is considered a great way to reduce costs because it uses fewer nodes and links. The average distance is also shorter, which is better. Despite it having a smaller bisection width and a higher degree than a hypercube by one. The Sierpinski Carpet Topology (SCT) has the advantage of having a high bisection width compared to a hypercube. That is preferable because it places a lower restriction on the difficulty of parallel algorithms. While the drawback of this topology is that it has a diameter and average distance more than a hypercube.

A New Fractal Topologies Based on Hypercube Interconnection Network

A parallel processing system's most crucial part is a network interconnection that links its processors. The hypercube topology has exciting features, making it an excellent option for parallel processing applications. This paper presents two innovative configurations of interconnection networks based on fractal Sierpinski and a hypercube. These are the Sierpinski Triangle Topology (STT) and Sierpinski Carpet Topology (SCT). Compared to a hypercube, the Sierpinski Triangle topology (STT) noticed a significant decrease in the number of nodes and links as large networks grew. Hence, it considers a great way to reduce costs because it uses fewer nodes and links. The average distance is also shorter, which is better. Despite it has a smaller bisection width and a more degree than a hypercube by one. The Sierpinski Carpet Topology (SCT) has the advantage of having a higher bisection width than a hypercube. That is preferable because it places a lower restriction on the difficulty of parallel algorithms. In contrast, the drawback of this topology is that it has a diameter and average distance more than a hypercube.

Achieving new SQL query performance levels through parallel execution in SQL Server

This article provides an in-depth look at implementing parallel SQL query processing using the Microsoft SQL Server database management system. It examines how parallelism can significantly accelerate query execution by leveraging multi-core processors and clustered environments. The article explores SQL Server's sophisticated parallel processing capabilities including automatic query parallelization, intra-query parallelism techniques like parallel joins and parallel data aggregation, as well as inter-query parallelism for concurrent query execution. It covers key considerations around effective parallelization such as managing concurrency and locks, handling data skew, resource governance, and monitoring. Challenges like debugging parallel plans and potential bottlenecks from excessive parallelism are also discussed along with mitigation strategies. Real-world examples demonstrate how judicious application of parallel processing helps optimize complex analytics workloads involving massive datasets. The insights presented provide guidance to database developers and administrators looking to enable parallel SQL query execution in SQL Server environments for substantial performance gains and scalability.

Expandable On-Board Real-Time Edge Computing Architecture for Luojia3 Intelligent Remote Sensing Satellite

Since the data generation rate of high-resolution satellites is increasing rapidly, to relieve the stress of data downloading and processing systems while enhancing the time efficiency of information acquisition, it is important to deploy on-board edge computing on satellites. However, the volume, weight, and computability of on-board systems are strictly limited by the harsh space environment. Therefore, it is very difficult to match the computability and the requirements of diversified intelligent applications. Currently, this problem has become the first challenge of the practical deployment of on-board edge computing. To match the actual requirements of the Luojia3 satellite of Wuhan University, this manuscript proposes a three-level edge computing architecture based on a System-on-Chip (SoC) for low power consumption and expandable on-board processing. First, a transfer level is designed to focus on hardware communications and Input/Output (I/O) works while maintaining a buffer to store image data for upper levels temporarily. Second, a processing framework that contains a series of libraries and Application Programming Interfaces (APIs) is designed for the algorithms to easily build parallel processing applications. Finally, an expandable level contains multiple intelligent remote sensing applications that perform data processing efficiently using base functions, such as instant geographic locating and data picking, stream computing balance model, and heterogeneous parallel processing strategy that are provided by the architecture. It is validated by the performance improvement experiment that following this architecture, using these base functions can help the Region of Interest (ROI) system geometric correction fusion algorithm to be 257.6 times faster than the traditional method that processes scene by scene. In the stream computing balance experiment, relying on this architecture, the time-consuming algorithm ROI stabilization production can maintain stream computing balance under the condition of insufficient computability. We predict that based on this architecture, with the continuous development of device computability, the future requirements of on-board computing could be better matched.

A Study of Cellular Neural Networks with Vertex-Edge Topological Descriptors

The Cellular Neural Network (CNN) has various parallel processing applications, image processing, non-linear processing, geometric maps, high-speed computations. It is an analog paradigm, consists of an array of cells that are interconnected locally. Cells can be arranged in different configurations. Each cell has an input, a state, and an output. The cellular neural network allows cells to communicate with the neighbor cells only. It can be represented graphically; cells will represent by vertices and their interconnections will represent by edges. In chemical graph theory, topological descriptors are used to study graph structure and their biological activities. It is a single value that characterizes the whole graph. In this article, the vertex-edge topological descriptors have been calculated for cellular neural network. Results can be used for cellular neural network of any size. This will enhance the applications of cellular neural network in image processing, solving partial differential equations, analyzing 3D surfaces, sensory-motor organs, and modeling biological vision.

The application of parallel processing in the selection of spectral variables in beer quality control

Parallel data analysis was investigated to improve performance in variable selection and to develop predictive models for beer quality control. A set of spectral near infrared (NIR) data from 60 beer samples and its primitive extracts as the original concentration was used. The dataset was distributed to Raspberry Pi 3 Model B devices connected to a network that was running a Machine Learning service. With more than 4 devices acting in parallel, it was possible to reduce time in 57% to find the best linear regression coefficient (0.999) with the lower RMSECV (0.216) if compared to a singular desktop computer. Thus, parallel processing can significantly reduce the time to indicate the best model fitted during the variable’s selection.

Efficient Algorithm for Providing Live Vulnerability Assessment in Corporate Network Environment

The time gap between public announcement of a vulnerability—its detection and reporting to stakeholders—is an important factor for cybersecurity of corporate networks. A large delay preceding an elimination of a critical vulnerability presents a significant risk to the network security and increases the probability of a sustained damage. Thus, accelerating the process of vulnerability identification and prioritization helps to red the probability of a successful cyberattack. This work introduces a flexible system that collects information about all known vulnerabilities present in the system, gathers data from organizational inventory database, and finally integrates and processes all collected information. Thanks to application of parallel processing and non relational databases, the results of this process are available subject to a negligible delay. The subsequent vulnerability prioritization is performed automatically on the basis of the calculated CVSS 2.0 and 3.1 scores for all scanned assets. The environmental CVSS vector component is evaluated accurately thanks to the fact that the environmental data is imported directly from the organizational inventory database.

Liquid crystal bifocal lens with adjustable intensities through polarization controls.

In this Letter, transverse and longitudinal liquid crystal bifocal lenses (LCBLs) are proposed to continuously control the relative intensity of two foci through a simple polarization control. The modulation of a LCBL comes from the geometric phase control and is designed through the principle of holography, where the object wave is a light field from two foci respectively formed by the left-circular polarized (LCP) and right-circular polarized (RCP) light, and the reference wave is the incident plane wave. Constructed millimeter-scale LCBLs are verified experimentally, and the foci are precisely formed at the preset plane. Besides, the relative intensity can be easily controlled with different weights of LCP and RCP light. The proposed strategy overcomes the shortcomings of previous bifocal lenses, such as a complex design method, a long optimization time, and an unchangeable relative intensity, and it is expected to find potential applications in parallel optical processing and optical interconnections.

Polynomials of Degree-Based Indices for Swapped Networks Modeled by Optical Transpose Interconnection System

The Optical Transpose Interconnection System (OTIS) has applications in parallel processing, distributed processing, routing, and networks. It is used for efficient usage of multiple parallel algorithms or parallel systems, with different global interconnections in a network as it is an optoelectronic (combination of light signals and electronics). In chemical graph theory, topological indices are used to study characteristics of the chemical structures or biological activities. Topological indices are sometimes studied with the assistance to their polynomial. In this article, polynomials of degree-based topological indices for OTIS and swapped networks have been studied. Results can be used to compute any degree-based topological polynomials for OTIS swapped network.

An Efficient Exchanged Hyper Cube for Parallel and Distributed Network

Enormously parallel distribution memory designs are accepting and expanding regard to satisfy the expanding need on processing power. Numerous topologies have been projected for interconnecting the processors of distributed computing systems. The hypercube topology has attracted significant consideration because of a significant number of attractive properties. The engaging properties of the hypercube topology, for example, vertex and edge balance, recursive structure, logarithmic diameter, maximally fault-tolerance, simple routing and broadcasting, and the capacity to recreate other interconnection systems with least overhead have made it a brilliant possibility for some parallel processing applications. Numerous varieties of the hypercube topology have been accounted for the literature, mostly to add the computational power of the hypercube. One of the gorgeous versions of the hypercube was introduced for the improvement of the presented Exchanged hypercube. An Exchanged hypercube has the equivalent structural complexities of the hypercube. It protects the gorgeous properties of the hypercube and diameter the communication time by dropping the diameter by a factor of two. This paper presents the fundamental communication and some of the essential operations normally required in parallel computing on the Exchanged hypercube interconnection networks.

A Proficient Performance Scrutiny of King Mesh Topology based on the Routing Algorithms

Network on Chip (NoC), is an associate degree approach to construct the interaction between subsystems. The number of cores in a System on Chip (SoC) increases gradually in the pre-decades and affect the system performance. The scalability of SoC is improved by NoC architectures where topology contains an important impact on the performance and cost of the network. Mesh, Torus is some of the topologies used in NoC system design. King mesh topology is the concept introduced to improve the performance of the NoC system. King topology introduces some new advancement in the performance of mesh and torus topology. The king mesh topology provides number of advantages such as reduced execution time in parallel processing applications. In king mesh topology the transmission latency of long distance traffic is high. The proposed XY routing and Weight based Path Selection (WPS) routing techniques increases the speed of the system, reduce the area utilization and power consumption and reduce the number of hop counts by finding the shortest path.

New Performance Modeling Methods for Parallel Data Processing Applications

Predicting the performance of an application running on parallel computing platforms is increasingly becoming important because of its influence on development time and resource management. However, predicting the performance with respect to parallel processes is complex for iterative and multi-stage applications. This research proposes a performance approximation approach FiM to predict the calculation time with FiM-Cal and communication time with FiM-Com of an application running on a distributed framework. FiM-Cal consists of two key components that are coupled with each other: (1) a Stochastic Markov Model to capture non-deterministic runtime that often depends on parallel resources, e.g., number of processes, and (2) a machine-learning model that extrapolates the parameters for calibrating our Markov model when we have changes in application parameters such as dataset. Along with the parallel calculation time, parallel computing platforms consume some data transfer time to communicate among different nodes. FiM-Com consists of a simulation queuing model to quickly estimate communication time. Our new modeling approach considers different design choices along multiple dimensions, namely (i) process-level parallelism, (ii) distribution of cores on multi-processor platform, (iii) application related parameters, and (iv) characteristics of datasets. The major contribution of our prediction approach is that FiM can provide an accurate prediction of parallel processing time for the datasets that have a much larger size than that of the training datasets. We evaluate our approach with NAS Parallel Benchmarks and real iterative data processing applications. We compare the predicted results (e.g., end-to-end execution time) with actual experimental measurements on a real distributed platform. We also compare our work with an existing prediction technique based on machine learning. We rank the number of processes according to the actual and predicted results from FiM and calculate the correlation between the actual and predicted rankings. Our results show that FiM obtains a high correlation in the range of 0.80 to 0.99, which indicates considerable accuracy of our technique. Such prediction provides data analysts a useful insight of optimal configuration of parallel resources (e.g., number of processes and number of cores) and also helps system designers to investigate the impact of changes in application parameters on system performance.

Enhanced SPIHT Algorithm with Pipelined Datapath Architecture Design

DOI : 10.26650/electrica.2018.15101 Set partitioning in hierarchical trees (SPIHT) is an efficient algorithm which is used for the image compression widely. SPIHT operates sequentially so, its parallel implementation is difficult. In this study, the SPIHT algorithm is improved for providing that it is suitable for the parallel processing applications, and the corresponding pipelined datapath is designed for the proposed enhanced SPIHT algorithm. The datapath is designed to have three stages as preprocessing, list generation and output stream. In the preprocessing stage, the flags which are supports the list generation stage are constituted. List of insignificant sets (LIS), list of insignificant pixels (LIP) and list of significant pixels (LSP) are formed in list generation stage. These lists contain the bit values which generate the output bit stream. The performance of the improved datapath design has been tested by compressing different images, and the obtained results are given. Cite this article as: Cekli S, Akman A. Enhanced SPIHT Algorithm with Pipelined Datapath Architecture Design. Electrica, 2019; 19(1): 29-36.

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 μm2 for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.

A high-performance and energy-efficient exhaustive key search approach via GPU on DES-like cryptosystems

Recently, graphical processing units (GPUs) have found a prominent role in general-purpose applications. Specifically, in parallel processing applications where a considerable number of tasks should be processed while meeting specific design constraints. One of the most interesting subjects in this area is cipher breaking via brute-force attacks, which attracts the attention of many researchers to the field. In this paper, we introduce a novel exhaustive key search approach for block cipher cryptosystems. The key point is how to utilize the single instruction multiple thread architecture to improve the speed of the DES-like hardware-based cryptosystems. At first, the standard DES core is implemented while all operations like bit permutation, swapping, and general hardware data stream follow the original algorithm. Then, in order to maximize the usage of the memory bandwidth and to eliminate the bit access penalty in GPU architecture, we exploit the register permutation and swapping (instead of the conventional bit swapping) in our implementation. In this approach, each thread examines a set of 32 keys per each iteration and hence a considerable throughput is achieved. The experimental results demonstrate 24K $$\times $$ , 800 $$\times $$ , and 400 $$\times $$ speed up over the traditional DES implementation on single-core CPU, the best previous work on multi-core CPU, and the conventional implementation on GPU, respectively. Furthermore, we measure the power and energy consumption of the best GPU and CPU approaches, where the GPU implementation proves to be more power efficient.

Effects of Multicore Distributed Memory Systems on Parallel Processing Applications

Complex problems need a longtime to be solved, with low efficiency and performance. Hence, to overcome these drawbacks, the approach of breaking the problem into independent parts and treating each part individually in the way that each processing element can execute its part of the problem simultaneously with the others. The systems that contain many computing elements combined. Parallel processing (PP) is divided into three types; shared, distributed, and hybrid memory systems are usually adopted. The aim of this research is to point out the effects of multicore distributed memory systems on PP applications that can reduce the total execution time of the programs. In this work, distributed- and shared-memory systems addressed depends on client/servers principles. However, to get the exact evaluation of our aim, just one client and one server have been depended. The algorithm used here is capable of calculating: The started, consumed, and terminated for CPU and total execution times, CPU usage of servers, and CPU and Total execution times for the client. The results compared with previous works depending on distributed memory systems, to overcome the previous drawbacks taking in the consideration the effects of multi-core processor. All of these algorithms are implemented using Java Language.

Parallel processing via carbon field emission-based controlled-switching of regular bijective nano systolic networks, Part II

Purpose The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced. Design/methodology/approach The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented. Findings Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented. Practical implications The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications. Originality/value The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.

Diagnosable evaluation of enhanced optical transpose interconnection system networks

The process of identifying faulty processors is called diagnosis of the system. Several models of diagnosis have been proposed, the most popular being the PMC (Preparata, Metze and Chien) diagnostic model proposed by Preparata et al. in 1967. The precise strategy correctly identifies all faulty processors while the pessimistic strategy isolates all faulty processors within a set containing at most one fault-free processor. For a multiprocessor system, diagnosability is critical to measure its performance. The enhanced optical transpose interconnection system (enhanced OTIS), network has important applications in parallel processing. In this network architecture, n2 processors are divided into n groups of n processors; processors in the same group are connected by electronic links while the groups are simultaneously connected by optical links. An enhanced OTIS network is regular if its base graph G is regular. In this paper, we discuss fault diagnosis in an enhanced OTIS network, including both the precise strategy and pessimistic strategy under the PMC diagnostic model.

Parallel processing via carbon field emission-based controlled switching of regular bijective nano systolic networks, part 1: basics

Purpose The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and the corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding m-ary (many-valued) extensions for the use in nano systolic networks are introduced. The first part of the paper presents important fundamentals with regards to systolic computing and carbon-based field emission that will be utilized in the implementations within the second part of the paper. Design/methodology/approach The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented. Findings Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented. Originality/value The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power very-large-scale-integration circuit design for signal processing applications.

Parallel Bijective Processing of Regular Nano Systolic Grids via Carbon Field Emission Controlled - Switching

New implementations for parallel processing applications using reversible systolic networks and the corresponding nano and field-emission controlled-switching components is introduced. The extensions of implementations to many-valued field-emission systolic networks using the introduced reversible systolic architectures are also presented. The developed implementations are performed in the reversible domain to perform the required parallel computing. The introduced systolic systems utilize recent findings in field emission and nano applications to implement the function of the basic reversible systolic network using nano controlled-switching. This includes many-valued systolic computing via carbon nanotubes and carbon field-emission techniques. The presented realization of reversible circuits can be important for several reasons including the reduction of power consumption, which is an important specification for the system design in several future and emerging technologies, and also achieving high performance realizations. The introduced implementations for non-classical systolic computation are new and interesting for the design within modern technologies that require optimal design specifications of high speed, minimum power and minimum size, which includes applications in adiabatic low-power signal processing .