Parallel Prefix Network Research Articles

Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1},2^{n}+2^{n-1}-1,2^{n+1}-1\}$

Residue number systems (RNS) are characterized by fast modular arithmetic and low power dissipation. Numerous RNS applications take advantage of moduli set ${\tau }=\{{2}^{{{n}}}{-1,}{2}^{{{n}}},\,\,2^{{{n}}}+1\}$ , with nearly ${2}^{3n}$ dynamic range and fast parallel-prefix adders. However, the ${2}^{{{n}}}+1$ channel is ${4}{\Delta }{{G}}$ slower ( ${\Delta }{{G}} =$ simple 2-input gate delay). To remedy such speed imbalance and accommodate higher dynamic ranges, other moduli forms have joined $\{{2}^{{{n}}},{2}^{{{n}}}-1\}$ , with only slightly slower adders (e.g., ${2}^{{{n}+1}}{-1} (n={2}^{{\text {h}}}){,}{2}^{{{n}}}{-}{2}^{q}{-1({q} , and ${2}^{{{n}}}{-3}$ , with at most ${2\Delta {G}}$ more parallel-prefix delay). However, the more the number of moduli, the harder and more costly becomes the required reverse convertor, while otherwise increasing the channel widths ${n}$ may incur some speed loss. Nevertheless, in the present work, the 3-moduli set ${\tau }^{+}=\{{2}^{{{n}+1}}{,}{2}^{{{n}}}{+}{2}^{n-1}{-1,} {2}^{{{n}+1}}{-1}\}$ is presented, with almost $6\times $ dynamic range than that of the aforementioned $\tau $ , where the corresponding parallel-prefix adders are as fast as those for the ${2}^{{{n}}}$ and ${2}^{{{n}}}{-1}$ channels. The required nontrivial forward convertor for modulo ${2}^{{{n}}}+{2}^{{{n}-1}}{-1}$ and the reverse convertor for the new 3-moduli set are also designed. Moreover, a new 3-input parallel-prefix node is designed and incorporated, as appropriate for ${n}= 2^{\text {h}}$ , within the employed parallel-prefix networks with the overall advantage of $2\Delta {G}$ speed-up. Improvements of proposed designs are confirmed via circuit synthesis.

Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders

In this paper, hybrid parallel-prefix/carry select and skip adder (PPF/CSSA) schemes are proposed for high-speed wide-size adders. The proposed adders are based on an improved design of the parallel-prefix network and carry select (CSL) blocks. In this design, the delays of the two parts are balanced and matched. The proposed method cuts the carry chain in the CSL block and separates the block into two sub-blocks, in which the carry-in signals of the second sub-blocks are connected directly with the PPF signals to reduce the critical path. The proposed adders are evaluated at 45 nm technology and compared with previous designs. The proposed designs reduce the delay and power-delay product (PDP) by up to 29% and 33%, respectively, compared to previous designs.

ENGLISH

Arithmetic and memory address computation are performed using adder operations. Hence, design of adders forms an important subset of electronic chip design functionality. BCD numbers play a prominent role in number system. To perform arithmetic operations on BCD numbers respective circuit has to be designed. To perform BCD addition, BCD adders are used. But the drawback with the BCD adder is low speed in operation due to delay in propagating carry output. This low speed operation will affect the operation of entire system in which it is used. As the technology is advancing day by day there is demand for chips with high speed. So to overcome this drawback, BCD adder using CLA is proposed in this paper. The proposed design is attempted here to reduce the delay and thereby increasing the speed of response. In existing BCD architecture, RCA is used to add numbers. The delay of RCA is high so it is effecting the speed of adder. So in the proposed design, CLA is used instead of RCA and also a parallel prefix network is to be used to produce the carry outputs for all stages. In this paper, a BCD adder using CLA is to be designed for 8, 16, 32, 64 and 128-bit size using VHDL with the help of ISE Xilinx design suite 14.1. The designed adder will be functionally verified by using ISIM simulator. Later, it will be synthesized using XST synthesizer to get the area (in terms of LUTS) and delay(ns). Finally, the designed BCD adders will be compared with conventional BCD adder in terms of delay(ns).

Fast parallel prefix logic circuits for n2n round-robin arbitration

An n2n round-robin arbiter (RRA) searches its n inputs for a 1, starting from the highest-priority input. It picks the first 1 and outputs its index in one-hot encoding. RRA aims to be fair to its inputs and maintains fairness by simply rotating the input priorities, i.e., the last arbitrated input becomes the lowest-priority input. Arbiters are used to multiplex the usage of shared resources among requestors as well as in dispatch logic where the purpose is load balancing among multiple resources. Today, arbiters have hundreds of ports and usually need to run at very high clock speeds. This article presents a new gate-level RRA circuit called Thermo Coded-Parallel Prefix Arbiter (TC-PPA) that scales to any number of requestors. It uses parallel prefix network topologies (borrowed from fast carry lookahead adders) to generate a thermometer-coded pointer, thus greatly reducing critical path. Code generators were written not only for TC-PPA but also for the 5 highly competitive circuits in the literature (9 including their variants), and a rich set of timing/area results were obtained using a standard-cell based logic synthesis flow with a novel iterative strategy based on binary search. Synthesis runs include results with wire-load and without. Results show that for 54 or more ports (except 256) TC-PPA offers the best timing (lowest latency) as well as competitive area. Contributions also include transaction-level simulations that show when pipelining is used to boost clock rate, latency and input FIFO sizes are adversely affected, and hence pipelining cannot be indiscriminately exploited to trim clock period. Graphical abstract [Display omitted] Highlights► Thermo Coded-Parallel Prefix Arbiter (TC-PPA) circuit topologies are proposed. ► TC-PPA offers the fastest Round-Robin Arbiter circuit for 54 ports or more. ► TC-PPA owes its speed in part to Parallel Prefix networks found in fast adders. ► Verilog generators were written and synthesis was run for 13 circuit topologies. ► Results with up to 512 ports, wire-load model, and pipelining are included.

Functional and dynamic programming in the design of parallel prefix networks

AbstractA parallel prefix network of width n takes n inputs, a1, a2, . . ., an, and computes each yi = a1 ○ a2 ○ ⋅ ⋅ ⋅ ○ ai for 1 ≤ i ≤ n, for an associative operator ○. This is one of the fundamental problems in computer science, because it gives insight into how parallel computation can be used to solve an apparently sequential problem. As parallel programming becomes the dominant programming paradigm, parallel prefix or scan is proving to be a very important building block of parallel algorithms and applications. There are many different parallel prefix networks, with different properties such as number of operators, depth and allowed fanout from the operators. In this paper, ideas from functional programming are combined with search to enable a deep exploration of parallel prefix network design. Networks that improve on the best known previous results are generated. It is argued that precise modelling in a functional programming language, together with simple visualization of the networks, gives a new, more experimental, approach to parallel prefix network design, improving on the manual techniques typically employed in the literature. The programming idiom that marries search with higher order functions may well have wider application than the network generation described here.

Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system

In this paper, a new model based on an improved Brent Kung (BK) parallel prefix network (PPN) algorithm is proposed and realized in the field programmable gate array (FPGA). This model is employed in the implementation of 20 Gb/s differential quadrature phase-shift keying (DQPSK) precoder in 40 Gb/s polarization division multiplex (PolDM) DQPSK system. In the computation process, the computation complexity (area) optimization with fan-out limited is achieved. In the implementation, 770 FPGA slice registers are utilized, which save about 60% logic resources compared with the previous Kogge Stone (KS) algorithm.