Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders

Abstract

In this paper, hybrid parallel-prefix/carry select and skip adder (PPF/CSSA) schemes are proposed for high-speed wide-size adders. The proposed adders are based on an improved design of the parallel-prefix network and carry select (CSL) blocks. In this design, the delays of the two parts are balanced and matched. The proposed method cuts the carry chain in the CSL block and separates the block into two sub-blocks, in which the carry-in signals of the second sub-blocks are connected directly with the PPF signals to reduce the critical path. The proposed adders are evaluated at 45 nm technology and compared with previous designs. The proposed designs reduce the delay and power-delay product (PDP) by up to 29% and 33%, respectively, compared to previous designs.