Parallel Multicore Architectures Research Articles

Factorization of Boolean Polynomials: Parallel Algorithms and Experimental Evaluation

Polynomial factorization is a classical algorithmic algebra problem with a wide range of applications. Of particular interest is factorization over finite fields, among which fields of order two are probably the most important ones when representing Boolean functions by Zhegalkin polynomials. In particular, factorization of Boolean polynomials corresponds to conjunctive decomposition of Boolean functions given in algebraic normal form. In addition, factorization enables decomposition of functions given in full disjunctive normal form (DNF) and positive DNF, as well as Cartesian decomposition of relational data. These applications demonstrate the importance of developing fast factorization algorithms. In this paper, we consider some recently proposed factorization algorithms of polynomial complexity and describe a parallel MIMD implementation that takes advantage of both task-level and data-level parallelism. We conduct some experiments on logic synthesis benchmarks and synthetic (random) polynomials to demonstrate significant factorization speedup. In conclusion, we discuss results of testing a parallel implementation of the algorithm on a massively parallel multicore architecture (REDEFINE).

A Multi-Core Approach to Efficiently Mining High-Utility Itemsets in Dynamic Profit Databases

Analyzing customer transactions to discover high-utility itemsets is a popular task, which consists of finding the sets of items that are purchased together and yield a high profit. However, many studies assume that transactional data is static while in real-life, it changes over time. For example, the unit profits of items may vary from one week to another because sale prices and production costs may change. Many algorithms for mining high-utility itemsets (HUI) ignore this important property and thus are inapplicable or generate inaccurate results on real data. To address this issue, this paper proposes a novel algorithm named Multi-Core HUI Miner (MCH-Miner). It adapts techniques introduced in the iMEFIM algorithm to run on a parallel multi-core architecture to efficiently mine HUIs in dynamic transaction databases. An empirical evaluation shows that in most cases, MCH-Miner is significantly faster than iMEFIM, and that the cost of database scans is reduced.

Comparison of multihardware parallel implementations for a phase unwrapping algorithm

Phase unwrapping is an important problem in the areas of optical metrology, synthetic aperture radar (SAR) image analysis, and magnetic resonance imaging (MRI) analysis. These images are becoming larger in size and, particularly, the availability and need for processing of SAR and MRI data have increased significantly with the acquisition of remote sensing data and the popularization of magnetic resonators in clinical diagnosis. Therefore, it is important to develop faster and accurate phase unwrapping algorithms. We propose a parallel multigrid algorithm of a phase unwrapping method named accumulation of residual maps, which builds on a serial algorithm that consists of the minimization of a cost function; minimization achieved by means of a serial Gauss–Seidel kind algorithm. Our algorithm also optimizes the original cost function, but unlike the original work, our algorithm is a parallel Jacobi class with alternated minimizations. This strategy is known as the chessboard type, where red pixels can be updated in parallel at same iteration since they are independent. Similarly, black pixels can be updated in parallel in an alternating iteration. We present parallel implementations of our algorithm for different parallel multicore architecture such as CPU-multicore, Xeon Phi coprocessor, and Nvidia graphics processing unit. In all the cases, we obtain a superior performance of our parallel algorithm when compared with the original serial version. In addition, we present a detailed comparative performance of the developed parallel versions.

Parallel reachability analysis of hybrid systems in XSpeed

Reachability analysis techniques are at the core of the current state-of-the-art technology for verifying safety properties of cyber-physical systems (CPS). The current limitation of such techniques is their inability to scale their analysis by exploiting the powerful parallel multi-core architectures now available in modern CPUs. Here, we address this limitation by presenting for the first time a suite of parallel state-space exploration algorithms that, leveraging multi-core CPUs, enable to scale the reachability analysis for linear continuous and hybrid automaton models of CPS. To demonstrate the achieved performance speedup on multi-core processors, we provide an empirical evaluation of the proposed parallel algorithms on several benchmarks comparing their key performance indicators. This enables also to identify which is the ideal algorithm and the parameters to choose that would maximize the performances for a given benchmark.

Real-time scheduling algorithm for safety-critical systems on faulty multicore environments

An algorithm (called FTM) for scheduling of real-time sporadic tasks on a multicore platform is proposed. Each task has a deadline by which it must complete its non-erroneous execution. The FTM algorithm executes backups in order to recover from errors caused by non-permanent and permanent hardware faults. The worst-case schedulability analysis of FTM algorithm is presented considering an application-level error model, which is independent of the stochastic behavior of the underlying hardware-level fault model. Then, the stochastic behavior of hardware-level fault model is plugged in to the analysis to derive the probability of meeting all the deadlines. Such probabilistic guarantee is the level of assurance (i.e., reliability) regarding the correct functional and timing behaviors of the system. One of the salient features of FTM algorithm is that it executes some backups in active redundancy to exploit the parallel multicore architecture while other backups passively to avoid unnecessary execution of too many active backups. This paper also proposes a scheme to determine for each task the number of backups that should run in active redundancy in order to increase the probability of meeting all the deadlines. The effectiveness of the proposed approach is demonstrated using an example application.

A tale of two technology disruptions

With power dissipation severely limiting the frequency scaling of microprocessors, the emergence of chip multiprocessors (CMPs) had shifted computingto embrace highly parallel multicore architectures. Realizing performance in these newgenerations of chips is becoming increasingly dependent on how efficiently applications can exploit the growing number of parallel resources. Whereas computation power as measured in FLOPs was the key metric of past microprocessors, performance in today?s CMPs is dominated by data movement challenges. In this so-called ``communications bound?? era of computing, new technologies are sought that can deliver energy-efficient high-bandwidth interconnectivity. While optics is a natural communications technology with broad success in long-haul fiber optic telecommunications, integration at the chip scale, particularly with silicon, had been challenging.

Pairwise verlet lists: Combining cell lists and verlet lists to improve memory locality and parallelism

Verlet lists, which are commonly used in many particle-based simulations, are not suited for modern, shared-memory parallel multicore architectures. In this article, we introduce pairwise Verlet lists: local Verlet lists containing only interacting particle pairs between a pair of neighboring computational cells. We show that these pairwise Verlet lists are more efficient and scale much better than the traditional global Verlet list, both on a single processor as well as on multiple shared-memory cores. The improved performance on a single core makes them an interesting option for distributed-memory simulations as well.

Special issue (part II) on parallel computing for real-time image processing

The performance requirements of image processing applications have continuously increased, especially when they are executed under real-time constraints. We have organized this special issue on Parallel Computing for Real-Time Image Processing to present the current state-of-the-art in the field of parallel programming and the future trends in real-time image and video processing as related to parallel computing or real-time implementation of embedded image processing applications on parallel architectures including multi-core platforms, GPUs and dedicated parallel architectures based upon FPGAs. Due to the overwhelming number and their wide scope of submissions received for this special issue and thus the difficulty associated with finding expert reviewers, it was decided to offer this special issue in three parts. We are very grateful to the reviewers who provided valuable comments and suggestions to improve the quality of the accepted papers. This third part of this special issue on Parallel Computing for Real-Time Image Processing presents five papers addressing different parallel applications including 2D wavelet transform, tone mapping, object recognition, face tracking and dynamic video applications. The realtime implementation of these applications uses GPU, parallel multi-core architecture and dedicated architecture based upon FPGA. Brief outlines of these papers are stated below: The first paper by Franco et al. presents a GPU implementation of the 2D Fast Wavelet Transform, based on a pair of Quadrature Mirror Filters. It also investigates hardware improvements including multicores on the CPU side, and exploits them at thread-level parallelism using OpenMP and Pthreads. Overall, the GPU exhibits better scalability and parallel performance on large-scale images to become a solid alternative for computing the 2D-FWT versus those thread-level methods run on emerging multicore architectures. The second paper by Liu et al. proposes a multi-cue-based face tracking algorithm with the supporting framework using parallel multi-core and one graphic processing unit (GPU). This paper explores two parallel computing techniques to speed up the racking process, especially the most computation-intensive observational steps. One is a multi-core-based parallel algorithm with a Map-Reduce thread model, and the other is a GPU-based speedup approach. The GPU-based technique uses features-matching and particle weight computations, which have been put into the GPU kernel. The results demonstrate that the proposed face tracking algorithm can work robustly with cluttered backgrounds and differing illuminations; the multi-core parallel scheme can increase the speed by 2–6 times compared with that of the corresponding sequential algorithms. Furthermore, a GPU parallel scheme and co-processing scheme can achieve a greater increase in speed (8x–12x) compared with the corresponding sequential algorithms. The third paper by Akil et al. presents the parallel implementation on a GPU of a Real-Time Dynamic Tone Mapping Operator. It describes a generic operator that may be used by any application. However, the goal of this work is to integrate this operator into the graphic rendering process of a car driving simulator, based on its real-time implementation. The tone mapping operator outputs a low M. Akil (&) L. Perroton Universite Paris-Est, LIGM, Equipe A3SI, ESIEE Paris Cite Descartes, BP 99, 93162 Noisy-le-Grand Cedex, France e-mail: m.akil@esiee.fr

Heterogeneous Multicore Parallel Programming for Graphics Processing Units

Hybrid parallel multicore architectures based on graphics processing units (GPUs) can provide tremendous computing power. Current NVIDIA and AMD Graphics Product Group hardware display a peak performance of hundreds of gigaflops. However, exploiting GPUs from existing applications is a difficult task that requires non-portable rewriting of the code. In this paper, we present HMPP, a Heterogeneous Multicore Parallel Programming workbench with compilers, developed by CAPS entreprise, that allows the integration of heterogeneous hardware accelerators in a unintrusive manner while preserving the legacy code.