Memory Parallel Architectures Research Articles

Parallelizing with BDSC, a resource-constrained scheduling algorithm for shared and distributed memory systems

BDSC schedules parallel programs in the presence of resource constraints.BDSC-based parallelization relies on static program analyses for cost modeling.BDSC-based parallelization yields significant speedups on parallel architectures. We introduce a new parallelization framework for scientific computing based on BDSC, an efficient automatic scheduling algorithm for parallel programs in the presence of resource constraints on the number of processors and their local memory size. BDSC extends Yang and Gerasoulis's Dominant Sequence Clustering (DSC) algorithm; it uses sophisticated cost models and addresses both shared and distributed parallel memory architectures. We describe BDSC, its integration within the PIPS compiler infrastructure and its application to the parallelization of four well-known scientific applications: Harris, ABF, equake and IS. Our experiments suggest that BDSC's focus on efficient resource management leads to significant parallelization speedups on both shared and distributed memory systems, improving upon DSC results, as shown by the comparison of the sequential and parallelized versions of these four applications running on both OpenMP and MPI frameworks.

A parallel memory architecture for video coding

To efficiently exploit the performance of single instruction multiple data (SIMD) architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements (8-bit and 16-bit data types) or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-μm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor (VSP). The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.

Introduction to the Special Issue on SAMOS 2007

This special issue includes a selection of the best papers from the 2007 SAMOS VII Symposium. The International Symposium on Embedded Computer Systems, Architectures, Modeling and Simulation (SAMOS) is an event which annually takes place on the scenic Mediterranean island of Samos. It comprises two co-located events—the International SAMOS Conference and the SAMOS Workshop. In 2007 more than 200 papers were submitted for these two events. After a very competitive selection process only about 30% of these papers have been selected for presentation. According to the Symposium’s ranked results and the results of a second stage review process of all presentations from SAMOS, the following eight papers related to architectures and implementations of embedded systems have been selected for publication in this special issue. We would like to thank all reviewers of the SAMOS Workshop and particularly all reviewers of this special issue for their detailed and intensive review work. The investment of their time and insight is very much appreciated and helped to generate this selection of high quality technical papers. The important field of Digital Signal Processor Architectures which is classically one of the focus topics of SAMOS is covered in this special issue by three papers: Thuresson et al. present a paper which is entitled “FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.” Within this paper the authors present a highly efficient DSP architecture and discuss specific elements of this architecture including fine-grained control and a flexible interconnect which lead to significant speedups and significant energy savings. They elaborated on their flexible interconnect that allows the datapath to be dynamically reconfigured as a consequence of code generation. Additionally, the FlexCore provides specialized datapath units to be inserted and utilized within the same architecture and compilation framework. The problem of memory bottlenecks in modern DSP architectures is addressed by the paper of Pitkaenen et al. which is entitled “Parallel Memory Architecture for Application-Specific Instruction-Set Processors.” In this paper, a conflict resolving parallel data memory system for application-specific instruction-set processors is described. The memory structure is generic and reusable to support various application-specific designs. The proposed parallel memory system is attached to an ASIP core and comparisons on area, power, and critical path are presented. Significant power savings can be obtained by exploiting their parallel memory system instead of multi-port memories. Memory access problems are also addressed in the paper of Galuzzi et al. In “High-bandwidth Address Generation Unit” they present an efficient data fetch circuit to retrieve several operands from an n-way interleaved memory system in a single machine cycle. The proposed address generation unit operates with an improved version of a low-order interleaved memory access approach. The presented design supports data structures of arbitrary lengths and various odd strides. J Sign Process Syst (2009) 57:1–3 DOI 10.1007/s11265-008-0220-8

A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms

This paper proposes an efficient parallel memory system for algorithms applied in fixed and variable block-size motion estimation (VBSME). The proposed system is implemented by a novel combination of two parallel memory architectures. The distribution of data among the memory modules is modified over contemporary approaches and the optimized address computation unit enables a rapid address generation for accessed memory locations. Furthermore, the introduced data permutation scheme organizes data efficiently for storage and retrieval. The proposed system enables up to 4 X speedup in data storage and retrieves data up to 55% faster for VBSME compared with the reference implementations. With a 0.18- mum CMOS technology, the proposed memory addressing and data permutation scheme can be clocked at 980 MHz operating frequency with a cost of less than 6 kgates. On FPGA, the system can operate at 200 MHz with less than 700 logic elements. The results show that the proposed system is applicable to real-time VBSME at HDTV resolution.

A Line-Based Parallel Memory for QCA Implementation

Quantum-dot cellular automata (QCA) has been widely advocated as a new device architecture for nanotechnology. Using QCA, the innovative design of digital systems can be achieved by exploiting the so-called capability of processing-in-wire, i.e., signal manipulation proceeds at the same time as propagation. QCA systems require low power together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the in-wire paradigm can be exploited for storage purposes. This paper proposes a novel parallel memory architecture for QCA implementation. This architecture is based on storing information on a QCA line by changing the direction of signal flow among three clocking zones. Timing of these zones requires two additional clocks to implement a four-step process for reading/writing data to the memory. Its operation has been verified by simulation. It is shown that the requirements for clocking, number of zones, as well as the underlying CMOS circuitry are significantly reduced compared with previous QCA parallel architectures.

On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.

Memory binding for performance optimization of control-flow intensive behavioral descriptions

This paper presents a memory binding algorithm for behaviors, used in application-specific integrated circuits (ASICs), that are characterized by the presence of conditionals and deeply nested loops that access memory extensively through arrays. Unlike previous works, this algorithm examines the effects of branch probabilities and allocation constraints. First, we demonstrate, through examples, the importance of incorporating branch probabilities and allocation constraint information when searching for a performance-efficient memory binding. We also show the interdependence of these two factors and how varying one without considering the other may greatly affect the performance of the behavior. Second, we introduce a memory binding algorithm that has the ability to examine numerous bindings by employing an efficient performance estimation procedure. The estimation procedure exploits locality of execution, which is an inherent characteristic of target behaviors. This enables the performance estimation technique to look at the global impact of the different bindings, given the allocation constraints. We tested our algorithm using a number of benchmarks from the parallel computing domain. A series of experiments demonstrates the algorithm's ability to produce bindings that optimize performance, meet memory allocation constraints, and adapt to different resource constraints and branch probabilities. One limitation of our algorithm is that, in its current form, it is not well suited for system-on-a-chip synthesis where there is complex communication between general-purpose microprocessors that use custom-designed arrays. Results show that the algorithm requires 41% fewer memories with a performance loss of only 0.2% when compared to a parallel memory architecture. When compared to the best of a series of random memory bindings, the algorithm improves schedule performance by 22%.

Scalable Parallel Memory Architectures for Video Coding

Current video compression standards, which process frames macroblock by macroblock, employ several processing functions to achieve the compression. These functions refer to data memory address space in different ways. E.g., performing motion estimation and motion compensation functions requires many times data accesses unaligned to word boundaries. On the other hand, Discrete Cosine Transformation (DCT) and inverse of it (IDCT) for 8 × 8 block can be performed first for rows and then for columns. Thus, transposition is needed between these two stages. Among other things, parallel memory architecture can provide a solution for these tasks. In our other paper, we shortly surveyed parallel memory architectures and proposed parallel memory architecture designs for different data path widths for video coding applications. In this paper, we construct video coding function examples by using the proposed parallel data memory efficiently. Furthermore, performance and implementation cost of the parallel memory architecture are estimated and compared to more conventional memory architectures. The examples are given for different data bus widths (16, 32, 64, and 128 bits). We show that the parallel memory can keep the data path fully utilized in many video coding function implementations. This ensures high-speed operation and full utilization of the processing resources.

Configurable parallel memory architecture for multimedia computers

This paper presents a novel parallel memory architecture for multimedia computers. Applying a configurable or programmable addressing circuitry capable of parallel memory accesses, the memory management of multimedia applications can be enhanced. Necessary computer architecture changes to virtual address representation, paging, virtual memory, address computation circuitry and data permutation are discussed. These changes allow the memory to be partitioned for different access functions. In addition, the same memory area can be accessed by multiple access patterns. Therefore, a general-purpose computing system that is capable of exploiting the repeating memory access patterns in its applications can be built. Performance of the configurable parallel memory architecture (CPMA) is analyzed in the case of a selection of algorithms from a video encoder. These motion estimation algorithms and zigzag scanning benefit from the multiple memory access functions, which is apparent from the comparisons to the traditional sequential memory accesses.

BLOCK PARTITIONING IN THE PARALLEL RECURSIVE DECOUPLING METHOD

ABSTRACT New 3 × 3 and 4 × 4 block partitioning techniques are presented for the Recursive Decoupling Method and tested on a set of tridiagonal linear systems. A comparison with the original 2 × 2 partitioning method [ 1], for accuracy, numerical stability and parallel performance, is also considered. All tests have been carried out on parallel shared memory architecture, such as the Sequent Balance8000 multiprocessor and the CRAY Y-MP parallel/ Vector supercomputer.

Analytical estimation of vector access performance in parallel memory architectures

A limiting factor in high-performance vector computers is the rate at which data can be moved to and from memory during vector loads and stores. To increase the bandwidth of vector memory operations, several investigators have proposed the use of noninterleaved storage mappings, also known as storage schemes. A method of analyzing the performance of vector references for the class of storage schemes referred to as XOR schemes is described. The proposed measure of relative performance, the variability of an access, is defined and its computation is outlined. The use of variability as a performance indicator is demonstrated and compared with performance measurements made using simulation. One of the key aspects of the variability measure is its capability to lend insight to the transient behavior of vector accesses.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>