Memory Parallel Research Articles

Frequency- and Power-Dependent Photoresponse of a Perovskite Photodetector Down to the Single-Photon Level.

Organometallic halide perovskites attract strong interests for their high photoresponsivity and solar cell efficiency. However, there was no systematic study of their power- and frequency-dependent photoresponsivity. We identified two different power-dependent photoresponse types in methylammonium lead iodide perovskite (MAPbI3) photodetectors. In the first type, the photoresponse remains constant from 5 Hz to 800 MHz. In the second type, absorption of a single photon can generate a persistent photoconductivity of 30 pA under an applied electric field of 2.5 × 104 V/cm. Additional absorbed photons, up to 8, linearly increase the persistent photoconductivity, which saturates with the absorption of more than 10 photons. This is different than single-photon avalanche detectors (SPADs) because the single-photon response is persistent as long as the device is under bias, providing unique opportunities for novel electronic and photonic devices such as analogue memories for neuromorphic computing. We propose an avalanche-like process for iodine ions and estimate that absorption of a single 0.38 aJ photon triggers the motion of 108-9 ions, resulting in accumulations of ions and charged vacancies at the MAPbI3/electrode interfaces to cause the band bending and change of electric material properties. We have made the first observation that single-digit photon absorption can alter the macroscopic electric and optoelectronic properties of a perovskite thin film.

Electrolyte-gated transistors for synaptic electronics, neuromorphic computing, and adaptable biointerfacing

Functional emulation of biological synapses using electronic devices is regarded as the first step toward neuromorphic engineering and artificial neural networks (ANNs). Electrolyte-gated transistors (EGTs) are mixed ionic–electronic conductivity devices capable of efficient gate-channel capacitance coupling, biocompatibility, and flexible architectures. Electrolyte gating offers significant advantages for the realization of neuromorphic devices/architectures, including ultralow-voltage operation and the ability to form parallel-interconnected networks with minimal hardwired connectivity. In this review, the most recent developments in EGT-based electronics are introduced with their synaptic behaviors and detailed mechanisms, including short-/long-term plasticity, global regulation phenomena, lateral coupling between device terminals, and spatiotemporal correlated functions. Analog memory phenomena allow for the implementation of perceptron-based ANNs. Due to their mixed-conductivity phenomena, neuromorphic circuits based on EGTs allow for facile interfacing with biological environments. We also discuss the future challenges in implementing low power, high speed, and reliable neuromorphic computing for large-scale ANNs with these neuromorphic devices. The advancement of neuromorphic devices that rely on EGTs highlights the importance of this field for neuromorphic computing and for novel healthcare technologies in the form of adaptable or trainable biointerfacing.

Digital and Analog Switching Characteristics of InGaZnO Memristor Depending on Top Electrode Material for Neuromorphic System

In this study, we demonstrate both of digital and analog memory operations in InGaZnO (IGZO) memristor devices by controlling the electrode materials for neuromorphic application. The switching properties of the devices are determined by the initial energy barrier characteristics between the metal electrodes and the IGZO switching layer. Digital switching characteristics are obtained after the forming process when Schottky junction occurs at both of top and bottom electrodes. On the other hands, analog resistive switching is achieved when Schottky and Ohmic junctions exist at each side because the applied voltage modulates the Schottky barrier height through the Ohmic contact. In addition, the weight-update properties of the devices are verified depending on identical and incremental pulse schemes. The incremental pulse trains improve the linearity and variation of weight modulation, leading to the stable learning characteristics of neuromorphic system in terms of pattern recognition with MNIST hand-written digit images.

Time-to-Voltage Converters Based on the Time-Sharing Principle

The authors offer a new approach to the creation of linear and nonlinear pulse width modulated (PWM) signal demodulators. The proposed approach is based on the time-sharing principle in feedback and feedforward circuits. The demodulators are characterized by ease of manufacturing due to the decreased need for analog element precision. The following circuits have been designed and presented: a PWM signal demodulator performing linear conversion of a PWM signal into voltage; calculating demodulators with the function of sum of products and simple fraction; and a demodulator with a fractional rational function. All these circuits are based on the principle of continuous signal averaging by the active Miller integrator with the storing of the intermediate result in an analog memory cell. The designed demodulators are investigated during modeling and full-scale experiments. The reviewed set of demodulators can be enlarged by adding similar circuits to the proposed structures with a larger number of inputs and new functional possibilities. The proposed solutions follow the modularity principle and can be used in fully integrated implementations.

Research and Design on Reducing the Difficulty of Magnetization of a Hybrid Permanent Magnet Memory Motor

In this article, magnetic barriers setting on both sides of a low coercive force magnet (low-Hc) and forward/reverse magnetization process of a parallel memory motor are analyzed by using magnetic circuit method and finite element analysis (FEA). The results show that magnetic barriers on both sides of the low-Hc magnets can weaken the influence of high coercive force magnets (high-Hc) on the low-Hc magnets and improve anti-demagnetization ability of the low-Hc permanent magnets. At the same time, the motor has difficulties in forward magnetization. In order to reduce the difficulty in magnetization of the motor, a new type of parallel hybrid permanent magnet memory motor is proposed. The structure and the operation principle of the motor are elaborated in detail in the paper. The analysis results by using the magnetic circuit method and FEA show that the new structure can greatly reduce the magnetization current of the motor. Compared with the existing parallel hybrid permanent magnet memory motor, the improved motor has comparatively less difficulty in magnetization and stronger anti-demagnetization ability. Finally, a prototype is fabricated and the magnetization performance and efficiency of the motor is verified. The measured results show that the motor has advantages of low magnetizing current and high efficiency.

Re-animating Ghosts: Materiality and memory in hauntological appropriation

This research examines the spectrality of animation and other media based on the photographic trace. Using diverse examples from popular culture and the author’s own investigative practice in media art, this paper looks at how archival media is re-used and can be brought back to life in new moving image works, in a gesture we might call hauntological appropriation. While sampling and re-using old materials is nothing new, over the last 15 years we have seen an ongoing tendency to foreground the ghostly qualities of vintage recordings and found footage, and a recurrent fetishisation and simulation of obsolete technologies. Here we examine the philosophies and productions behind this hauntological turn and why the materiality of still and moving image media has become such a focus. We ask how that materiality effects the machines that remember for us, and how we re-use these analogue memories in digital cultures. Due to the multimodal nature of the author’s creative practice, photography, video art, documentary film and animation, are interrogated here theoretically. Re-animating the ghosts of old media can reveal ontological differences between these forms, and a ghostly synergy between the animated and the photographic.

Improved Particle Filter Resampling Architectures

The most challenging aspect of particle filtering hardware implementation is the resampling step. This is because of high latency as it can be only partially executed in parallel with the other steps of particle filtering and has no inherent parallelism inside it. To reduce the latency, an improved resampling architecture is proposed which involves pre-fetching from the weight memory in parallel to the fetching of a value from a random function generator along with architectures for realizing the pre-fetch technique. This enables a particle filter using M particles with otherwise streaming operation to get new inputs more often than 2M cycles as the previously best approach gives. Results show that a pre-fetch buffer of five values achieves the best area-latency reduction trade-off while on average achieving an 85% reduction in latency for the resampling step leading to a sample time reduction of more than 40%. We also propose a generic division-free architecture for the resampling steps. It also removes the need of explicitly ordering the random values for efficient multinomial resampling implementation. In addition, on-the-fly computation of the cumulative sum of weights is proposed which helps reduce the word length of the particle weight memory. FPGA implementation results show that the memory size is reduced by up to 50%.

Electric readout of magnetic stripes in insulators

In superconductors, a topological configuration of the superconducting order parameter called a superconducting vortex carries magnetization. Such a magnetic topological object behaves like a minute particle generating a magnetic flux. Since the flux is localized with a nanometer scale, the vortex provides a nano-scale probe for local magnetic fields. Here we show that information of magnetic stripes in insulators can be read out by using vortices in an adjacent superconductor film as a probe. The orientation and width of magnetic micro stripes are both transcribed into resistance change of the superconductor through the modulation of vortex mobility affected by local magnetization. By changing the direction of external magnetic fields, zero-field resistance changes continuously according to the stripe orientation, and its modulation magnitude reaches up to 100%. The width of the stripes can also be estimated from the oscillatory magnetoresistance. Our results demonstrate a new possibility for non-volatile analog memory devices based on topological objects.

A Novel Compound Synapse Using Probabilistic Spin–Orbit-Torque Switching for MTJ-Based Deep Neural Networks

Analog electronic nonvolatile memories mimicking synaptic operations are being explored for the implementation of neuromorphic computing systems. Compound synapses consisting of ensembles of stochastic binary elements are alternatives to analog memory synapses to achieve multilevel memory operation. Among the existing binary memory technologies, magnetic tunneling junction (MTJ)-based magnetic random access memory (MRAM) technology has matured to the point of commercialization. More importantly for this work, stochasticity is natural to the MTJ switching physics, e.g., devices referred to as p-bits that mimic binary stochastic neurons. In this article, we experimentally demonstrate a novel compound synapse that uses stochastic spin–orbit-torque (SOT) switching of an ensemble of nanomagnets that are located on one shared spin Hall effect (SHE) material channel, i.e., tantalum. By using a properly chosen pulse scheme, we are able to demonstrate linear potentiation and depression in the synapse, as required for many neuromorphic architectures. In addition to this experimental effort, we also performed circuit simulations on an SOT-MRAM-based $784\times 200\times 10$ deep belief network (DBN) consisting of p-bit-based neurons and compound synapses. MNIST pattern recognition was used to evaluate the system performance, and our findings indicate that a significant reduction in recognition error rates can be achieved by improving the linearity of the potentiation and depression curves using an incremental pulse scheme.

Nitric oxide acts as a cotransmitter in a subset of dopaminergic neurons to diversify memory dynamics.

Animals employ diverse learning rules and synaptic plasticity dynamics to record temporal and statistical information about the world. However, the molecular mechanisms underlying this diversity are poorly understood. The anatomically defined compartments of the insect mushroom body function as parallel units of associative learning, with different learning rates, memory decay dynamics and flexibility (Aso and Rubin, 2016). Here, we show that nitric oxide (NO) acts as a neurotransmitter in a subset of dopaminergic neurons in Drosophila. NO's effects develop more slowly than those of dopamine and depend on soluble guanylate cyclase in postsynaptic Kenyon cells. NO acts antagonistically to dopamine; it shortens memory retention and facilitates the rapid updating of memories. The interplay of NO and dopamine enables memories stored in local domains along Kenyon cell axons to be specialized for predicting the value of odors based only on recent events. Our results provide key mechanistic insights into how diverse memory dynamics are established in parallel memory systems.

Versatile stochastic dot product circuits based on nonvolatile memories for high performance neurocomputing and neurooptimization

The key operation in stochastic neural networks, which have become the state-of-the-art approach for solving problems in machine learning, information theory, and statistics, is a stochastic dot-product. While there have been many demonstrations of dot-product circuits and, separately, of stochastic neurons, the efficient hardware implementation combining both functionalities is still missing. Here we report compact, fast, energy-efficient, and scalable stochastic dot-product circuits based on either passively integrated metal-oxide memristors or embedded floating-gate memories. The circuit’s high performance is due to mixed-signal implementation, while the efficient stochastic operation is achieved by utilizing circuit’s noise, intrinsic and/or extrinsic to the memory cell array. The dynamic scaling of weights, enabled by analog memory devices, allows for efficient realization of different annealing approaches to improve functionality. The proposed approach is experimentally verified for two representative applications, namely by implementing neural network for solving a four-node graph-partitioning problem, and a Boltzmann machine with 10-input and 8-hidden neurons.

AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed

In this article, we present innovative microarchitectural designs for multilayer deep neural networks (DNNs) implemented in crossbar arrays of analog memories. Data is transferred in a fully parallel manner between arrays without explicit analog-to-digital converters. Design ideas including source follower-based readout, array segmentation, and transmit-by-duration are adopted to improve the circuit efficiency. The execution energy and throughput, for both DNN training and inference, are analyzed quantitatively using circuit simulations of a full CMOS design in the 90-nm technology node. We find that our current design could achieve up to 12–14 TOPs/s/W energy efficiency for training, while a projected scaled design could achieve up to 250 TOPs/s/W. Key challenges in realizing analog AI systems are discussed.

Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die

Nonvolatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU's die. ReRAM bitcells are fabricated within crosspoint subarrays that leave the bulk of transistors underneath the subarrays vacant. This permits placing the memory system over the CPU, improving area, parallelism, and power. Our work quantifies the impact of integrating ReRAM into a CPU's die. When integrating ReRAM over CPU logic, the best area efficiency occurs when 48% of the die is covered with ReRAM. The CPU's area increases by 18.8%, but we can recoup 35.5% of the die area by utilizing the free transistors underneath the crosspoint subarrays. When integrating ReRAM over CPU cache, up to 85.3% of the cache can be covered with ReRAM. Our work also shows that on-die ReRAM can support very high bandwidth through massively parallel memory access. At 28 nm, 4–16k independent ReRAM banks could be integrated onto the CPU die, providing 512–1024–GB/s peak bandwidth. At more advanced technology nodes, 5–10 TB/s may be possible.

Low Power, CMOS-MoS2 Memtransistor based Neuromorphic Hybrid Architecture for Wake-Up Systems

Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.

Charge-Trap Transistors for CMOS-Only Analog Memory

Since our demonstration of unsupervised learning using the CMOS-only charge-trap transistors (CTTs) as analog synapses, there has been an increasing interest in exploiting the device for various other neural network (NN) applications. However, most of these studies are limited to mere simulation due to the absence of detailed experimental device characterization. In this article, we provide a comprehensive investigation of the programming behavior of CTTs, including analog retention, intra- and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array. It is found that, after programming, the channel current gradually increases to a higher level, and the shift is larger when the device is programmed to a higher threshold voltage. With this postprogramming current increase appropriately accounted for, individual devices can be programmed to an equivalent precision of five bits, and three bits can be achieved for devices in an array. Our results reveal the promising future of using the CTT as a CMOS-only analog memory device.

Optical memory architectures for fast routing address look-up (AL) table operation

Today, the increasing demand for fast routing processes has turned the address look-up (AL) operation into one of the main critical performance operations in modern optical networks, since it conventionally relies on slow-performing AL tables. Specifically, AL memory tables are comprised of content addressable memories (CAMs) for storing a known route of the forwarding information base of the router, and random access memories (RAMs) for storing the respective output port for this route. They thus allow for a one-cycle search operation of a packet’s destination address, yet they typically operate at speeds well below 1 GHz, in contrast with the vastly increasing optical line rates. In this paper, we present our overall vision towards light-based optical AL memory functionalities that may facilitate faster router AL operations, as the means to replace slow-performing electronic counterparts. In order to achieve this, we report on the development of a novel optical RAM cell architecture that performs for the first time with a speed of up to 10 Gb s−1, as well as our latest works on multi-bit 10 Gb s−1 optical CAM cell architectures. Specifically, the proposed optical RAM cell exploits a semiconductor optical amplifier-Mach–Zehnder interferometer in a push-pull configuration and deep saturation regime, doubling the speed of prior optical RAM cell configurations. Error-free write/read operation is demonstrated with a peak power penalty of 6.2 dB and 0.4 dB, respectively. Next, we present the recent progress on optical CAM cell architectures, starting with an experimental demonstration of a 2-bit optical CAM match-line architecture that achieves an exact bitwise search operation of an incoming 2-bit destination address at 10 Gb s−1, while the analysis is also extended to a numerical evaluation of a multi-cell 4-bit CAM-based row architecture with wavelength division multiplexed outputs for fast parallel memory operations at speeds of up to 4 × 20 Gb s−1. Finally, we present a comparative study between electronic and optical RAMs and CAMs in terms of energy and speed and discuss the further challenges towards our vision.

Low-Voltage, CMOS-Free Synaptic Memory Based on LiXTiO2 Redox Transistors.

Neuromorphic computers based on analogue neural networks aim to substantially lower computing power by reducing the need to shuttle data between memory and logic units. Artificial synapses containing nonvolatile analogue conductance states enable direct computation using memory elements; however, most nonvolatile analogue memories require high write voltages and large current densities and are accompanied by nonlinear and unpredictable weight updates. Here, we develop an inorganic redox transistor based on electrochemical lithium-ion insertion into LiXTiO2 that displays linear weight updates at both low current densities and low write voltages. The write voltage, as low as 200 mV at room temperature, is achieved by minimizing the open-circuit voltage and using a low-voltage diffusive memristor selector. We further show that the LiXTiO2 redox transistor can achieve an extremely sharp transistor subthreshold slope of just 40 mV/decade when operating in an electrochemically driven phase transformation regime.

Visual versus Verbal Working Memory in Statistically Determined Patients with Mild Cognitive Impairment: On behalf of the Consortium for Clinical and Epidemiological Neuropsychological Data Analysis (CENDA).

Previous research in mild cognitive impairment (MCI) suggests that visual episodic memory impairment may emerge before analogous verbal episodic memory impairment. The current study examined working memory (WM) test performance in MCI to assess whether patients present with greater visual versus verbal WM impairment. WM performance was also assessed in relation to hippocampal occupancy (HO), a ratio of hippocampal volume to ventricular dilation adjusted for demographic variables and intracranial volume. Jak etal. (2009) (The American Journal of Geriatric Psychiatry, 17, 368-375) and Edmonds, Delano-Wood, Galasko, Salmon, & Bondi (2015) (Journal of Alzheimer's Disease,47(1), 231-242) criteria classify patients into four groups: little to no cognitive impairment (non-MCI); subtle cognitive impairment (SCI); amnestic MCI (aMCI); and a combined mixed/dysexecutive MCI (mixed/dys MCI). WM was assessed using co-normed Wechsler Adult Intelligence Scale-IV (WAIS-IV) Digit Span Backwards and Wechsler Memory Scale-IV (WMS-IV) Symbol Span Z-scores. Between-group analyses found worse WMS-IV Symbol Span and WAIS-IV Digit Span Backwards performance for mixed/dys MCI compared to non-MCI patients. Within-group analyses found no differences for non-MCI patients; however, all other groups scored lower on WMS-IV Symbol Span than WAIS-IV Digit Span Backwards. Regression analysis with HO as the dependent variable was statistically significant for WMS-IV Symbol Span performance. WAIS-IV Digit Span Backwards performance failed to reach statistical significance. Worse WMS-IV Symbol Span performance was observed in patient groups with measurable neuropsychological impairment and better WMS-IV Symbol Span performance was associated with higher HO ratios. These results suggest that visual WM may be particularly sensitive to emergent illness compared to analogous verbal WM tests.

Time-dependent saccadic selection in analogue and categorical visual short-term memory tasks

Time-dependent saccadic selection in analogue and categorical visual short-term memory tasks

(Invited) Energy Efficient Neural Network Training with Analog Synapses: Challenges and Opportunities

As the exponential performance-per-watt gains from traditional CMOS scaling end, new computing paradigms are being seriously considered. Neural network algorithms such as deep neural networks (DNN) offer compatibility with analog, in-memory computing paradigm with the potential for orders of magnitude improvement over today’s special purpose chips. In this analog paradigm, neural network weights are stored as conductance levels in a physical matrix of tunable nonvolatile resistance memory devices, such as oxide-based resistive memory (ReRAM), phase change memory (PCRAM), three terminal floating gate, and redox memories. Our detailed analysis of a neural processing unit (NPU) core analog block based on these devices can perform individual inference and training operations at energies as low as 10 fJ per operation (100 TOPs/W), achieving greater than a 100x improvement over the best modern digital neural training processors. This will achieve revolutionary performance for modern deep neural network accelerators, which are currently found in computing from smartphones to datacenters. Improvements originate from the efficient mapping of key inference and training logical operations directly to the physical memory array. The multiply-accumulate operation is physically performed by Kirchoff’s Voltage Law (to multiply an input with a weight) and Kirchoff’s current law (to accumulate column weights) (Fig. 1). The enormous energy expense of moving the data from an arithmetic-logic-unit to a register and back several times per training operation is reduced by a factor roughly proportional to the number of rows (or columns) of a neural network weight matrix (typically >100). Analog array benefits have been well established for the inference stage of neural networks and are now under early commercial development. Harnessing analog arrays for neural network training offers to solve a significantly more energy intensive task than inference only – but analog training remains elusive due to device-level challenges. Training places electrical constraints on the analog memory far beyond those for inference-only accelerators. Foremost among these challenges is obtaining sufficient “linearity” and “symmetry” in analog memory devices. The conductance increments during a weight update operation must occur without feedback to verify the correct conductance change, as this iterative process would negate the energy and latency advances over digital CMOS. This open-loop weight update scheme requires that the analog memory changes a predictable conductance value linearly proportional to the number of write pulses, regardless of the initial state. Hence, this is known as “linearity” of an analog device. The linearity often tends to be differ between the positive and negative conductance increments, indicating poor device "symmetry." Furthermore, devices in an array must have significantly overlapping conductance ranges over many cycles. If the analog memory elements do not have sufficient linearity and symmetry, the neural network will suffer unacceptable accuracy loss during the training stage. This is still an area of active research, with several strong two- and three-terminal candidates. Sandia has developed a characterization methodology and modeling code, CrossSim, which allows the training accuracy to be evaluated for experimental devices. Two terminal emerging memories including oxide-based resistive memory (ReRAM) and phase change memory (PCRAM) are very dense and capable of high speed switching. However, typical TaOx ReRAM and GST PCRAM have been evaluated and found to suffer unacceptable accuracy losses, due to the nonlinearity and asymmetry inherent to the devices. In the case of ReRAM this is most likely due to the nonlinear acceleration of the filament growth these devices when switched from the high conductance to low conductance state, or the abrupt amorphization in the low to high conductance change during the PCRAM RESET process. Recently, three-terminal floating gate semiconductor-oxide-nitride-oxide-semiconductor (SONOS) cell, a close cousin of NAND-flash, have been demonstrated to have high training accuracy, low energy, and may be the best near-term weight storage device. However, challenges of SONOS include the relatively long write latency (>1μs), high voltage, limited scalability, and low endurance. The most novel emerging three terminal class of devices known as nonvolatile redox transistors show excellent training behavior with very low write voltages. These three terminal elements, such as Sandia’s Lithium-Ion Synaptic Transistor for Analog Computing (LISTA), utilize the electrochemical mechanism of a lithium-ion battery, where cathode conductivity is modulated by lithium or proton ion transport (charging and discharging the battery). While very promising, these devices face research challenges of increased speed, endurance, and CMOS integration. This presentation will discuss current research directions for key two- and three-terminal analog neural memory devices, with a focus on areas where materials and device innovation can drive significant process in neural training technology. SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525. Figure 1