Parallel Loops Research Articles

Systematic Knowledge Sharing in a Natural Hazard Damage Context: How Organizational Borders Limit Lessons Learned

The aim of this paper is to increase knowledge about systematic lessons learning in a public–private partnership. Empirically, it focuses on road maintenance in Sweden where the Swedish Transport Administration (STA) is responsible for the state‐owned infrastructure and tendered contractors carry out all maintenance. The tendering process stipulates that the stakeholders should enable learning and the knowledge transfer that is, by necessity, required for preventive purposes. Semi‐structured interviews with project leaders from the STA and respondents from two tendering contractors of maintenance were used to investigate attitudes to and the understanding of sharing experiences and knowledge about damage caused by weather extremes and the relevance of climate change adaptation in their field. The analysis suggests that most of the respondents’ experiences stay within their own organization, which creates parallel feedback loops, rather than becomes shared knowledge that could be used as lessons learned enhancing preventive work against future damage and loss. The analysis indicates imbalance in feedback of knowledge concerning weather extremes and their effects.

A numerical and experimental investigation on passive piezoelectric shunt damping of mistuned blisks

In a previous study, we proposed a method for the damping of rotationally periodic structures, when a specific mode with n nodal diameters is targeted. The proposed method considers 4 n lead zirconate titanate patches (or a multiple of) which can be, either, shunted independently on 4 n identical resistor–inductor circuits, or mounted in two parallel loops and shunted on only two resistor–inductor circuits. Both configurations offer the same performance; however, the parallel configuration requires only two inductors and it is aimed to reduce the demand on inductors; it works actually like a spatial filter and assumes a perfectly symmetric structure with harmonic mode shapes in the circumferential direction. The study presented in this article is aimed at evaluating the proposed damping technique in the presence of blade mistuning. In the first part, the parallel and the independent configurations are compared numerically on a set of mistuned bladed drums with controlled level of mistuning. In the second part, the parallel and the independent shunts are implemented experimentally on a mistuned bladed drum mock-up. For the considered mock-up, the numerical results show that for moderate levels of mistuning, the parallel shunt performs almost like the independent shunt, while the experimental results confirm this fact.

Biomass Gasification and Hot Gas Upgrading in a Decoupled Dual-Loop Gasifier

A decoupled dual-loop gasifier (DDLG) has been developed in which biomass gasification and hot gas upgrading are separated into two parallel loops so that they can be optimized individually. In the gasification loop, the gasifier is designed so that the contact between volatiles and char is restrained and, therefore, the steam gasification of char is enhanced. In the upgrading loop, both a desulfurizer and a tar-reforming catalyst are used for desulfurization and tar destruction, respectively. As the in-bed desulfurizer, an iron-bearing olivine-supported ZnO (Zn/olivine) material was prepared and tested in a fixed-bed reactor. H2S sorption over ZnO, adversely affected by H2O, was accompanied by the evident reduction of ZnO and vaporization of Zn at 550 °C. In contrast, no obvious ZnO reduction was observed under the same conditions over Zn/olivine. The reduction resistance of Zn/olivine was investigated by means of temperature-programmed reduction and powder X-ray diffraction. In DDLG tests with pine sawd...

Synthesis of divide and conquer parallelism for loops

Divide-and-conquer is a common parallel programming skeleton supported by many cross-platform multithreaded libraries, and most commonly used by programmers for parallelization. The challenges of producing (manually or automatically) a correct divide-and-conquer parallel program from a given sequential code are two-fold: (1) assuming that a good solution exists where individual worker threads execute a code identical to the sequential one, the programmer has to provide the extra code for dividing the tasks and combining the partial results (i.e. joins), and (2) the sequential code may not be suitable for divide-and-conquer parallelization as is, and may need to be modified to become a part of a good solution. We address both challenges in this paper. We present an automated synthesis technique to synthesize correct joins and an algorithm for modifying the sequential code to make it suitable for parallelization when necessary. This paper focuses on class of loops that traverse a read-only collection and compute a scalar function over that collection. We present theoretical results for when the necessary modifications to sequential code are possible, theoretical guarantees for the algorithmic solutions presented here, and experimental evaluation of the approach's success in practice and the quality of the produced parallel programs.

Full runtime polyhedral optimizing loop transformations with the generation, instantiation, and scheduling of code‐bones

SummaryIn this paper, we present a new runtime code generation technique for speculative loop optimization and parallelization. The main benefit of this technique, compared to previous approaches, is to enable advanced optimizing loop transformations at runtime with an acceptable time overhead. The loop transformations that may be applied are those handled by the polyhedral model. The proposed code generation strategy is based on the generation of “code‐bones” at compile‐time, which are parametrized code snippets either dedicated to speculation management or to computations of the original target program. These code‐bones are then instantiated and assembled at runtime to constitute the speculatively optimized code, as soon as an optimizing polyhedral transformation has been determined. Their granularity threshold is sufficient to apply any polyhedral transformation, while still enabling fast runtime code generation. This approach has been implemented in the speculative loop parallelizing framework APOLLO.

Parallel tiled Nussinov RNA folding loop nest generated using both dependence graph transitive closure and loop skewing

BackgroundRNA secondary structure prediction is a compute intensive task that lies at the core of several search algorithms in bioinformatics. Fortunately, the RNA folding approaches, such as the Nussinov base pair maximization, involve mathematical operations over affine control loops whose iteration space can be represented by the polyhedral model. Polyhedral compilation techniques have proven to be a powerful tool for optimization of dense array codes. However, classical affine loop nest transformations used with these techniques do not optimize effectively codes of dynamic programming of RNA structure predictions.ResultsThe purpose of this paper is to present a novel approach allowing for generation of a parallel tiled Nussinov RNA loop nest exposing significantly higher performance than that of known related code. This effect is achieved due to improving code locality and calculation parallelization. In order to improve code locality, we apply our previously published technique of automatic loop nest tiling to all the three loops of the Nussinov loop nest. This approach first forms original rectangular 3D tiles and then corrects them to establish their validity by means of applying the transitive closure of a dependence graph. To produce parallel code, we apply the loop skewing technique to a tiled Nussinov loop nest.ConclusionsThe technique is implemented as a part of the publicly available polyhedral source-to-source TRACO compiler. Generated code was run on modern Intel multi-core processors and coprocessors. We present the speed-up factor of generated Nussinov RNA parallel code and demonstrate that it is considerably faster than related codes in which only the two outer loops of the Nussinov loop nest are tiled.

SIMD Monte-Carlo Numerical Simulations Accelerated on GPU and Xeon Phi

The efficiency of a pleasingly parallel application is studied for several computing platforms. A real world problem, i.e., Monte-Carlo numerical simulations of stratospheric balloon envelope drift descent is considered. We detail the optimization of the SIMD parallel codes on the K40 and K80 GPUs as well as on the Intel Xeon Phi. We emphasize on loop and task parallelism, multi-threading and vectorization, respectively. The experiments show that GPU and MIC permit one to decrease computing time by non negligeable factors, as compared to a parallel code implemented on a two sockets CPU (E5-2680-v2) which finally allows us to use these devices in operational conditions.

Improvement of workload balancing using parallel loop self-scheduling on Intel Xeon Phi

In recent years, Intel promotes its new product Xeon Phi coprocessor, which is similar to the x86 architecture coprocessor. It has about 60 cores and can be regarded as a single computing node, with the computing power that cannot be ignored. This work aims to improve the workload balance by parallel loop self-scheduling scheme performed on Xeon Phi-based computer cluster. The proposed concept is implemented by hybrid MPI and OpenMP parallel programming in C language. Since parallel loop self-scheduling composes of static and dynamic allocation, weighting algorithm is adopted in the static part, while the well-known loop self-scheduling is adopted in dynamic part. The loop block is partitioned according to the weighting of MIC and HOST nodes. Accordingly, Xeon Phi with many-core is adopted to implement parallel loop self-scheduling. Finally, we test the performance in the experiments by four applicable problems: matrix multiplication, sparse matrix multiplication, Mandelbrot set and circuit meet. The experimental results indicate how to do the weight allocation and which scheduling method can achieve the best performance.

Decision Optimization for Power Grid Operating Conditions with High- and Low-Voltage Parallel Loops

With the development of higher-voltage power grids, the high- and low-voltage parallel loops are emerging, which lead to energy losses and even threaten the security and stability of power systems. The multi-infeed high-voltage direct current (HVDC) configurations widely appearing in AC/DC interconnected power systems make this situation even worse. Aimed at energy saving and system security, a decision optimization method for power grid operating conditions with high- and low-voltage parallel loops is proposed in this paper. Firstly, considering hub substation distribution and power grid structure, parallel loop opening schemes are generated with GN (Girvan-Newman) algorithms. Then, candidate opening schemes are preliminarily selected from all these generated schemes based on a filtering index. Finally, with the influence on power system security, stability and operation economy in consideration, an evaluation model for candidate opening schemes is founded based on analytic hierarchy process (AHP). And a fuzzy evaluation algorithm is used to find the optimal scheme. Simulation results of a New England 39-bus system and an actual power system validate the effectiveness and superiority of this proposed method.

Virtual Solar Field - Validation of a detailed transient simulation tool for line focus STE fields with single phase heat transfer fluid

Simulation models enable designers and operators to test different settings of the real systems while avoiding the large costs associated with experimental or practical systems. However, creating models that resemble the real physical system with acceptable accuracy and computational time remains a challenge for developers of such tools. With this motivation, a new simulation tool, the Virtual Solar Field (VSF), has been developed for line-focus power plants with single-phase heat transfer fluid (HTF) to assist in plant control during transient processes. VSF is a whole-field model based on an efficient coupling of hydraulic and thermal solvers that take into account the flow distribution in the parallel loops, as well as the transient conditions in the field.In this paper, some validation cases for VSF using data from Andasol-3 power plant are shown. Five test cases are examined, which include normal operation, start-up and evening operation during clear-sky and strong transients. The results show very good agreement with the real plant and some discrepancies are discussed and studied. The main sources of discrepancies are associated with difficulties in modelling all fine details of reality using the current technologies in some commercial power plants. For example, small cloud passage are not detected by the few weather stations in the power plant, as well as knowing the exact loop valve settings is not possible in Andasol-3. In addition, an overview of the potential applications of VSF are mentioned and briefly discussed. VSF offers a suitable platform for testing novel control strategies and assessing the performance of the solar fields.

Tapir

This paper explores how fork-join parallelism, as supported by concurrency platforms such as Cilk and OpenMP, can be embedded into a compiler's intermediate representation (IR). Mainstream compilers typically treat parallel linguistic constructs as syntactic sugar for function calls into a parallel runtime. These calls prevent the compiler from performing optimizations across parallel control constructs. Remedying this situation is generally thought to require an extensive reworking of compiler analyses and code transformations to handle parallel semantics. Tapir is a compiler IR that represents logically parallel tasks asymmetrically in the program's control flow graph. Tapir allows the compiler to optimize across parallel control constructs with only minor changes to its existing analyses and code transformations. To prototype Tapir in the LLVM compiler, for example, we added or modified about 6000 lines of LLVM's 4-million-line codebase. Tapir enables LLVM's existing compiler optimizations for serial code -- including loop-invariant-code motion, common-subexpression elimination, and tail-recursion elimination -- to work with parallel control constructs such as spawning and parallel loops. Tapir also supports parallel optimizations such as loop scheduling.

Validation of parallelizing transformations of sequential programs

SummaryTransformations for high‐performance superscalar, vector, and parallel processors maximize parallelism and memory locality. Often parallelizing compilers apply transformations, such as loop parallelization and loop vectorization, to convert a sequential array‐handling program into a parallel program. Validation of such transformations is extremely useful in the prevalent high‐performance computing environment. This paper proposes a novel algorithm for construction of the dependence graph of the generated parallel programs. These transformations are validated by checking equivalence of the dependence graphs of the original sequential program and the transformed parallel program using a standard algorithm reported in the literature. The above equivalence checker works even when the above parallelizing transformations are preceded by various enabling transformations except for loop collapsing transformation that changes the dimensions of the arrays. In the present paper, the scope of the equivalence checker has been expanded to handle this special case by informing it of the correspondence between the index spaces of the corresponding of input and output arrays in the sequential and the parallel programs. The proposed methods are implemented and tested against a set of available benchmark programs that are parallelized by the polyhedral auto‐parallelizer LooPo and the auto‐vectorizer Scout.

OpenMP with parallel loops or asynchronous tasks: a performance evaluation focusing the NQueens benchmark

This paper presents a performance evaluation of the NQueens benchmark implemented using OpenMP in parallel loop and asynchronous tasks versions. Our experiments aimed to evaluate which parallel strategy reaches the best performance, as well as to verify whether different compiler tools suporting OpenMP affect the results. First, we evaluate the NQueens version available in BOTS suite. Then, two new versions with optimizations were coded and tested. Experimental results suggest that our asynchronous tasks version outperforms the parallel loops version on performance. Besides, it seems that different compilers may impact performance on both OpenMP NQueens versions.

Analysis on Double Loop Wireless Power Transfer

This paper examines the properties of the double loop wireless power transmitter using numerical simulations. The double loop wireless power transmitter consists of two coupling and parallel loop antennas which transmit field energy through resonant electromagnetic waves. This tech-nology can be applied in RFIDs (Radio Frequency Identification) and re-mote charging scenarios where wires cannot be applied to, including the wireless charging of drones and satellites.

Architecture, Languages, Compilation and Hardware support for Emerging ManYcore systems (ALCHEMY): Preface

Manycore systems are one of the key enabler technologies for most of current computational paradigms, including Internet of things, data-centers on chip and big data processing. These paradigms are characterized by tight and demanding requirements such as code portability, dynamicity, high performance, usability, predictability, reliability, low power and security.This combination of requirements has led to heterogeneous manycore systems which are extremely challenging to design and to program. As a result, a large body of research has focused on development of languages, simulation environments and analysis tools that allow to model and predict the behavior of this type of systems from early design stages.ALCHEMY 2017 presents five research works addressing the challenges of code portability, high performance, usability, security and reliability in manycore systems. These are namely:1. ”An OpenMP backend for the Sigma-C streaming language, addresses the software portability challenge of manycore architectures. It proposes an implementation of an OpenMP backend for the SigmaC language, a cycle-static data flow abstraction to program many-core embedded platforms. Its compilation scheme allows for utilization of future manycore embedded systems such as Kalray’s MPPA.2. A multi-level optimization strategy to improve the performance of the stencil computation combines manual vectorization, space tiling and stencil composition for achieving high performance of stencil kernels on manycore systems. The evaluation with three compilers (Intel, Clang and GCC) and two target multi-core platforms (Intel Broadwell and Ivybridge) reports better results compared to the state of the art.3. A Distributed Shared Memory Model and C++ Templated Meta-Programming Interface for the Epiphany RISC Array Processor addresses the usability challenge. It proposes techniques for data layout and parallel loop order abstraction as a parallel programming API targeting the Epiphany architecture. This results into a transparent distributed shared memory (DSM) model for Epiphany that eliminates the need to manage local data movement between cores.4. Towards Protected MPSoC Communication for Information Protection against a Malicious NoC deals with vulnerabilities on Network-on-Chip (NoC). The authors propose a security protocol which allows the secure communication among the cores of the system, even in the presence of Trojan insertions at the NoC whose aim is to modify and steal data.5. GPU-Accelerated Real-Time Path Planning and the Predictable Execution Model addresses the reliability challenge and tackles the important problem of ensuring reliable Worst Case Execution Time for Real-Time and Cyber Physical Systems. While considering heterogeneous (CPU/GPU), the idea is to separate memory and processor operations through Time-Division Multiplexing (TDM).

Wing-bib multi helix maxillary expander

An orthodontic appliance for maxillary expansion is presented, which consists of a wire assembly fabricated from 0.032” round straight length beta-titanium wire. Posterior active portion of the appliance consists of a trihelix omega loop parallel to palatal surface, providing transverse expansion and distalizing forces on the first molars. Anterior active portion consisting of an acrylic apron (bib) over a (wing-like) wire framework, provides transverse expansion at the anterolateral slopes of the palate including the depths; lying directly over the envisioned canine- first premolar root area of the palatal vault surface.

Nested-Loops Tiling for Parallelization and Locality Optimization

Data locality improvement and nested loops parallelization are two complementary and competing approaches for optimizing loop nests that constitute a large portion of computation times in scientific and engineering programs. While there are effective methods for each one of these, prior studies have paid less attention to address these two simultaneously. This paper proposes a unified approach that integrates these two techniques to obtain an appropriate locality conscious loop transformation to partition the loop iteration space into outer parallel tiled loops. The approach is based on the polyhedral model to achieve a multidimensional affine scheduling as a transformation that result the largest groups of tilable loops with maximum coarse grain parallelism, as far as possible. Furthermore, tiles will be scheduled on processor cores to exploit maximum data reuse through scheduling tiles with high volume of data sharing on the same core consecutively or on different cores with shared cache at around the same time.

Decision making under uncertainty in a spiking neural network model of the basal ganglia.

The mechanisms of decision-making and action selection are generally thought to be under the control of parallel cortico-subcortical loops connecting back to distinct areas of cortex through the basal ganglia and processing motor, cognitive and limbic modalities of decision-making. We have used these properties to develop and extend a connectionist model at a spiking neuron level based on a previous rate model approach. This model is demonstrated on decision-making tasks that have been studied in primates and the electrophysiology interpreted to show that the decision is made in two steps. To model this, we have used two parallel loops, each of which performs decision-making based on interactions between positive and negative feedback pathways. This model is able to perform two-level decision-making as in primates. We show here that, before learning, synaptic noise is sufficient to drive the decision-making process and that, after learning, the decision is based on the choice that has proven most likely to be rewarded. The model is then submitted to lesion tests, reversal learning and extinction protocols. We show that, under these conditions, it behaves in a consistent manner and provides predictions in accordance with observed experimental data.

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

Free-Positioning Wireless Power Transfer to Multiple Devices Using a Planar Transmitting Coil and Switchable Impedance Matching Networks

In this paper, an efficient free-positioning wireless power transfer (WPT) system for charging multiple devices is proposed. For the system, a planar transmitting (Tx) coil that consists of a spiral coil and concentric multiple parallel loops and switchable impedance matching networks (IMNs) at a transmitter are developed. Using the Tx coil, mutual inductance between the Tx coil and the receiving (Rx) spiral coils is made uniform in the effective charging area. The parallel loops are placed in the interior of the Tx coil, and the magnetic field is enhanced and controlled by adjusting the space in each parallel loop. For optimal design of the coil, an analysis method using an equivalent circuit is explained in detail. It is found that the current of one loop of a parallel loop is more than the input current and negative current flows on the other loop, while the total current of each parallel loop is constant. An array of parallel capacitors with a switch as the switchable IMN is used for the maximum power transfer efficiency corresponding to the number of devices. The reflection coefficients of the fabricated WPT system are under −10 dB at 6.78 MHz, regardless of the number of devices and positions. The WPT system has the maximum power transfer efficiencies of 93% for two devices and simultaneously transfers uniform power to up to four devices with high efficiency.