Parallel Loops Research Articles

Experimental analysis on the loop heat pipes with different microchannel evaporators

Thoroughly understanding the influence of evaporator design on the characteristics of loop heat pipes (LHPs) is of great significance to develop optimal microchannel structures for high-power microprocessors. In the current work, the parallel microchannel loop heat pipe (PMLHP) and the self-similar fractal microchannel loop heat pipe (SFMLHP) were designed, fabricated and experimentally analyzed from the aspects of filling ratio and inclined angle, and then the heat transfer performances were compared with the dendritic bionic microchannel loop heat pipe (DBMLHP) under the same experimental conditions. The results show that PMLHP had four operation phenomena similar to DBMLHP while SFMLHP only had two operation phenomena. The start-up performances of PMLHP and SFMLHP were the best when the inclined angle was 90°. When the inclined angle was fixed at 90°, the optimal filling ratios for PMLHP and SFMLHP to yield the optimal thermal resistance were rather different. Through comparative analysis, it can be concluded that the overall heat transfer characteristic of DBMLHP was the best of the three under specified conditions. However, the average temperature fluctuation range in DBMLHP evaporator was the largest in the stable operation. The results provide valuable guidance on the choice of better and more suitable evaporator structure for microchannel loop heat pipes.

Alternating direction implicit time integrations for finite difference acoustic wave propagation: Parallelization and convergence

This work studies the parallelization and empirical convergence of two finite difference acoustic wave propagation methods on 2-D rectangular grids, that use the same alternating direction implicit (ADI) time integration. This ADI integration is based on a second-order implicit Crank-Nicolson temporal discretization that is factored out by a Peaceman-Rachford decomposition of the time and space equation terms. In space, these methods highly diverge and apply different fourth-order accurate differentiation techniques. The first method uses compact finite differences (CFD) on nodal meshes that requires solving tridiagonal linear systems along each grid line, while the second one employs staggered-grid mimetic finite differences (MFD). For each method, we implement three parallel versions: (i) a multithreaded code in Octave, (ii) a C++ code that exploits OpenMP loop parallelization, and (iii) a CUDA kernel for a NVIDIA GTX 960 Maxwell card. In these implementations, the main source of parallelism is the simultaneous ADI updating of each wave field matrix, either column-wise or row-wise, according to the differentiation direction. In our numerical applications, the highest performances are displayed by the CFD and MFD CUDA codes that achieve speedups of 7.21x and 15.81x, respectively, relative to their C++ sequential counterparts with optimal compilation flags. Our test cases also allow to assess the numerical convergence and accuracy of both methods. In a problem with exact harmonic solution, both methods exhibit convergence rates close to 4 and the MDF accuracy is practically higher. Alternatively, both convergences decay to second order on smooth problems with severe gradients at boundaries, and the MDF rates degrade in highly-resolved grids leading to larger inaccuracies. This transition of empirical convergences agrees with the nominal truncation errors in space and time.

Low Frequency Magnetic Shielding Effectiveness of a Conducting Plate With Periodic Apertures

This article focuses on the shielding effectiveness (SE) prediction of the periodic aperture array on an infinite PEC plate against the low frequency (≤1 MHz) magnetic field resulting from a current loop parallel to the plate. Two different models of the penetration field through the plate are presented. From the two models, the same simplified expression for the field on the central axis is derived. The SE of a 1000 mm × 1000 mm aluminum plate with 2500 apertures against the magnetic field from a current loop is measured. The results show that the theoretical results are in good agreement with the measurement if the frequency is higher than a critical frequency. Above the critical frequency, penetration from the apertures is primary factor for field leakage, and the SE is constant with the increasing frequency. When the frequency is lower than the critical frequency, penetration from the aluminum is primary channel for field leakage, and hence the SE reduces with the decreasing frequency. In this case, the upper limit of the SE does not exceed the SE of the corresponding solid plate without apertures.

Velocity storage mechanism drives a cerebellar clock for predictive eye velocity control

Predictive motor control is ubiquitously employed in animal kingdom to achieve rapid and precise motor action. In most vertebrates large, moving visual scenes induce an optokinetic response (OKR) control of eye movements to stabilize vision. In goldfish, the OKR was found to be predictive after a prolonged exposure to temporally periodic visual motion. A recent study showed the cerebellum necessary to acquire this predictive OKR (pOKR), but it remained unclear as to whether the cerebellum alone was sufficient. Herein we examined different fish species known to share the basic architecture of cerebellar neuronal circuitry for their ability to acquire pOKR. Carps were shown to acquire pOKR like goldfish while zebrafish and medaka did not, demonstrating the cerebellum alone not to be sufficient. Interestingly, those fish that acquired pOKR were found to exhibit long-lasting optokinetic after nystagmus (OKAN) as opposed to those that didn’t. To directly manipulate OKAN vestibular-neurectomy was performed in goldfish that severely shortened OKAN, but pOKR was acquired comparable to normal animals. These results suggest that the neuronal circuitry producing OKAN, known as the velocity storage mechanism (VSM), is required to acquire pOKR irrespective of OKAN duration. Taken together, we conclude that pOKR is acquired through recurrent cerebellum-brainstem parallel loops in which the cerebellum adjusts VSM signal flow and, in turn, receives appropriately timed eye velocity information to clock visual world motion.

Parallel Loop Control for Torque and Angular Velocity of BLDC Motors with DTC Commutation

This paper is focused in the development of a parallel control loop of the angular velocity and torque for Brushless Direct Current (BLDC) motors. This parallel loop is proposed as an improvement for the performance of those cascaded solutions commonly reported in the body of literature of the field. Performance is improved by reducing the steady state error of the speed considerably when compared with the typical cascaded loop solution under a commanded change of torque. In addition, the steady state response of the parallel loop is reached in a shorter time. Simulations were designed to carry out a comparison between both methodologies. The results of these simulations consider only changes in the set point for speed or torque and are reported here. The control signal was applied to a simulated driver using a switching method known as Direct Torque Control of 2 and 3 phases (DTC-2+3P). These preliminary results show that the parallel control loop outperforms the cascaded control of BLDC motors.

Performance Modeling of Parallel Loops on Multi-Socket Platforms Using Queueing Systems

Predicting the performance of parallel loops on modern shared-memory multi-socket multi-core systems in dependence of the allocated resources is an important means to achieve better system utilization. Previous prediction techniques are tied to specific architectures and do not allow for purely online performance predictions without requiring an offline analysis of the parallel program. This paper presents a practical approach based on queueing theory to model the performance of parallel programs in dependence of the number of allocated core resources. Based on the key insight that scalability of scientific parallel loops is limited by memory performance, a hierarchically constructed M/M/1/N/N queue system is used to analytically compute the response time at the different congestion points in the memory system of modern NUMA architectures. After automatically tuning the model to a specific architecture by executing a number of micro-benchmarks, the required parameter values are obtained at runtime from hardware performance counters present in modern commodity AMD and Intel processors. Evaluated with 24 OpenMP parallel loops on a 64-core AMD and a 72-core Intel multi-socket platform, the presented queueing system is able to accurately predict the speedup of parallel loops with a mean absolute percentage error of 8.3 percent on the AMD system and 6.7 percent on the Intel platform.

The modeling and energy efficiency analysis of thermal energy management operation of ground source heat pump air-conditioning system

To improve the energy-saving effect of the ground source heat pump air-conditioning system, an example is investigated, and the annual loads of the building are simulated and analyzed. The thermal energy management operation modelling is conducted. The hydraulic analysis is performed for different modes in each section. Given the same flow and tube type, a larger pipe diameter indicates a smaller hydraulic loss. Compared with the parallel 5-well loop and the parallel 10-well loop, the hydraulic loss of the series 2-well loop is the highest. When the sub-catch is connected to 5 loops, as the number of series wells increases, the tube length gets longer, the flow rate allocated by the loop gets less, and the load increases. Besides, the energy efficiency ratio of the ground source side decreases as the heat rejection load increases. Therefore, by adjusting the pipe diameter, the pipe type, and the depth of the well, the hydraulic loss can be reduced. The energy-saving effect of the loop in the parallel mode is better. Given the limited number of the managed wells, the parallel circuit can be adjusted to the same program. The connection allows the collector to distribute the flow evenly. The energy efficiency ratio of the ground source can be improved by changing the diameter of the horizontal trunk pipe. It is hoped that the hydraulic optimization design of the ground source heat pump air-conditioning system can provide a theoretical basis for the application and promotion of the ground source heat pumps.

Comparison for gas flow range 5 ml/min to 30 l/min (EURAMET.M.FF-S10)

The EURAMET.M.FF-S10 comparison, also registered as EURAMET project 1325, was organized to compare the results of low gas flow facilities at twelve European laboratories. The following laboratories took part in the comparison: MIKES (Finland), INRIM (Italy), PTB (Germany), FORCE (Denmark), METAS (Switzerland), VSL (Netherlands), EIM (Greece), UL (Slovenia), CMI (Czech Republic), LNE (France), GUM (Poland), LEI (Lithuania).Due to the high amount of participants, the comparison was carried out in two parallel loops with one circulating transfer standard in each loop. MIKES acted as the pilot laboratory and INRIM and PTB were the linking laboratories. High-accuracy piston provers (MesaLabs DryCal 800) provided by Mesa Laboratories Inc. were used as transfer standards. Each transfer standard package consisted of three flow cells in order to cover the flow range of the comparison from 5 ml/min to 30 l/min.Generally, a good agreement between participating laboratories was found; 85% of the results agree with the comparison reference value and only 8% were found inconsistent. The remaining 7% of results were classified as inconclusive, because the participating laboratory stated uncertainty was lower than the standard uncertainty of the transfer standard.The comparison provided valuable experience of using piston provers as high precision transfer standards. Such an extensive inter-comparison using piston provers has not been done before. As such, it gives a good overview on the capabilities of European laboratories of calibrating such instruments that are commonly used in industrial calibration laboratories worldwide.Main textTo reach the main text of this paper, click on Final Report. Note that this text is that which appears in Appendix B of the BIPM key comparison database kcdb.bipm.org/.The final report has been peer-reviewed and approved for publication by the CCM, according to the provisions of the CIPM Mutual Recognition Arrangement (CIPM MRA).

Auto-Tuning of Dynamic Scheduling Applied to 3D Reverse Time Migration on Multicore Systems

Reverse time migration (RTM) is an algorithm widely used in the oil and gas industry to process seismic data. It is a computationally intensive task that suits well in parallel computers. Methods such as RTM can be parallelized in shared memory systems through scheduling iterations of parallel loops to threads. However, several aspects, such as memory size and hierarchy, number of cores, and input size, make optimal scheduling very challenging. In this paper, we introduce a run-time strategy to automatically tune the dynamic scheduling of parallel loops iterations in iterative applications, such as the RTM, in multicore systems. The proposed method aims to reduce the execution time of such applications. To find the optimal granularity, we propose a coupled simulated annealing (CSA) based auto-tuning strategy that adjusts the chunk size of work that OpenMP parallel loops assign dynamically to worker threads during the initialization of a 3D RTM application. Experiments performed with different computational systems and input sizes show that the proposed method is consistently better than the default OpenMP schedulers, static, auto, and guided, causing the application to be up to 33% faster. We show that the possible reason for this performance is the reduction of cache misses, mainly level L3, and low overhead, inferior to 2%. Having shown to be robust and scalable for the 3D RTM, the proposed method could also improve the performance of similar wave-based algorithms, such as full-waveform inversion (FWI) and other iterative applications.

A Probabilistic Machine Learning Approach to Scheduling Parallel Loops with Bayesian Optimization

This paper proposes Bayesian optimization augmented factoring self-scheduling (BO FSS), a new parallel loop scheduling strategy. BO FSS is an automatic tuning variant of the factoring self-scheduling (FSS) algorithm and is based on Bayesian optimization (BO), a black-box optimization algorithm. Its core idea is to automatically tune the internal parameter of FSS by solving an optimization problem using BO. The tuning procedure only requires online execution time measurement of the target loop. In order to apply BO, we model the execution time using two Gaussian process (GP) probabilistic machine learning models. Notably, we propose a locality-aware GP model, which assumes that the temporal locality effect resembles an exponentially decreasing function. By accurately modeling the temporal locality effect, our locality-aware GP model accelerates the convergence of BO. We implemented BO FSS on the GCC implementation of the OpenMP standard and evaluated its performance against other scheduling algorithms. Also, to quantify our method's performance variation on different workloads, or workload-robustness in our terms, we measure the minimax regret. According to the minimax regret, BO FSS shows more consistent performance than other algorithms. Within the considered workloads, BO FSS improves the execution time of FSS by as much as 22% and 5% on average.

Распараллеливание рекуррентных циклов с предварительным вычислением суперпозиций

Распараллеливание рекуррентных циклов с предварительным вычислением суперпозиций

IR-Level Dynamic Data Dependence Using Abstract Interpretation Towards Speculative Parallelization

Recently, with the wide usage of multicore architectures, automatic parallelization has become a pressing issue. Speculative parallelization, one of the most popular automatic parallelization techniques, depends on estimating probably-parallelized code parts. This in turn motivates the employment of data dependence detection techniques for these code parts to report whether they contain dependence or not in order to be parallelized. In this paper, we propose a runtime data-dependence detection technique that is based on abstract interpretation at the intermediate representation (IR) level. We apply our proposed approach on the most frequently visited blocks of the code, hot loops. Unlike most existing approaches in which data analysis occurs at compile time, our proposed method conducts the analysis immediately while interpreting the code, which in turn saves the analysis time for potentially parallelized loops. Specifically, the proposed technique depends on the concept of abstract interpretation to analyze the hot loops at runtime. This process is done by firstly computing the abstract domain for each hot loop program points. Each abstract domain is incrementally computed, till a fixpoint is achieved for all program points, and correspondingly the analysis terminates in order to consecutively detect the existence of data dependence. Once the analysis result reports a parallelization possibility for the finished hot loop, the interpreter invokes the compiler to resume the execution in a parallel fashion as recommended by our proposed approach. The proposed technique is implemented on LLVM compiler, then used to test the dependence detection for a set of kernels on the Polybench framework, and the data dependence analysis required for each kernel is studied in terms of the computation overhead.

Improving runtime performance and energy consumption through balanced data locality with NUMA-BTLP and NUMA-BTDM static algorithms for thread classification and thread type-aware mapping

Extending compilers like LLVM with NUMA-aware optimisations significantly improves runtime performance and energy consumption on NUMA systems. The paper presents NUMA-BTDM algorithm, which is a compile-time thread-type dependent mapping algorithm that performs the mapping uniformly based on the type of each thread given by NUMA-BTLP algorithm following a static analysis on the code. First, the compiler inserts in the program code architecture dependent code that detects at runtime the characteristics of the underlying architecture for Intel processors, and then the mapping is performed at runtime (using specific functions calls from the PThreads library) depending on these characteristics following a compile-time mapping analysis which gives the CPU affinity of each thread. NUMA-BTDM allows the application to customise, control and optimise the thread mapping and achieves balanced data locality on NUMA systems for C parallel code that combine PThreads based task parallelism with OpenMP based loop parallelism.

Reconfigurable high-resolution photonic fractional Fourier transformer for broadband frequency measurement and large-scale chirp rate characterization of microwave signals

A reconfigurable photonic fractional Fourier transformer is proposed to realize broadband frequency measurement and large-scale chirp rate characterization of microwave signals with a high resolution. This scheme is based on three parallel frequency-shifting loops (FSLs) with co-prime free spectral range (FSR). Tunable high-resolution fractional Fourier transform is achieved through simply changing the frequency shift in each FSL with a small FSR, and large unambiguous frequency and chirp rate measurement range are guaranteed by the proposed recovery algorithm. In the numerical verification, non-aliasing frequency measurement range up to 14.7404 GHz and unambiguous chirp rate characterization range from -4.35×105 to 4.35×105 GHz/μs are obtained by using three FSLs with FSRs of 17.13 MHz, 17.21 MHz and 17.39 MHz, where the frequency resolution and the chirp rate resolution are 139.12 kHz and 0.3356 GHz/ms, respectively. Through properly setting the FSR in each FSL, the frequency and chirp rate measurement range can be further improved, which can find application in electronic warfare to achieve microwave signal recognition.

Tapir

Tapir (pronounced TAY-per) is a compiler intermediate representation (IR) that embeds recursive fork-join parallelism, as supported by task-parallel programming platforms such as Cilk and OpenMP, into a mainstream compiler’s IR. Mainstream compilers typically treat parallel linguistic constructs as syntactic sugar for function calls into a parallel runtime. These calls prevent the compiler from performing optimizations on and across parallel control constructs. Remedying this situation has generally been thought to require an extensive reworking of compiler analyses and code transformations to handle parallel semantics. Tapir leverages the “serial-projection property,” which is commonly satisfied by task-parallel programs, to handle the semantics of these programs without an extensive rework of the compiler. For recursive fork-join programs that satisfy the serial-projection property, Tapir enables effective compiler optimization of parallel programs with only minor changes to existing compiler analyses and code transformations. Tapir uses the serial-projection property to order logically parallel fine-grained tasks in the program’s control-flow graph. This ordered representation of parallel tasks allows the compiler to optimize parallel codes effectively with only minor modifications. For example, to implement Tapir/LLVM, a prototype of Tapir in the LLVM compiler, we added or modified less than 3,000 lines of LLVM’s half-million-line core middle-end functionality. These changes sufficed to enable LLVM’s existing compiler optimizations for serial code—including loop-invariant-code motion, common-subexpression elimination, and tail-recursion elimination—to work with parallel control constructs such as parallel loops and Cilk’s Cilk_Spawn keyword. Tapir also supports parallel optimizations, such as loop scheduling, which restructure the parallel control flow of the program. By making use of existing LLVM optimizations and new parallel optimizations, Tapir/LLVM can optimize recursive fork-join programs more effectively than traditional compilation methods. On a suite of 35 Cilk application benchmarks, Tapir/LLVM produces more efficient executables for 30 benchmarks, with faster 18-core running times for 26 of them, compared to a nearly identical compiler that compiles parallel linguistic constructs the traditional way.

Nested MIMD-SIMD Parallelization for Heterogeneous Microprocessors

Heterogeneous microprocessors integrate a CPU and GPU on the same chip, providing fast CPU-GPU communication and enabling cores to compute on data “in place.” This permits exploiting a finer granularity of parallelism on the integrated GPUs, and enables the use of GPUs for accelerating more complex and irregular codes. One challenge, however, is exposing enough parallelism such that both the CPU and GPU are effectively utilized to achieve maximum gain. In this article, we propose exploiting nested parallelism for integrated CPU-GPU chips. We look for loop structures in which one or more regular data parallel loops are nested within a parallel outer loop that can contain irregular code (e.g., with control divergence). By scheduling the outer loop on multiple CPU cores, multiple dynamic instances of the inner regular loop(s) can be scheduled on the GPU cores. This boosts GPU utilization and parallelizes the outer loop. We find that such nested MIMD-SIMD parallelization provides greater levels of parallelism for integrated CPU-GPU chips, and additionally there is ample opportunity to perform such parallelization in OpenMP programs. Our results show nested MIMD-SIMD parallelization provides a 16.1x and 8.67x speedup over sequential execution on a simulator and a physical machine, respectively. Our technique beats CPU-only parallelization by 4.13x and 2.40x, respectively, and GPU-only parallelization by 2.74x and 2.26x, respectively. Compared to the next-best scheme (either CPU- or GPU-only parallelization) per benchmark, our approach provides a 1.46x and 1.23x speedup for the simulator and physical machine, respectively.

How Boundaries Form: Linked Nonautonomous Feedback Loops Regulate Pattern Formation in Yeast Colonies.

Under conditions in which budding yeast form colonies and then undergo meiosis/sporulation, the resulting colonies are organized such that a sharply defined layer of meiotic cells overlays a layer of unsporulated cells termed "feeder cells." This differentiation pattern requires activation of both the Rlm1/cell-wall integrity pathway and the Rim101/alkaline-response pathway. In the current study, we analyzed the connection between these two signaling pathways in regulating colony development by determining expression patterns and cell-autonomy relationships. We present evidence that two parallel cell-nonautonomous positive-feedback loops are active in colony patterning, an Rlm1-Slt2 loop active in feeder cells and an Rim101-Ime1 loop active in meiotic cells. The Rlm1-Slt2 loop is expressed first and subsequently activates the Rim101-Ime1 loop through a cell-nonautonomous mechanism. Once activated, each feedback loop activates the cell fate specific to its colony region. At the same time, cell-autonomous mechanisms inhibit ectopic fates within these regions. In addition, once the second loop is active, it represses the first loop through a cell-nonautonomous mechanism. Linked cell-nonautonomous positive-feedback loops, by amplifying small differences in microenvironments, may be a general mechanism for pattern formation in yeast and other organisms.

A new method to model dislocation self-climb dominated by core diffusion

The mobility of atoms in dislocation core regions is many orders of magnitude faster than in the surrounding lattice. This rapid atomic transport along dislocation cores plays a significant role in the kinetics of many material processes, including low-temperature creep and post-irradiation annealing. In the present work, a finite element based analysis of the dislocation core diffusion process is presented; based on a variational principle for the evolution of microstructure. A dislocation self-climb model is then developed by incorporating this finite element core diffusion formulation within the nodal based three-dimensional discrete dislocation dynamics framework. The behaviour of an isolated loop in bcc iron is briefly reviewed, and simulations are extended to include the loop coarsening processes of both parallel and non-parallel loops by self-climb plus glide mechanisms, in which the huge time scale separation between climb and glide is bridged by an adaptive time stepping scheme. Excellent agreement is obtained between the numerical simulation, the theoretical solution of rigid prismatic loops and published experimental results. The coarsening process of a population of loops is simulated to investigate the mechanisms of the accumulative interactions and large-scale-patterning in bcc materials.

An approach for realistically simulating the performance of scientific applications on high performance computing systems

Scientific applications often contain large, computationally-intensive, and irregular parallel loops or tasks that exhibit stochastic behavior leading to load imbalance. Load imbalance often manifests during the execution of parallel scientific applications on large and complex high performance computing (HPC) systems. The extreme scale of HPC systems on the road to Exascale computing only exacerbates the loss in performance due to load imbalance. Dynamic loop self-scheduling (DLS) techniques are instrumental in improving the performance of scientific applications on HPC systems via load balancing. Selecting a DLS technique that results in the best performance for different problem and system sizes requires a large number of exploratory experiments. Currently, a theoretical model that can be used to predict the scheduling technique that yields the best performance for a given problem and system has not yet been identified. Therefore, simulation is the most appropriate approach for conducting such exploratory experiments in a reasonable amount of time. However, conducting realistic and trustworthy simulations of application performance under different configurations is challenging. This work devises an approach to realistically simulate computationally-intensive scientific applications that employ DLS and execute on HPC systems. The proposed approach minimizes the sources of uncertainty in the simulative experiments results by bridging the native and simulative experimental approaches. A new method is proposed to capture the variation of application performance between different native executions. Several approaches to represent the application tasks (or loop iterations) are compared to establish their influence on the simulative application performance. A novel simulation strategy is introduced that applies the proposed approach, which transforms a native application code into simulative code. The native and simulative performance of two computationally-intensive scientific applications that employ eight task scheduling techniques (static, nonadaptive dynamic, and adaptive dynamic) are compared to evaluate the realism of the proposed simulation approach. The comparison of the performance characteristics extracted from the native and simulative performance shows that the proposed simulation approach fully captured most of the performance characteristics of interest. This work shows and establishes the importance of simulations that realistically predict the performance of DLS techniques for different applications and system configurations.

Quantum interference effects in 1D parallel high-Tc SQUID arrays with finite inductance

The quantum interference effects of one-dimensional (1D) parallel arrays of high-temperature superconducting (HTS) SQUIDs were investigated experimentally and theoretically via the voltage–magnetic field responses for 4–81 Josephson junctions. The sensitivity of the arrays generally decreased as the number of junctions (and SQUIDs) in parallel increased, contrary to the predictions of models in the low (zero) inductance limit. A full theoretical description was developed to describe 1D parallel HTS SQUID arrays with finite inductances in an applied magnetic field, by extending the model for a single DC SQUID to multiple loops in parallel and including the flux generated by currents circulating through all loops in the array. Calculations were extended from SQUID arrays with equal loop areas to arrays with a distribution of loop areas, otherwise known as superconducting quantum interference filters. The model uses parameters relevant to HTS arrays, including typical variations (up to 30%) in HTS Josephson junction parameters, such as critical current and normal resistance. The effect of the location of the current biasing leads was also explored through the calculations. This model shows good agreement with experimentally measured 1D arrays of different lengths and highlights the importance of the geometry of the current biasing leads to the arrays when optimizing the array response.