Parallel Interconnection Research Articles

Evaluation Scheme for NoC-based CMP with Integrated Processor Management System

Evaluation Scheme for NoC-based CMP with Integrated Processor Management SystemWith the opportunities and benefits offered by Chip Multiprocessors (CMPs), there are many challenges that need to be addressed in order to exploit the full potential of CMPs. Such aspects as parallel programs, interconnection design, cache arrangement and on-chip cores allocation become a limiting factor. To ensure validity of approaches and research, we propose an evaluation system for CMPs with Network-on-Chip (NoC) and processor management system integrated on one die. The suggested experimentation system is described in details. The proposed system that is used for tests and results of the experiments are presented and discussed. As decision making criteria, we consider energy efficiency of Processor Allocator (PA) and NoC, as well as NoC traffic characteristic (load balance). In order to improve the system understanding, brief overview on most important NoC and PA architectures is also presented. Analyzed results reveal that CMP with a PA controlled by IFF allocation algorithm for mesh systems and torus-based NoC driven by DORLB routing with express-virtual-channel flow control achieved the best traffic balance and energy characteristic.

SPARE—A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction

This paper describes a flexible and efficient new algorithm for model order reduction of parameterized systems. The method is based on the reformulation of the parameterized system as a perturbation-like parallel interconnection of the nominal transfer function and the nonparameterized transfer function sensitivities with respect to the parameter variations. Such a formulation reveals an explicit dependence on each parameter which is exploited by reducing each component system independently via a standard nonparameterized structure preserving algorithm. Therefore, the resulting smaller size interconnected system retains the structure of the original system with respect to parameter dependence. This allows for better accuracy control, enabling independent adaptive order determination with respect to each parameter and adding flexibility in simulation environments. It is shown that the method is efficiently scalable and preserves relevant system properties such as passivity. The new technique can handle fairly large parameter variations on systems whose outputs exhibit smooth dependence on the parameters, also allowing design space exploration to some degree. Several examples show that besides the added flexibility and control, when compared with competing algorithms, the proposed technique can, in some cases, produce smaller reduced models with potential accuracy gains.

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.

The fabrication of efficiency-improved W-series interconnect type of module by balancing the performance of single cells

Large dye-sensitized solar cells (DSCs) are usually fabricated as module types instead of single cell types, because the overall efficiency of an area-expanded single DSC is decreased by its large surface resistances and low fill factor (FF). The general DSC module designs are the parallel grid, series interconnect, and series monolithic types. The W-series interconnect type of module has some advantages, such as its easy fabrication and simple structure. Moreover, it also avoids the reduction in the FF. However, it has an efficiency imbalance between the single cells, because of the discrepancy in their luminous intensity. Therefore, the fabrication of the W-series interconnect type of module will be cost-effective only if the problem of its efficiency imbalance is solved. In this study, the thickness of the Pt layer, which has a very high reflection rate, and that of the electrolyte layer are minimized and the transmitted light is reflected by a metallic thin film in order to increase the number of photons absorbed by the dye molecules in the module. As a result, the performance of the efficiency-balanced W-module is improved by approximately 1% as compared to that of the conventional module.

ArchSim: A System-Level Parallel Simulation Platform for the Architecture Design of High Performance Computer

High performance computer (HPC) is a complex huge system, of which the architecture design meets increasing difficulties and risks. Traditional methods, such as theoretical analysis, component-level simulation and sequential simulation, are not applicable to system-level simulations of HPC systems. Even the parallel simulation using large-scale parallel machines also have many difficulties in scalability, reliability, generality, as well as efficiency. According to the current needs of HPC architecture design, this paper proposes a system-level parallel simulation platform: ArchSim. We first introduce the architecture of ArchSim simulation platform which is composed of a global server (GS), local server agents (LSA) and entities. Secondly, we emphasize some key techniques of ArchSim, including the synchronization protocol, the communication mechanism and the distributed checkpointing/restart mechanism. We then make a synthesized test of some main performance indices of ArchSim with the phold benchmark and analyze the extra overhead generated by ArchSim. Finally, based on ArchSim, we construct a parallel event-driven interconnection network simulator and a system-level simulator for a small scale HPC system with 256 processors. The results of the performance test and HPC system simulations demonstrate that ArchSim can achieve high speedup ratio and high scalability on parallel host machine and support system-level simulations for the arhitecture design of HPC systems.

Development and Simulation of an Innovative Planar Stack Design-Combining a Solid Oxide Fuel Cell (SOFC) With an Allothermal Steam Reformer

Increasing energy demands, limited resources, pollutants, and CO2-emissions caused by the use of fossil fuels require a more efficient and sustainable energy production. Due to their high electrical efficiencies as well as fuel and application flexibilities, high temperature fuel cells offer great potential to meet the demands of the future energy supply. The fuel gases hydrogen and carbon monoxide, which are electrochemically convertible in solid oxide fuel cells (SOFCs), have to be generated by reformation or gasification of hydrocarbons, or in the case of pure hydrogen, as fuel gas, by electrolysis. For these generating processes energy is required. This generally leads to a deterioration of SOFC-system efficiencies. At state of the art combined processes, the reformation or gasification reactor and the SOFC are usually separated. The heat required for the endothermic reforming is generated by partial oxidation (POx) of the supplied fuel or by using the waste heat of the exhaust gases. At the Institute for Heat- and Fuel-Technology of the Technische Universität Braunschweig, an innovative planar SOFC-stack-design with indirect internal reforming and without bipolar plates was developed. Due to the thermal and material couplings, the SOFC-waste heat can be directly used to supply the endothermic reforming process. Additionally, a part of the hot anode off-gas, consisting mainly of water vapor, is recycled as a reforming agent. Therefore, based on the principle of the chemical heat pump, depending on the fuel used, system efficiencies of more than 60% can be achieved, even though the SOFC itself reached only an electrical efficiency of approximately 50%. Additionally, due to the cascaded SOFC structure resulting in high fuel utilization, postcombustion of the waste gases is no longer necessary. Because of the SOFC membrane allowing only an oxygen-ion flow and thus representing an air separation unit and the SOFC design without the mixing of anode and cathode flows, a simple CO2-separation can be realized by condensing the water vapor out of the anode off-gas. Another advantage of the newly developed stack design is its parallel interconnection, which leads to higher reliability concerning single stack levels. The aim of the work was a first dimensioning of the new stack design for natural gas as a fuel and its energetical analysis concerning operation and feasibility. With the simulation program developed, the theoretical feasibility of the concept and a high electrical efficiency of about 60% were proven.

High-Precision Digital-to-Analog Tunable Capacitors With Improved Quality Factor Using a Parallel Digital Actuator Array

We present a micromechanical digital-to-analog (DA) tunable capacitor using a parallel digital actuator array, which is capable of accomplishing high-precision tuning and quality factor improvement. The present DA tunable capacitor uses a parallel interconnection of digital actuators and thus achieves a low-resistive structure for wireless communications. Based on the criteria for the capacitance range (0.348-1.932 pF) and the actuation voltage (25 V), the present parallel DA tunable capacitor is estimated to have a quality factor that is 2.0 times higher than the previous serial-parallel DA tunable capacitor. In the experimental study, the parallel DA tunable capacitor changed the total capacitances from 2.268 to 3.973 pF (0.5 GHz), 2.384 to 4.197 pF (1.0 GHz), and 2.773 to 4.826 pF (2.5 GHz), thus achieving tuning ranges of 75.2%, 76.1%, and 74.0%, respectively. The capacitance precisions were measured to be 6.16 plusmn 4.24 fF (0.5 GHz), 7.42 plusmn 5.48 fF (1.0 GHz), and 9.56 plusmn 5.63 fF (2.5 GHz), which were 10 times higher than the precisions (> 100 fF) compared to the conventional analog tunable capacitors. The parallel DA tunable capacitor showed total resistances of 2.97 plusmn0.29 Omega (0.5 GHz), 3.01 plusmn0.42 Omega (1.0 GHz), and 4.32 plusmn0.66 Omega (2.5 GHz), resulting in quality factors measuring 33.7 plusmn 7.8 (0.5 GHz), 18.5 plusmn 4.9 (1.0 GHz), and 4.3 plusmn 1.4 (2.5 GHz) for large capacitance values (2.268-4.826 pF). We experimentally verified the high-precision tuning capability of the present parallel DA tunable capacitor with improved quality factor.

21113 稼働時のULSIにおいて多ビット配線まわりのlow-k材料に加わる熱応力の増大と危険性(配線技術,OS.3 機械工学が支援する微細加工技術(半導体,MEMS,NEMS))

Under the operation environment, the heat generation and the thermal stress of high performance integration circuits are considerably serious. Here, the thermal stress of low-k materials in the operating thermal environment is discussed from the point of view related to the parallel multi-bit interconnections. The maximum thermal stress of the low-k material for the multi-bit line is about four times that of the single line.

Spontaneous Nanoripple Formation on Metallic Templates

Nanoripple structures spontaneously formed at room temperature during chemical and electrochemical deposition of metals, semiconductors, and alloys on gold and copper templates, patterned with nanocavities, have been studied by atomic force microscopy (AFM) and scanning tunneling microscopy (STM). Annealing the templates at approximately equal to 373 K also results in ripple formation. Both experimental results and modeling, including anisotropic surface diffusion, demonstrate that nanocavity size in the template determines the ripple wavelength and amplitude, prior to a final stage of coarsening. Therefore, an ordered array of "nanodefects" introduced in the substrate is able to guide the self-organization of these nanofeatures during their growth, creating the possibility for nanofabrication of parallel interconnections with adjustable periodicity. Ripples are robust nanostructures that can in turn be used as templates for the preparation of hybrid nanostructured surfaces with specific physical properties.

Design of GRIN optical components for coupling and interconnects

AbstractThis paper reviews the design of some optical systems for coupling and interconnection by GRIN components. The optical systems designed with these components are based on imaging and transforming properties of such components to carry out specific functions. First of all, a brief description of light propagation through GRIN materials will be given. After that, a device to couple light by a GRIN fiber lens into fibers of different core sizes with low loss is described. The coupling efficiency as well as the coupling loss are studied versus variation of the GRIN fiber lens length and the refractive‐index profile of the coupler. The design of crossover and parallel interconnects by using a GRIN planar structure will be presented. The optical analysis includes the PSF for describing the performance of the device and the SBP for estimating the numbers of channels that can be handled. The dependence of the number of channels on the wavelength of light and the transverse aperture of the planar interconnect is shown.

Data Handling Limits of On-Chip Interconnects

With shrinking feature size and growing integration density in the deep sub-micrometer (DSM) technologies, the global buses are fast becoming the ldquoweakest-linksrdquo in VLSI design. They have large delays and are error-prone. Especially, in system-on-chip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This paper presents a two-fold approach for evaluating the signal and data carrying capacity of on-chip interconnects. In the first approach, the wire is modeled as a linear time invariant (LTI) system and a frequency response is studied. The second approach addresses delay and reliability in interconnects from an information theoretic perspective. Simulation results for an 8-bit-wide bus in 0.1-mum technology are presented for both approaches. The results closely match to a similar optimal bus clock frequency that will result in the maximum data transfer rate. Moreover, this optimal frequency is higher than that achieved by present day designs which accommodate the worst case delays. The first approach achieves this higher transmission rate using ideal signal shapes, instead of square pulses, while the second approach uses coding techniques to eliminate high delay cases to generate a higher transmission rate. It is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication theory, these ldquogoodrdquo signals arriving early can be used to predict/correct the ldquofewrdquo signals that arrive late.

Principal Component Analysis-Based Object Detection/Recognition Chip for Wireless Interconnected Three-Dimensional Integration

To develop image detection/recognition systems for various types of multiobjects that operate in real-time/real-world with small-size hardware and low-power dissipation, three-demensional (3-D) integration of multichips is required. We have designed a complementary metal oxide semiconductor (CMOS) test chip for object detection/recognition utilizing the processing algorithm based on the eigenface method and wireless chip-to-chip interconnections. Furthermore, a 3-D integration system was designed utilizing wireless chip-to-chip interconnections of parallel inductor-coupled local wireless interconnect (LWI) for 5.3 Gbps image data transfer, and antenna-coupled global wireless interconnect (GWI) for 500 Mbps clock and command distribution. With the prospect of realizing enhanced system performance using 0.18 µm CMOS chips, object detection/recognition times of 580 µs for detection and 4.2 µs for one-to-one recognition, and 40 giga operation per second (GOPS) processing capabilities at a 250 MHz clock frequency were obtained.

Performance of a Speculative Transmission Scheme for Scheduling-Latency Reduction

Low latency is a critical requirement in some switching applications, specifically in parallel computer interconnection networks. The minimum latency in switches with centralized scheduling comprises two components, namely, the control-path latency and the data-path latency, which in a practical high-capacity, distributed switch implementation can be far greater than the cell duration. We introduce a speculative transmission scheme to significantly reduce the average control-path latency by allowing cells to proceed without waiting for a grant, under certain conditions. It operates in conjunction with any centralized matching algorithm to achieve a high maximum utilization and incorporates a reliable delivery mechanism to deal with failed speculations. An analytical model is presented to investigate the efficiency of the speculative transmission scheme employed in a non-blocking N times NR input-queued crossbar switch with R receivers per output. Using this model, performance measures such as the mean delay and the rate of successful speculative transmissions are derived. The results demonstrate that the control-path latency can be almost entirely eliminated for loads up to 50%. Our simulations confirm the analytical results.

Formula omitted]-graphs: An efficient tool for constructing symmetric and semisymmetric graphs

Symmetric and semisymmetric graphs are used in many scientific domains, especially parallel computation and interconnection networks. The industry and the research world make a huge usage of such graphs. Constructing symmetric and semisymmetric graphs is a large and hard problem. In this paper a tool called G -graphs and based on group theory is used. We show the efficiency of this tool for constructing symmetric and semisymmetric graphs and we exhibit experimental results.

Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis

Xetal-II is a single-instruction multiple-data (SIMD) processor with 320 processing elements. It delivers a peak performance of 107 GOPS on 16-bit data while dissipating 600 mW. A 10 Mbit on-chip memory is provided which can store up to four VGA frames, allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3 Tbit/s to sustain the peak performance. The IC is realized in 90 nm CMOS and takes up 74 mm2.

Future generation supercomputers II

In part-I, a novel multi-core node architecture was proposed which when employed in a cluster environment would be capable of tackling computational complexity associated with wide class of applications. Furthermore, it was discussed that by appropriately scaling the architectural specifications, Teraops computing power could be achieved at the node level. In order to harness the computational power of such a node, we have developed an efficient application execution model with a competent cluster architectural backbone. In this paper we present the novel cluster paradigm, dealing with operating system design, parallel programming model and cluster interconnection network. Our approach in developing the competent cluster design revolves around an execution model to aid the execution of multiple applications simultaneously on all partitions of the cluster, leading to cost sharing across applications. This would be a major initiative towards achieving Cost-Effective Supercomputing.

A speculative transmission scheme for scheduling‐latency reduction

AbstractLow latency is a critical requirement in some switching applications, specifically in parallel computer interconnection networks. The minimum latency in switches with centralized scheduling comprises two components, namely, the control‐path latency and the data‐path latency, which in a practical high‐capacity, distributed switch implementation can be far greater than the cell duration. We introduce a speculative transmission scheme to significantly reduce the average control‐path latency by allowing cells to proceed without waiting for a grant, under certain conditions. It operates in conjunction with any centralized matching algorithm to achieve a high maximum utilization and incorporates a reliable delivery mechanism to deal with failed speculations. The speculative transmission scheme is employed in a non‐blocking N ×N R input‐queued crossbar switch with R receivers per output. The control‐path latency can be almost entirely eliminated for loads up to 50%. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Analytical Frequency-Dependent Model for Transmission Lines on RF-CMOS Lossy Substrates

Transmission lines (T-Lines) are widely used in millimeter wave applications on silicon-based complementary metal-oxide semiconductor (CMOS) technology. Accurate modeling of T-lines to capture the related electrical effects has, therefore, become increasingly important. This paper describes a method to model the capacitance and conductance of T-Lines on CMOS multilayer, lossy substrates based on conformal mapping, and region subdivision. Tests show that the line parameters (per unit length) obtained by the method are frequency dependent and very accurate. The method is also suitable for parallel multiconductor interconnect modeling for high frequency circuits.

Parallel, series, and intermediate interconnections of optical nanocircuit elements 2 Nanocircuit and physical interpretation

Applying the analytical closed-form solutions of the quasi-static potential distribution around two conjoined resonant half-cylinders with different permittivities, reported in the first part of this manuscript, here we interpret these results in terms of our nanocircuit paradigm applicable to nanoparticles at infrared and optical frequencies [Phys. Rev. Lett.95, 095504 (2005)]. We investigate the possibility of connecting in series and parallel configurations plasmonic and/or dielectric nanoparticles acting as nanocircuit elements, with a goal for the design of a more-complex nanocircuit system with the desired response. The present analysis fully validates the heuristic predictions regarding the parallel and series combination of a pair of nanocircuit elements depending on their relative orientation with respect to the field polarization. Moreover, the geometries under analysis present interesting peculiar features in their wave interaction, such as an intermediate stage between the parallel and series configurations, which may be of interest for certain applications. In particular, the resonant nanocircuit configuration analyzed here may dramatically change, in a continuous way, its effective total impedance by simply rotating its orientation with respect to the polarization of the impressed optical electric field, providing a novel optical nanodevice that may alter its function by rotation with respect to the impressed optical local field.

Parallel, series, and intermediate interconnections of optical nanocircuit elements 1 Analytical solution

Following our recent development of a paradigm for extending the classic concepts of circuit elements to the infrared and optical frequencies [Phys. Rev. Lett.95, 095504 (2005)], in this paper we investigate the possibility of connecting nanoparticles in series and in parallel configurations, acting as nanocircuit elements. In particular, here we analyze a pair of conjoined half-cylinders whose relatively simple geometry may be studied and analyzed analytically. In this first part of this work, we derive a novel closed-form quasi-static analytical solution of the boundary-value problem associated with this geometry, which will be applied in Part 2 for a nanocircuit and physical interpretation of these results.