Parallel Hardware Platform Research Articles

A parallel computing architecture based on cellular automata for hydraulic analysis of water distribution networks

Water distribution networks (WDNs) are one of the largest infrastructures in society. Various methods for formulation and hydraulic analysis of water distribution networks, including numerical and non-numerical methods, have been previously proposed. Due to the complexity, the nonlinearity of the hydraulic equations of water distribution networks, and the need for multiple executions and uncertainties in parameters, solving the hydraulic model of water distribution networks has high time complexity. In this paper, a parallel computational architecture based on the concept of cellular automata is proposed to accelerate the numerical solution of the steady-state water distribution network model. Taylor series is proposed to solve hydraulic equations. The presented architecture was implemented as a parallel hardware platform on a field-programmable gate array. The performance of the proposed method was compared with EPANET software for networks with different complexities and topologies. The results show that the proposed parallel algorithm can accelerate the hydraulic analysis of regular water distribution networks up to 700 times and 250 times for small and large networks, respectively.

Inter-domain routing for communication networks using Hierarchical Hopfield Neural Networks

This paper presents the Hierarchical Hopfield Neural Networks (HHNN). HHNN is a novel Hopfield Neural Network (HNN) approach. HHNN is composed of a hierarchy of self-sufficient HNNs, aiming to reduce the neural network structure and mitigate convergence problems. The HNNN composition depends on the applied problem. In this paper, the problem approached is the inter-domain routing for communication networks. Thus, the hierarchy of HNNs mimics the structure of communication networks (domains, nodes, and links). The proof of concept and the comparison between HNNN with the state-of-art HNN occurs using an implementation of them in the Java programming language. Besides, the performance analysis of the HHNN runs on a parallel hardware platform, using VHDL to develop it. The results have demonstrated a reduction of 93.75% and 99.98% in the number of neurons and connections to build the neural network, respectively. Furthermore, the mean time to achieve convergence of HHNN is rough 1.52% of the total time needed by the current state-of-art HNN approach. It is also less susceptible to early convergence problems when used in communications networks with a large number of nodes. Last, but not least, the VHDL implementation shows that convergence time of HHNN is comparable to routing algorithms used in practical applications.

A parallel function evaluation approach for solution to large-scale equation-oriented models

Abstract The equation-oriented (EO) approach is widely used for process simulation and optimization. Nevertheless, large-scale EO models consist of a huge number of nonlinear equations and make the solution procedure a challenging and time-consuming task. For most gradient-based numerical algorithms, function evaluations are the dominant step during the solution procedure. Here, a parallel computation method is developed for function evaluations within EO optimization strategies. After dividing the equations into several groups, function evaluations are calculated by using multiple threads on a parallel hardware platform simultaneously. Theoretical analysis for the speedup ratio is conducted. The implementation of the proposed method on a multi-core processor platform as well as a graphics processing unit (GPU) platform is then presented with several case studies. Numerical results are compared and discussed to show that the multi-core processor implementation has good computational performance, whereas the GPU implementation only achieves computational acceleration under relatively specific conditions.

Real-Time Fabric Defect Detection Using Accelerated Small-Scale Over-Completed Dictionary of Sparse Coding

An auto fabric defect detection system via computer vision is used to replace manual inspection. In this paper, we propose a hardware accelerated algorithm based on a small-scale over-completed dictionary (SSOCD) via sparse coding (SC) method, which is realized on a parallel hardware platform (TMS320C6678). In order to reduce computation, the image patches projections in the training SSOCD are taken as features and the proposed features are more robust, and exhibit obvious advantages in detection results and computational cost. Furthermore, we introduce detection ratio and false ratio in order to measure the performance and reliability of the hardware accelerated algorithm. The experiments show that the proposed algorithm can run with high parallel efficiency and that the detection speed meets the real-time requirements of industrial inspection.

An FPGA Implementation of an Investment Strategy Processor

A special purpose processing element is described which can be used to optimize an investment strategy for financial securities. It has been used to configure the FPGAs of the massively parallel hardware platform RIVYERA. Using this configuration, the compute intensive part of the technical analysis of financial markets can be accelerated with a speedup of more than 17,000 compared to a high-performance PC.

Parallel adaptive mesh generation and decomposition

An important class of methodologies for the parallel processing of computational models defined on some discrete geometric data structures (i.e. meshes, grids) is the so calledgeometry decomposition or splitting approach. Compared to the sequential processing of such models, the geometry splitting parallel methodology requires an additional computational phase. It consists of the decomposition of the associated geometric data structure into a number of balancedsubdomains that satisfy a number of conditions that ensure the load balancing and minimum communication requirement of the underlying computations on a parallel hardware platform. It is well known that the implementation of the mesh decomposition phase requires the solution of a computationally intensive problem. For this reason several fast heuristics have been proposed. In this paper we explore a decomposition approach which is part of a parallel adaptive finite element mesh procedure. The proposed integrated approach consists of five steps. It starts with a coarse background mesh that isoptimally decomposed by applying well known heuristics. Then, the initial mesh is refined in each subdomain after linking the new boundaries introduced by its decomposition. Finally, the decomposition of the new refined mesh is improved so that it satisfies the objectives and conditions of the mesh decomposition problem. Extensive experimentation indicates the effectiveness and efficiency of the proposed parallel mesh and decomposition approach.