Parallel Filter Structure Research Articles

AREA REDUCTION TECHNIQUES FOR PARALLEL FIR FILTER WITH SYMMETRIC COEFFICIENTS.

The objective of the paper is to reduce the hardware complexity of higher order FIR filter with symmetric coefficients. The aim is to design efficient Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure with the constraint that the filter tap must be a multiple of 2. The parallel FIR filter structure based on proposed FFA technique has been implemented based on carry save and ripple carry adder for further optimization. The reduction in silicon area complexity is achieved by eliminating the bulky multiplier with an adder namely ripple carry and carry save adder. For example, for a 6-parallel 1024-tap filter, the proposed structure saves 14 multipliers at the expense of 10 adders, whereas for a six-parallel 512-tap filter, the proposed structure saves 108 multipliers at the expense of 10 adders. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR filter, especially when the length of the filter is very large.

Comparative Analysis of Design Methodologies for Parallel FIR Filter

The importance of DSP systems with low power, low area and high performance appear to be increasing with no visible sign of saturation. Digital filters play a vital role in digital systems where Finite Impulse Response (FIR) filters are one of the most widely used fundamental devices. This review paper deal with the design and implementation of parallel FIR filter structure on FPGA using 4 different parallel processing methodologies with minimal cost of hardware. Since adders have no effect to the filter length and occupy less area than the multipliers, here multipliers are exchanged with adders. The paper hence describes the comparative performance analysis of traditional parallel FIR filter with respect to the FFA, transposition and symmetric convolution based parallel FIR filter with featuring the advantage of reduced hardware complexity to accurate processing with conservation of filter dynamic.

Linear-Phase VDF Design With Unabridged Bandwidth Control Over the Nyquist Band

This brief presents a low-complexity linear-phase variable digital filter (VDF) design with tunable lowpass (LP), highpass (HP), bandpass (BP), and bandstop (BS) responses anywhere over the entire Nyquist band. The spectral-parameter-approximation-based VDFs (SPA-VDFs) was designed using the Farrow structure and has advantages of linear phase, lower group delay, and fewer variable multipliers. However, the total gate count and the dynamic range of filter coefficient values of SPA-VDFs significantly increase with the tunable range of cutoff frequency, which limits their usefulness in emerging signal processing and wireless communication applications. In addition, existing VDFs need to update either filter coefficients or need parallel filter structures to obtain variable LP, HP, BP and BS responses. In this brief, a new VDF design is proposed by deftly integrating SPA-VDF with the modified coefficient decimation method (MCDM), and it will be referred to as SPA-MCDM-VDF. The SPA-MCDM-VDF provides LP, HP, BP, and BS responses with unabridged center frequency and bandwidth control over the entire Nyquist band without the need for hardware reimplementation or coefficient update. The complexity comparisons show that the SPA-MCDM-VDF offers substantial savings in gate count, group delay, and number of variable multiplications over other linear-phase VDFs.

A Novel Fast FIR Algorithm for Area-Efficient Parallel FIR Digital Filter Structures Utilizes Symmetric Convolutions

Based on fast finite-impulse response (FIR) algorithms (FFAs), this paper proposes new parallel FIR filter structures, which are beneficial to symmetric coefficients in terms of the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. The proposed parallel FIR structures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in sub filter section at the expense of additional adders in preprocessing and post processing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area; in addition, the overhead from the additional adders in preprocessing and post processing blocks stay fixed and do not increase along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a four-parallel 72-tap filter, the proposed structure saves 27 multipliers at the expense of 11 adders, whereas for a four-parallel 576-tap filter, the proposed structure saves 216 multipliers at the expense of 11 adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolutions from the existing FFA parallel FIR filter, especially when the length of the filter is large

Efficient Complexity Reduction Technique for Parallel FIR Digital Filter based on Fast FIR Algorithm

The objective of the paper is to reduce the hardware complexity of higher order FIR filter with symmetric coefficients. The aim is to design efficient Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure with the constraint that the filter tap must be a multiple of 2. In our work we have briefly discussed for L = 4 parallel implementation. The parallel FIR filter structure based on proposed FFA technique has been implemented based on carry save and ripple carry adder for further optimization. The reduction in silicon area complexity is achieved by eliminating the bulky multiplier with an adder namely ripple carry and carry save adder. For example, for a 6-parallel 1024-tap filter, the proposed structure saves 14 multipliers at the expense of 10 adders, whereas for a six-parallel 512-tap filter, the proposed structure saves 108 multipliers at the expense of 10 adders. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR filter, especially when the length of the filter is very large.

A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation

Evaluating the previous work is an important part of developing new hardware efficient methods for the implementation of DWT through Lifting schemes. The aim of this paper is to give a review of VLSI architectures for efficient hardware implementation of wavelet lifting schemes. The inherent in place computation of lifting scheme has many advantages over conventional convolution based DWT. The architectures are represented in terms of parallel filter, row column, folded, flipping and recursive structures. The methods for scanning of images are the line-based and the block-based and their characteristics for the given application are given. The various architectures are analyzed in terms of hardware and timing complexity involved with the given size of input image and required levels of decomposition. This study is useful for deriving an efficient method for improving the speed and hardware complexities of existing architectures and to design a new hardware implementation of multilevel DWT using lifting schemes.

Performance Analysis of Parallel FIR Digital Filter using VHDL

With the continuing trends to reduce the chip size and integrates multichip solution into a single chip solution it is important to limit the silicon area required to implement parallel FIR digital filter in VLSI implementation. The Need for high performance and low power digital signal processing is getting increased. Finite Impulse Response (FIR) filters are one of the most widely used fundamental devices performed in DSP system. This paper presents the performance analysis of parallel FIR digital filter, In this paper, Traditional FIR filter structure and FFA based FIR filter structure and symmetric convolution based FFA FIR filter are designed for 2-parallel filter (2*2). These entire filter structures are designed based on Carry Save Adder (CSA) and Ripple Carry Adder (RCA).Exchanging multipliers with adder is advantageous because adders weight less then multipliers in terms of silicon area. The performance of parallel FIR filter structure based on Ripple Carry Adder and Carry Save Adder will be compared.

Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm

Based on fast finite-impulse response (FIR) algorithms (FFAs), this paper proposes new parallel FIR filter structures, which are beneficial to symmetric coefficients in terms of the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. The proposed parallel FIR structures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in subfilter section at the expense of additional adders in preprocessing and postprocessing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area; in addition, the overhead from the additional adders in preprocessing and postprocessing blocks stay fixed and do not increase along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a four-parallel 72-tap filter, the proposed structure saves 27 multipliers at the expense of 11 adders, whereas for a four-parallel 576-tap filter, the proposed structure saves 216 multipliers at the expense of 11 adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolutions from the existing FFA parallel FIR filter, especially when the length of the filter is large.

Detecting Multiple failures in GPS/INS integrated system: A Novel architecture for Integrity Monitoring

GPS is a widely used satellite navigation system. By design, there is no provision for real time integrity information within the Standard Positioning Service (SPS) which is available to the civilian community. However, in safety critical sectors like aviation, stringent integrity performance requirements must be met. This can be achieved using the GIC (GPS Integrity Channel) or RAIM (Receiver Autonomous Integrity Monitoring) or both. RAIM, the most cost effective method relies on data consistency, and therefore requires redundant measurements for its operation. An external aid to provide this redundancy can be in the form of an Inertial Navigation system (INS). This should enable continued performance even during RAIM holes. RAIM algorithms have traditionally been designed for the situation when only one failure occurs at a time. However, due to tighter alert limits and usage of GPS in urban environments there is now a focus on extending the RAIM concept to include multiple failures. Furthermore, in aviation, detection of simultaneous multiple slowly growing errors (SGE) is very challenging particularly in the case of integrated GPS/INS systems. This paper provides a detailed survey of RAIM approaches used to detect multiple failures proposed by navigation and geodesy communities. Furthermore the paper extends a previous algorithm proposed by the authors for the detection of a single SGE to the simultaneous multiple failure case for stand-alone GPS and integrated GPS/INS systems. Simulated and real data results attest to the effectiveness of the approach proposed. The developed algorithm is successful in the detection of multiple failures in GPS as well as in the INS. Furthermore isolation of the faulty sensor (GPS or INS) is possible with the same parallel filter structure. Hence, this approach will enhance the integrity of a GPS/INS integrated system installed on an aircraft.

Passive admittance synthesis for sound synthesis applications

In physics‐based sound synthesis, it is in general possible to incorporate a mechanical or acoustical admittance/impedance in the form of a digital filter. Examples include modeling of the termination of a string or a tube. However, when digital filters are fitted to measured admittance or impedance data, care has to be taken that the resulting filter corresponds to a passive mechanical or acoustical system, otherwise the stability of the instrument model is at risk. This paper presents a simple method for designing inherently passive admittance or impedance filters. The admittance/impedance is composed as a linear combination of positive real (PR) functions, and the weights are determined by a constrained least squares optimization. The resulting filter is a parallel set of second‐order sections. For wave‐based modeling, such as digital waveguides (DWGs) or wave digital filters (WDFs), the admittance/impedance is converted to a reflectance filter. The parallel filter structure is retained during conversi...

A wavelet-VQ system for real-time video compression

This paper presents a scheme and its Field Programmable Gate Array (FPGA) implementation for a system based on combining the bi-dimensional discrete wavelet transformation (2D-DWT) and vector quantization (VQ) for image compression. The 2D-DWT works in a non-separable fashion using a parallel filter structure with distributed control to compute two resolution levels. The wavelet coefficients of the higher frequency sub-bands are vector quantized using multi-resolution codebook and those of the lower frequency sub-band at level two are scalar quantized and entropy encoded. VQ is carried out by self organizing feature map (SOFM) neural nets working at the recall phase. Codebooks are quickly generated off-line using the same nets functioning at the training phase. The complete system, including the 2D-DWT, the multi-resolution codebook VQ, and the statistical encoder, was implemented on a Xilinx Virtex 4 FPGA and is capable of performing real-time compression for digital video when dealing with grayscale 512 × 512 pixels images. It offers high compression quality (PSNR values around 35 dB) and acceptable compression rate values (0.62 bpp).

A Method for Reduced Finite Precision Effects in Parallel Filtering Echo Cancellation

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The two-path algorithm is an adaptive filter algorithm based on a parallel filter structure, which has been found to be useful for line echo cancellation as well as for acoustic echo cancellation. It is well known that in finite precision arithmetic, the adaptation process of adaptive algorithms can be reduced or even halted due to finite precision effects. This paper proposes a variant of the two-path scheme where the effects of quantization are reduced, without any significant increase in complexity. The improvement is shown by simulations using bandlimited flat spectrum noise as well as real speech signals. </para>

Low- Cost Parallel FIR Filter Structures With 2-Stage Parallelism

Based on recently published low-complexity parallel finite-impulse response (FIR) filter structures, this paper proposes a new parallel FIR Filter structure with less hardware complexity. The subfilters in the previous parallel FIR structures are replaced by a second stage parallel FIR filter. The proposed 2-stage parallel FIR filter structures can efficiently reduce the number of required multiplications and additions at the expense of delay elements. For a 32-parallel 1152-tap FIR filter, the proposed structure can save 5184 multiplications (67%), 2612 additions (30%), compared to previous parallel FIR structures, at the expense of 10089 delay elements (-133%). The proposed structures will lead to significant hardware savings because the hardware cost of a delay element is only a small portion of that of a multiplier, not including the savings in the number of additions

A robust transform domain echo canceller employing a parallel filter structure

The proper control of acoustic echoes is of vital significance in modern communication systems. Acoustic echoes are commonly combatted by means of acoustic echo cancellation. A critical issue in acoustic echo cancellation is the control of adaptation of the echo cancellation filter with the possible presence of near-end speech activities. In this paper, a novel echo cancellation structure is proposed. The proposed structure makes use of two parallel adaptive filters. Echo of the two parallel adaptive filters is tailored for a specific operating situation. By so doing, the contradicting requirements of robustness against near-end disturbance and fast convergence and tracking speed are achieved simultaneously.

A Novel FPGA Architecture of a 2-D Wavelet Transform

This paper presents a new architecture for implementing a two-dimensional Discrete Wavelet Transform (2-D DWT). This architecture works in a non-separable fashion using a parallel filter structure with distributed control to compute all the DWT resolution levels. The architecture is modular and scalable in its totality. In this way, the input sample can be processed at the rate of one sample per clock cycle. To compute an N × N still image with a filter length L, N2?+?N clock cycles and 4.5N memory storage cells are required. Implementation results based on a Xilinx Virtex FPGA device are included.

Possible solution of parallel FIR filter structure

In this paper, a parallel form FIR adaptive filter structure with RLS (Recursive Least Squares) type adaptive algorithm is proposed. The proposed parallel form FIR structure consists of a recursive orthogonal transform stage and sparse FIR sub filters operating in parallel. The adaptive algorithm used to update coefficient vector of the sparse filters is implemented by using modified Hopfield networks. This structure implements the RLS-type adaptive algorithm, without an explicit matrix inversion avoiding numerical instability problems. Simulation results which show the desirable features of proposed structure are given.

Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices

This paper presents a flexible filter and control unit structure for implementing different VLSI architectures on two-dimensional DWT. These structures are applied over three different architectures: a direct approach, Recursive Pyramidal Algorithm (RPA) architecture, and a new proposed modification of RPA. This modified architecture works in a non-separable fashion using a parallel filter structure with distributed control to compute all the DWT resolution levels. It is fully modular and scalable, with low latency and high throughput performance. Implementation results based on a Virtex-II FPGA device are included. Real-time video processing is achieved.

Low-Area/Power Parallel FIR Digital Filter Implementations

This paper presents a novel approach for implementing area-efficient parallel (block) finite impulse response (FIR) filters that require less hardware than traditional block FIR filter implementations. Parallel processing is a powerful technique because it can be used to increase the throughput of a FIR filter or reduce the power consumption of a FIR filter. However, a traditional block filter implementation causes a linear increase in the hardware cost (area) by a factor of L, the block size. In many design situations, this large hardware penalty cannot be tolerated. Therefore, it is important to design parallel FIR filter structures that require less area than traditional block FIR filtering structures. In this paper, we propose a method to design parallel FIR filter structures that require a less-than-linear increase in the hardware cost. A novel adjacent coefficient sharing based sub-structure sharing technique is introduced and used to reduce the hardware cost of parallel FIR filters. A novel coefficient quantization technique, referred to as a scalable maximum absolute difference (MAD) quantization process, is introduced and used to produce quantized filters with good spectrum characteristics. By using a combination of fast FIR filtering algorithms, a novel coefficient quantization process and area reduction techniques, we show that parallel FIR filters can be implemented with up to a 45% reduction in hardware compared to traditional parallel FIR filters.

PARALLEL COMPUTING IN MULTIDIMENSIONAL RECURSIVE FILTERING

This paper introduces and generalizes a number of multidimensional (MD) recursive parallel filter algorithms, which are based on the principles of orthogonal and diagonal computing, respectively. Efficient software and hardware implementation methods for the proposed parallel algorithms are presented. In particular, it is shown that systolic array implementations can be achieved for MD parallel filter structures that are locally interconnected and have a critical path of 1 multiplication plus 1 addition. In this way, the proposed parallel filters are easily able to perform real-time processing at video rates.

Noise cancellation using parallel adaptive filters

The development of adaptive noise cancellers based on the reference microphone approach proposed by B. Widrow et al. (1975) is presented. It is shown that the use of multiple reference microphones improves the performance of noise cancelers in a multipath, multisource noise environment commonly found in an automobile. Cancellation based on subbands of the reference signals and the structure of the canceler are shown to improve the ability of the canceler to track nonstationary noise processes. The authors compare various parallel multireference filter structures using noise recorded in an automobile to show that a two-stage canceler using a precorrelation stage followed by a beamforming stage provides noise reduction at all frequencies in the telephone audio band with a maximum reduction of 28 dB and an average reduction of 16 dB. >