Parallel Fault Simulation Research Articles

Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System

Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System

Assessing the Effectiveness of Different Test Approaches for Power Devices in a PCB

Power electronic systems using printed circuit boards (PCBs) are broadly used in many applications, including some safety-critical ones. Several standards (e.g., ISO26262 for the automotive sector and DO-178 for avionics) mandate the adoption of effective test procedures for all electronic systems. However, the metrics to be used to compute the effectiveness of the adopted test procedures are not so clearly defined for power devices and systems. In the past years, some commercial fault simulation tools (e.g., DefectSim by Mentor Graphics and TestMAX by Synopsys) for analog circuits have been introduced, together with some new fault models. With these new tools, systematic analog fault simulation finally became practically feasible. The aim of this article is twofold: first, we propose a method to extend the usage of the new analog fault models to power devices, thus allowing to compute a fault coverage figure for a given test. Second, we adopt the method on a case study, for which we quantitatively evaluate the effectiveness of some test procedures commonly used at the PCB level for the detection of faults inside power devices. A typical power supply unit (PSU) used in industrial products, including power transistors and power diodes, is considered. The analysis of the gathered results shows that using the new method we can identify the main points of strength/weakness of the different test solutions in a quantitative and deterministic manner and pinpoint the faults escaping to each one.

SWIFT: Switch-Level Fault Simulation on GPUs

Current nanometer CMOS circuits show an increasing sensitivity to deviations in first-order parameters and suffer from process variations during manufacturing. To properly assess and support test validation of digital designs, low-level fault simulation approaches are utilized to accurately capture the behavior of CMOS cells under parametric faults and process variations as early as possible throughout the design phase. However, low-level simulation approaches exhibit a high computational complexity, especially when variation has to be taken into account. In this paper, a high-throughput parallel fault simulation at switch level is presented. First-order electrical parameters are utilized to capture CMOS-specific functional and timing behavior of complex cells allowing to model faults with transistor granularity and without the need of logic abstraction. Furthermore, variation modeling in cells and transistor devices enables broad and efficient variation analyses of faults over many circuit instances for the first time. The simulation approach utilizes massive parallelization on graphics processing units by exploiting parallelism from cells, stimuli, faults, and circuit instances. Despite the lower abstraction levels of the approach, it processes designs with millions of gates and outperforms conventional fault simulation at logic level in terms of speed and accuracy.

Improving Time-Efficiency of Fault-Coverage Simulation for MOS Analog Circuit

In analog fault simulation, the number one challenge is that simulation time could grow rapidly and become prohibitive as the circuit size becomes large. This paper proposes a systematic method to significantly improve the time efficiency in estimating the fault coverage for analog fault simulation. In the proposed method, a circuit under test (CUT) is first partitioned into independent sub-circuits. This is accomplished through mapping the circuit into a graph, decomposing the graph into strongly connected components (SCCs), and generating a sub-circuit for each SCC. The impacts of potential faults directly entering a sub-circuit are then simulated and recorded using the sub-circuits, which is expected to be much more time efficient than fault simulation using the whole circuit, which is much larger in size. Finally, the fault detectability at the given test points is evaluated based on the fault impacts and sensitivity among different sub-circuits. As a first step toward quick estimation of fault coverage, this paper focuses on dc tests. Simulation results show that the fault coverage of dc tests can be estimated sufficiently accurately with simulation time being reduced by 10X for the benchmark circuit, or by approximately the number of SCCs. For a much larger circuit, the number of SCCs is expected to be much larger and the time-saving factor will be much larger.

Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation

Shared-memory systems enable parallel computing for the automatic test pattern generation (ATPG). Although the existing techniques for parallel ATPG reach near-linear speedup, test inflation becomes a common problem in its practicality. Therefore, this paper proposes a multi-threaded test pattern generation called MT-TPG that can suppress test inflation and accelerate fault processing, simultaneously, to retain high parallelism. For suppressing test inflation, hard-fault shuffling ( HFS ) and concurrent-fault interruption ( CFI ) are involved to avoid repeated detection of the same fault among different threads. For accelerating fault processing, the potentially-droppable-fault removal ( PDFR ) and single-pattern parallel-fault simulation ( SPPFSim ) collectively drop not-yet-detected faults as early as possible for shortening the overall execution time of ATPG. According to our experimental results, the HFS and CFI can successfully suppress test inflation to PDFR and SPPFSim can achieve 13.7X speedup using 16 threads on average. As a result, MT-TPG is proven effective at unleashing parallelism with minimal test inflation on shared-memory systems.

3-D Parallel Fault Simulation With GPGPU

General purpose computing on graphical processing units (GPGPU) is a paradigm shift in computing that promises a dramatic increase in performance. GPGPU also brings an unprecedented level of complexity in algorithmic design and software development. In this paper, we present an efficient parallel fault simulator, FSimGP2, that exploits the high degree of parallelism supported by a state-of-the-art graphic processing unit (GPU) with the NVIDIA compute unified device architecture. A novel 3-D parallel fault simulation technique is proposed to achieve extremely high computation efficiency on the GPU. Global communication is minimized by concentrating as much work as possible on the local device's memory. We present results on a GPU platform from NVIDIA (a GeForce GTX 285 graphics card) that demonstrate a speedup of up to 63× and 4× compared to two other GPU-based fault simulators and up to 95× over a state-of-the-art algorithm on conventional processor architectures.

Fault Table Computation on GPUs

In this paper, we explore the implementation of fault table generation on a Graphics Processing Unit (GPU). A fault table is essential for fault diagnosis and fault detection in VLSI testing and debug. Generating a fault table requires extensive fault simulation, with no fault dropping, and is extremely expensive from a computational standpoint. Fault simulation is inherently parallelizable, and the large number of threads that a GPU can operate on in parallel can be employed to accelerate fault simulation, and thereby accelerate fault table generation. Our approach, called GFTABLE, employs a pattern parallel approach which utilizes both bit-parallelism and thread-level parallelism. Our implementation is a significantly modified version of FSIM, which is pattern parallel fault simulation approach for single core processors. Like FSIM, GFTABLE utilizes critical path tracing and the dominator concept to reduce runtime. Further modifications to FSIM allow us to maximally harness the GPU's huge memory bandwidth and high computational power. Our approach does not store the circuit (or any part of the circuit) on the GPU. Efficient parallel reduction operations are implemented in our implementation of GFTABLE. We compare our performance to FSIM*, which is FSIM modified to generate a fault table on a single core processor. Our experiments indicate that GFTABLE, implemented on a single NVIDIA Quadro FX 5800 GPU card, can generate a fault table for 0.5 million test patterns on average 15.68× faster when compared with FSIM*. With the NVIDIA Tesla server, our approach would be potentially 89.57× faster.

Structural Fault Modeling and Fault Detection Through Neyman–Pearson Decision Criteria for Analog Integrated Circuits

A new approach for analog fault modeling and simulation is presented. The proposed approach utilizes the sensitivity of the circuit's DC node voltages to the process variations and consequently the...

Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE

This paper presents results on fault simulation and response compaction on ISCAS 89 full scan sequential benchmark circuits using HOPE-a fault simulator developed for synchronous sequential circuits that employs parallel fault simulation with heuristics to reduce simulation time in the context of designing space-efficient support hardware for built-in self-testing of very large-scale integrated circuits. The techniques realized in this paper take advantage of the basic ideas of sequence characterization previously developed and utilized by the authors for response data compaction in the case of ISCAS 85 combinational benchmark circuits, using simulation programs ATALANTA, FSIM, and COMPACTEST, under conditions of both stochastic independence and dependence of single and double line errors in the selection of specific gates for merger of a pair of output bit streams from a circuit under test (CUT). These concepts are then applied to designing efficient space compression networks in the case of full scan sequential benchmark circuits using the fault simulator HOPE.

Concurrent analogue fault simulation, the equation formulation aspect

AbstractFault simulation is an essential tool for developing test patterns for circuits. Because the potential number of faults in a circuit is potentially very large, computational efficiency is an important consideration. In the digital domain, concurrent fault simulation is well‐established as an efficient tool. For analogue circuits, fault simulation is often performed by repeated insertion of possible faults and resimulation of the circuit. Consequently, methods for efficient concurrent analogue fault simulation are attracting attention. A review of existing methods of concurrent analogue fault simulation shows that most are based on a similar fundamental perturbation of the original fault‐free circuit equations, although the methods differ in the procedure applied after the circuit equations are formulated. We develop here a comprehensive set of element stamps, describing faulty elements, enabling effective and routine equation formulation for faulty circuits. These may be used no matter what method of fault simulation is later applied. These stamps are used in a new technique for concurrent analogue fault simulation, based on modified nodal analysis. A significant improvement in efficiency, compared with other methods, is demonstrated. Copyright © 2004 John Wiley & Sons, Ltd.

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.

Concurrent transient fault simulation for analog circuits

This paper presents a novel concurrent fault simulation algorithm for nonlinear analog circuits. Between successive time steps in transient fault simulation, all faulty circuits in the fault list are simulated before the simulator proceeds to the next step. Four primary techniques, including fault grouping, fault ordering, state prediction, and reduced-order fault matrix computation, are proposed to significantly reduce analog fault simulation complexity by making use of the similarities between the faulty and fault-free circuits. The method has been implemented in a dc and transient fault simulator called CONCERT2, which is the first ever for nonlinear analog circuits. Up to two orders of magnitude speedup is obtained for complete transient fault simulation, without loss of accuracy in fault detection. It is shown that the methodology of CONCERT2 can significantly speed up the process of analog test stimulus generation.

Building an analogue fault simulation tool and its application to MEMS

Microsystems are rapidly evolving from individual transducer components into highly integrated complete systems on the same chip. Conceiving these devices requires significant changes in the design and test flow. Computer-Aided Design (CAD) tools and validation procedures are to be created and prepared to face the new challenge. So far, very little work has been done to ease the burden of testing highly integrated transducers. This paper first looks into the design and test flow for these new systems. Next it presents a tool that is currently being developed in order to make possible the extensive fault simulation of Microsystems, concerning the transducer and the electronic parts as well. A Fault Model Description Language (FMDL) is proposed. The FMDL is expected to deal gracefully with this task, taking into account the specific requirements of non-electronic parts but keeping compatibility with an Integrated Circuit CAD environment.

Multi-level hierarchical analogue fault simulation

In this paper the extensions of our analogue fault simulator ‘aFSIM’ to a multi-level hierarchical analogue fault simulation tool are described. Due to these extensions it is now possible to fault-simulate larger analogue circuits. In addition mixed-signal circuits including a not too large amount of digital circuitry can also be fault-simulated. The term ‘multi-level hierarchical analogue fault simulation’ comprises the usage of behavioural models for components together with components described at the transistor-level, fault injection at different abstraction levels, and a hierarchically handling of both different descriptions of the circuit components and faults during the fault simulation process. Multi-level hierarchical analogue fault simulation is an important means to tackle the complexity of analogue circuits for providing test signals with a high fault and defect coverage.

A novel simulation technique for testing analog ICs

The increasing demand for reliable and high quality mixed-signal integrated circuits necessitates a defect-oriented testing methodology. Thereby fault simulation (FS) is essential for test stimuli generation and test quality assessment. Due to the high computational effort needed, analog FS is becoming a critical factor in testing mixed-signal ICs. This paper provides a new accelerated FS approach. It is based on an improved application of the Newton–Raphson method in the analysis of similarly behaving circuits. Metrics for measuring circuits' behavior similarity are presented. The new techniques are implemented in an experimental FS tool. For sample circuits, experimental results are presented and discussed.

Fault Modeling and Fault Simulation in Mixed Micro-Fluidic Microelectronic Systems

Developments in electronic/fluidic microsystems are progressing rapidly. The ultimate goal is to deliver products in the 10,000 fluidic reaction-wells range. Exciting applications include massive parallel DNA analysis and automatic drug synthesis. Until now, only functional testing has been used to “guarantee” the quality of micro-fluidic systems after manufacturing. In this paper, defect-oriented test approaches developed in analogue fault modeling and simulation have been used to predict for the first time the faulty behavior of micro-electronic fluidic microsystems. The modeling is targeted for use in complex electronic/fluidic microsystems employing commercial microsystem CAD tools. It enables a measure for the quality of these systems based on the performed (functional) tests and can be a guide for future test-stimuli generation and yield prediction.

Closing the gap between analog and digital testing

This paper presents a highly effective method for parallel hard fault simulation and test-specification development. The proposed method formulates the fault-simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs. This approach, extended by parametric fault testing, has been implemented as an automated tool set for integrated circuit (IC) testing.

Applying mutual information theory to behavioural analogue fault modelling

To assess the effectiveness of a testing strategy for an integrated circuit, the potential structural faults in a circuit must be modelled. Analogue fault simulation is conventionally done at the transistor level. Behavioural fault models are desirable to speed up the simulations. Behavioural fault modelling needs faults to be grouped. However, it is not easy to group faults using a Euclidean measurement of the distance between faults, if the populations of the circuit faults have distributions with differing variances. Mutual information theory is suggested here as a robust method for clustering circuit faults. The bootstrap technique is proposed to speed up the process of generating statistical data. Statistical data on the performance of circuits under fault conditions is generated using HSPICE. A software program has been written to implement clustering of responses using mutual information theory and to generate statistical data using bootstrap. The technique is shown to generate a suitable set of parameters for a regression function. The simulation results for the behavioural models are close to those of the full circuit model. Mutual information theory is a useful technique for clustering responses of circuits under fault conditions.

Fault Simulation for Analog Circuits Under Parameter Variations

Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4.

Static test compaction for synchronous sequential circuits based on vector restoration

We propose a new static test compaction procedure for synchronous sequential circuits. The procedure belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its length without reducing the fault coverage. The previous procedure that achieved high levels of compaction using this approach attempted to omit test vectors from a given test sequence one at a time or in subsequences of consecutive vectors. The omission of each vector or subsequence required extensive simulation to determine the effects of each omission on the fault coverage. The procedure proposed here first omits (almost) all the test vectors from the sequence, and then restores some of them as necessary to achieve the required fault coverage. The decision to restore a vector requires simulation of a single fault. Thus, the overall computational effort of this procedure is relatively low. The loss of compaction compared to the scheme that omits the vectors one at a time or in subsequences is small in most cases. Techniques to speed up the restoration process are also investigated, including consideration of several faults in parallel during restoration, and the use of a parallel fault simulator. Experimental results are presented to demonstrate the effectiveness of vector restoration as a static compaction technique.