Parallel DSP Research Articles

An improved multi-objective evolutionary algorithm for multiple-target asynchronous parallel selective disassembly sequence planning

The product’s service life has been shortened rapidly along with the development of modern technologies and human esthetic evolutions, resulting in a great number of end-of-life (EOL) products. Disassembling renewable parts from EOL products for remanufacturing is of great significance to save resources and protect the environment. The existing studies on selective disassembly sequence planning (SDSP) largely focus on the sequential disassembly planning, which is inefficient especially for complex products because it is a linear process where only one component can be removed at a time. Thus, this work focuses on parallel SDSP and further proposes a multiple-target asynchronous parallel selective DSP (APSDSP) with the objectives of minimizing disassembly time and maximizing disassembly profit simultaneously. In APSDSP, operators can remove multiple components simultaneously as long as disassembly constraints are not violated, and without synchronization requirement between operators. The feasible disassembly sequence and disassembly direction sequence are generated by a space interference matrix method (SIMM) to meet the actual disassembly environment. Based on SIMM, an improved multi-objective evolutionary algorithm based on multiple neighborhood search strategy is developed to create the pareto frontier of the problem. Finally, two cases study are presented to validate the effectiveness of the proposed methodology. It gives enterprises new insights to reduce disassembly time and improve disassembly profit.

Design of the Real-Time Single-Photodiode Digital Coherent Receiver Suitable for Free Space Optical Communication

High sensitivity, small size, light weight and low power are the most critical requirements for the lasercom terminals used in free space optical communication (FSOC) systems. Coherent receivers have an exceptionally high sensitivity but their optical complexity and power consumption are too high, especially for the space-borne lasercom terminals. Recently we propose a pseudo-single-side-band-signal based single-photodiode coherent receiver (P-SCR) with very low optical and algorithm complexity which can potentially satisfy the strict requirement of the FSOC systems. In this paper, we first introduce the working principles of the P-SCR based on the frequency and time domain field reconstruction algorithms (TD-FRA and FD-FRA). We then investigate the relationships between the computation complexity and sensitivity for the two kinds of P-SCR, respectively. We also provide a method to minimize the FD-FRA complexity and demonstrate that its power consumption is only 3.7%, 25.3% and 37.8% of that of the well-known conventional Kramers-Kronig (KK) algorithm, upsampling-free KK algorithm and TD-FRA. Based on the optimized FD-FRA, we develop a highly parallel DSP circuit for the real-time P-SCR using a FPGA chip. The experiments in a 10GBaud QPSK transmission system show that the sensitivity of the real-time P-SCR is only ~4.2 dB away from the theoretical limit.

A new parallel DSP hardware compatible algorithm for noise reduction and contrast enhancement in video sequence using Zynq-7020

Various video processing applications such as liquid crystal display processing, high quality video photography, terrestrial video recording and medical imaging systems requires robust noise reduction and contrast enhancement technique which provides visually pleasing for real time implementation novel hardware architecture has been designed using look-up-table (LUT) acceleration approach which helps achieve high speed processing. Until now, a lot of researchers have worked on noise removal and contrast enhancement of digital videos, but the developed algorithms works with only some verity of noises and failed to produce desirable results for various types of distortions and real time implementation is still remaining a challenge. Hence, appropriate filter needs to be designed which address both kinds of errors. In this paper, adaptive trilateral filter has been designed for noise reduction the results are measured using qualitative and quantitative analysis which has aided in better utilisation of hardware for real time implementation. The experimental results show that the proposed algorithm provides a frame rate of 40 fps on an average and has a resolution of 720 × 576. The proposed algorithm was implemented on ZedBoard Znyq-7020 development kit by Xilinx.

A new parallel DSP hardware compatible algorithm for noise reduction and contrast enhancement in video sequence using Zynq-7020

Various video processing applications such as liquid crystal display processing, high quality video photography, terrestrial video recording and medical imaging systems requires robust noise reduction and contrast enhancement technique which provides visually pleasing for real time implementation novel hardware architecture has been designed using look-up-table (LUT) acceleration approach which helps achieve high speed processing. Until now, a lot of researchers have worked on noise removal and contrast enhancement of digital videos, but the developed algorithms works with only some verity of noises and failed to produce desirable results for various types of distortions and real time implementation is still remaining a challenge. Hence, appropriate filter needs to be designed which address both kinds of errors. In this paper, adaptive trilateral filter has been designed for noise reduction the results are measured using qualitative and quantitative analysis which has aided in better utilisation of hardware for real time implementation. The experimental results show that the proposed algorithm provides a frame rate of 40 fps on an average and has a resolution of 720 × 576. The proposed algorithm was implemented on ZedBoard Znyq-7020 development kit by Xilinx.

Massive Image Treatment System Based on Cloud Computing Platform

Massive image processing technology requires high requirements of processor and memory, and it needs to adopt high performance of processor and the large capacity memory. While the single or single core processing and traditional memory can’t satisfy the need of image processing. This paper introduces the cloud computing function into the massive image processing system. Through the cloud computing function it expands the virtual space of the system, saves computer resources and improves the efficiency of image processing. The system processor uses multi-core DSP parallel processor, and develops visualization parameter setting window and output results using VC software settings. Through simulation calculation we get the image processing speed curve and the system image adaptive curve. It provides the technical reference for the design of large-scale image processing system.

Overcoming Phase Sensitivity in Real-Time Parallel DSP for Optical Coherent Communications: Optically Filtered Lasers

Implementation of real-time giga-Baud optical coherent systems for single-carrier higher-level modulation format such as 64-quadrature amplitude modulation (QAM) depends heavily on phase tracking. For offline digital signal processing, decision-directed phase recovery is performed at symbol rate with the best performance and the least computational effort compared among other best-known algorithms. However, in real-time systems, hardware parallelization and pipelining delay on feedback path pose stringer requirement on the linewidth, or the frequency noise spectral level of laser sources. This leads to the paucity of experiments demonstrating real-time phase tracking for 64- or higher QAM. In this paper, we experimentally investigate the impact of optically-filtered lasers on parallel and pipelined phase tracking in a single-carrier 5 Gbaud 64-QAM back-to-back coherent system. For parallelization levels higher than 24, the optically-filtered laser shows more than 2 dB improvement in optical signal-to-noise ratio penalty compared to that of the same laser without optical filtering.

Study on the Multi-Core DSP Parallel Processing of Polarization Images Registration

Three-channel polarization images must be registered before pixel-level fusion processing to acquire accurate polarization characteristics information. In the condition of serial processing, the image registration efficiency is bad, and then the real-time of polarization imaging application is poor. The multi-core DSP chip which type is TMS320C6670 is selected as the polarization images processing platform. Fourier-Mellin Transform (FMT) is selected as the registration algorithm. The parallel processing of the polarization image registration is studied based on data flow model. The hierarchical task graph is designed in the parallel processing tasks partitioning. According to processing performance and functions, four DSP cores and two FFT coprocessors are divided into different processor groups in each task processing stage. Same hierarchical tasks are assigned to each processor group. According to principles including load balancing and reducing inter-processor communication, algorithms and data of each hierarchical task are assigned manually to each processing unit in the processor group. Experimental results show that the average processing time is 0.429 second while the average registration accuracy achieves 0.5 pixel, the propose parallel processing method improves the efficiency of the polarization image registration.

Research on Real-Time Laser Range Finding System

Phase shift laser range finder, as a large-scale, high-precision measurement method, is widely used in industrial and military fields. The traditional laser range finder can not meet the need of real-time, high resolution measurement because of its low anti-jamming capability and time-consuming measurement. Owing to this, multi-channel transmitting and receiving system for phase shift laser range finder based on parallel DSP was designed. Multi-frequency modulation laser can be transmitted and received at the same time, improving the measurement speed and avoiding the wrong data fusion because of target moving. The distance was got by measuring the phase difference between the measurement signal and reference signal, and the Doppler velocity of the target is got by measuring the measurement signals frequency, The measurement signals reference signals were acquired by parallel AD convertors, the phase difference between them was calculated adopting all-phase FFT(apFFT). A new frequency correction method was proposed according to the amplitude spectrum acquired by apFFT, Amplitude spectrum is expanded into Taylor series and the correction value of frequency is calculated by relationship of spectrum lines. Monte Carlo simulation results proved that the new frequency correction method had higher resolution and better stability than Rife method and centro-baric method. The experiments is implemented on a precision guide of 3m-long, on the condition that the sampling frequency of AD converter is 937.5KHz, the apFFT transform point number is 4096, distance and velocity results can be obtained each 10ms, experiments prove that the distance measurement standard deviation better than 0.09mm and the velocity measurement standard deviation better than 0.022m/s are obtained. The system can meet the need of high accuracy ,real-time distance measurement of moving target.

Design and Implementation of High Precision Active Wheel Sensor

Wheel sensor is the basic facility of railway axle counter. The traditional active magnetic steel axle counter method has a disadvantage of low accuracy. For this reason, a high-precision active wheel sensor which sends axle pulse in a fixed position of wheel signal was presented. In addition, double DSP parallel working mode was used to improve the reliability of the system. Firstly, the detection scheme of the system was presented. Then hardware circuit of the wheel sensor was designed with TMS320F2812, and the reliable output of the pulse was realized by using the gate circuit. Finally, software programming was completed based on the hardware design, which mainly includes the wheel signal detection and position calculation for sending axle pulse. The actual operation shows that the system has the advantages of being stable and reliable and has strong resistance to interference, which makes it a high practical value.

Research on the Performance of DSP Parallel System

This paper introduces the performance metric of DSP parallel processing system and presents a model of coarse-grained speedup of DSP parallel processing structure. Quantitative research is done according to the system performance index and target program features. This study simulates and analyzes different communication protocols and different influences of different degrees of parallelism on the parallel processing structure performances. Optimization direction of parallel processing system is put forward.

Register spilling via transformed interference equations for PAC DSP architecture

SUMMARYDigital signal processors (DSPs) with very long instruction word (VLIW) data‐path architectures are increasingly being deployed on embedded devices for multimedia processing applications. To reduce the power consumption and design cost of VLIW DSP processors, distributed register files and multibank register architectures are being adopted to reduce the number of read and write ports associated with register files, which presents new challenges for devising compiler optimization schemes. This paper addresses the issues of reducing the spill code for a VLIW DSP with distributed register files. Spill code produced by register allocation is traditionally handled by memory spills, but the multibank register‐file architecture provides the opportunity to spill‐out register values onto different register banks. We present a conceptual framework based on the universal and the proxy interference graphs to model the live ranges of registers for spilling codes to different register banks. Heuristic algorithms are then developed on the basis of this concept. By heuristically estimating the register pressure for each register file, we treat different register banks as optional spilling locations in addition to traditional spilling to memory. Experiments were performed on the parallel architecture core VLIW DSP with distributed register files by incorporating our proposed optimization schemes into an Open64‐based compiler. The experimental results show that our approach can improve the performances on average for DSPStone and MiBench benchmarks with spilling cases by 7.1% and 21.6%, respectively, compared with the one always handling spill code in memory. Copyright © 2013 John Wiley & Sons, Ltd.

Widely Tunable Burst Mode Digital Coherent Receiver With Fast Reconfiguration Time for 112 Gb/s DP-QPSK WDM Networks

A widely tunable burst mode digital coherent receiver is implemented in a 112 Gb/s DP-QPSK WDM system. The receiver performance is validated in a 24-channel WDM test-bed using a commercially available DS-DBR laser as the local oscillator. It is demonstrated that the wavelength tunable laser can switch to any one of the 24-channels in less than 130 ns, thus enabling the dynamic reception of 5 μ s optical bursts. The performance of the DS-DBR local oscillator laser is commensurate with burst mode coherent reception when differential decoding is employed and the parallel DSP implementation does not impair the polarization and frequency tracking performance of a digital coherent receiver under burst mode operation. The worst case reconfiguration time of the burst mode receiver, which is a combination of the laser switching time and the CMA convergence time, is less than 410 ns when switching from a single channel to any other channel in the WDM grid. It is shown that the variation in reconfiguration time is dependent on the convergence time of the CMA equalizer, which is adversely affected by certain input states of polarization.

A High Definition Motion JPEG Encoder Based on Epuma Platform

The ePUMA is a novel parallel DSP platform based on master-multi-SIMD architecture. The essential technology is to use separated data access kernels and algorithm kernels to minimize the communication overhead of parallel processing by running the two types of kernels in parallel. In this paper, a high definition motion JPEG encoder based on ePUMA platform is introduced. The ePUMA processor is re-configured and acts as the main processing unit of the encoder. The motion JPEG encoder is implemented on the FPGA development board. Results show that the encoder can process high definition video with 1920x1080@30fps.

Burst Mode Receiver for 112 Gb/s DP-QPSK with parallel DSP

A burst mode 112 Gb/s DP-QPSK digital coherent optical receiver with parallel DSP suitable for implementation in a CMOS ASIC with a 218.75 MHz clock speed is presented. The receiver performance is validated in a five channel 50 GHz grid WDM burst switching experiment using a commercially available wavelength tunable laser as the local oscillator. A new equalizer initialization scheme that overcomes the degenerate convergence problem and ensures rapid convergence is introduced. We show that the performance of the tunable local oscillator is commensurate with burst mode coherent reception when differential decoding in employed and that required parallel DSP implementation does not seriously impair the polarization and frequency tracking performance of a digital coherent receiver under burst mode operation. We report a burst acquisition time of less than 200 ns.

Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels

A novel master-multi-SIMD architecture and its kernel (template) based parallel programming flow is introduced as a parallel signal processing platform. The name of the platform is ePUMA (embedded Parallel DSP processor architecture with Unique Memory Access). The essential technology is to separate data accessing kernels from arithmetic computing kernels so that the run-time cost of data access can be minimized by running it in parallel with algorithm computing. The SIMD memory subsystem architecture based on the proposed flow dramatically improves the total computing performance. The hardware system and programming flow introduced in this article will primarily aim at low-power high-performance embedded parallel computing with low silicon cost for communications and similar real-time signal processing.

VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor

Audio coding is indispensable in our life and MPEG AAC is one of the most popular audio coding standards. It has been widely used in variant applications. In this paper, we propose VLIW-aware software optimization techniques for the AAC decoding blocks on the parallel architecture core DSP (PACDSP) processor. This approach provides the flexibility for adding new extensions and solves two important issues, low power consumption and limited resources problems on DSP for portable devices. We change the traditional sequential algorithms into parallel processes and minimize the memory utilization of each block. The realized decoder can be operated at a lower frequency of only 15 MHz and needs only 27 Kbytes of program memory and 27 Kbytes of data memory .

Interleaving on Parallel DSP Architectures

Today's communications systems especially in the field of wireless communications rely on many different algorithms to provide applications with constantly increasing data rates and higher quality. This development combined with the wireless channel characteristics as well as the invention of turbo codes has particularly increased the importance of interleaver algorithms. In this paper, we demonstrate the feasibility to exploit the hardware parallelism in order to accelerate the interleaving procedure. Based on a heuristic algorithm, the possible speedup for different interleavers as a function of the degree of parallelism of the hardware is presented. The parallelization is generic in the sense that the assumed underlying hardware is based on a parallel datapath DSP architecture and therefore provides the flexibility of software solutions.

A visual servoing system for edge trimming of fabric embroideries by laser

This paper describes a position-based visual servoing system for edge trimming of fabric embroideries by laser. The high-speed vision system, based on a 220 Hz digital camera and the TMS320C40 parallel DSP processor is presented, and the novel image processing algorithm developed for seam tracking applications is briefly explained. Two methods for seam trajectory generation are discussed. In the first method the tracking trajectory is determined only by using the vision data; in the second method, which is suitable for periodic patterns, the predetermined path data is modified by the vision data. A tracking controller using a feedforward controller in the tangential direction of the seam and a feedback controller in the normal direction is described. The custom built manipulator is a four-axis velocity controlled gantry robot with independent PID controllers for each axis. The axes’ reference speeds are commanded and updated by the top-level tracking controller in equal time intervals. The gantry controller program runs on a Pentium PC. The experimental results in edge trimming of different seam patterns are presented.

The Rationale for Distributed Semantics as a Topology Independent Embedded Systems Design Methodology and its Implementation in the Virtuoso RTOS

Virtuoso VSP is a fully distributed real-time operating system originally developed on the Inmos transputer. Its generic architecture is based on a small but very fast nanokernel and a portable preemptive microkernel. It was further on ported in single and virtual single processor implementations to a wide range of processors. This paper describes the rationale for developing the distributed semantics of Virtuoso's microkernel and describes some of the implementation issues. The analysis is based on the parallel DSP implementations as these push the performance limits most for hard real-time applications. Extensions of the model towards heterogeneous embedded target systems are discussed.

The TigerSHARC DSP architecture

This highly parallel DSP architecture based on a short-vector memory system incorporates techniques found in general-purpose computing. It promises sustained performance close to its peak computational rates of 900 MFLOPS (32-bit floating-point) or 3.6 BOPS (16-bit fixed-point).