Parallel Decoding Research Articles

Simultaneous Denoising and Localization Network for Photoacoustic Target Localization.

A significant research problem of recent interest is the localization of targets like vessels, surgical needles, and tumors in photoacoustic (PA) images.To achieve accurate localization, a high photoacoustic signal-to-noise ratio (SNR) is required. However, this is not guaranteed for deep targets, as optical scattering causes an exponential decay in optical fluence with respect to tissue depth. To address this, we develop a novel deep learning method designed to explicitly exhibit robustness to noise present in photoacoustic radio-frequency (RF) data. More precisely, we describe and evaluate a deep neural network architecture consisting of a shared encoder and two parallel decoders. One decoder extracts the target coordinates from the input RF data while the other boosts the SNR and estimates clean RF data. The joint optimization of the shared encoder and dual decoders lends significant noise robustness to the features extracted by the encoder, which in turn enables the network to contain detailed information about deep targets that may be obscured by noise. Additional custom layers and newly proposed regularizers in the training loss function (designed based on observed RF data signal and noise behavior) serve to increase the SNR in the cleaned RF output and improve model performance. To account for depth-dependent strong optical scattering, our network was trained with simulated photoacoustic datasets of targets embedded at different depths inside tissue media of different scattering levels. The network trained on this novel dataset accurately locates targets in experimental PA data that is clinically relevant with respect to the localization of vessels, needles, or brachytherapy seeds. We verify the merits of the proposed architecture by outperforming the state of the art on both simulated and experimental datasets.

A dual population multi-operator genetic algorithm for flight deck operations scheduling problem

It is of great significance to carry out effective scheduling for the carrier-based aircraft flight deck operations. In this paper, the precedence constraints and resource constraints in flight deck operations are analyzed, then the model of the multi-aircraft integrated scheduling problem with transfer times (MAISPTT) is established. A dual population multi-operator genetic algorithm (DPMOGA) is proposed for solving the problem. In the algorithm, the dual population structure and random-key encoding modified by starting/ending time of operations are adopted, and multiple genetic operators are self-adaptively used to obtain better encodings. In order to conduct the mapping from encodings to feasible schedules, serial and parallel scheduling generation scheme-based decoding operators, each of which adopts different justified mechanisms in two separated populations, are introduced. The superiority of the DPMOGA is verified by simulation experiments.

Balancing memory-accessing and computing over sparse DNN accelerator via efficient data packaging

Embedded devices are common carriers for deploying inference networks, which leverage the customized accelerator to achieve the promised performance with strict resource constraints. In the inference of Deep Neural Network(DNN), the sparsity existing in the activations and weights of every layer contributes massive non-effective memory accesses and computing operations. The data compression is adopted as a data pruning method for accelerator design, which eliminates the zero-valued data with a specific data packaging method. However, the data compression, in varying degrees, breaks the data regularity of the processing array DNN accelerators calculates with. The complexity of data access caused by irregular data organization will add extra control logic and decoding logic to compensate. The accelerator architecture that supports sparsity can use the sophisticated memory access scheming and parallel on-chip decoder structure via an efficient data packaging method to balance memory-accessing and computing for acceleration. In this paper, we propose a flexible and highly parallel accelerator architecture that uses a quantitative data packaging method which is efficient and stable for different degrees of sparsity and parallel optimization to explore the sparsity in DNN to achieve high performance with low energy consumption. The total DRAM accesses, performance and energy consumption of the proposed sparse architecture are evaluated with different inference networks. Experiments show that the DRAM accesses of the proposed efficient data packaging method is significantly lower than other commonly used sparse data compression storage methods, the improved performance and saved energy of the sparse accelerator architecture after adopting the optimization method proposed in this paper are up to 1.2x and 1.6x, respectively, over a comparably provisioned do not support sparsity accelerator. In addition, the accelerator architecture proposed has achieved energy efficiency and performance improvements of up to 1.70x and 1.56x, compared with the state-of-the-art architectures.

Parallel Backscatter: Channel Estimation and Beyond

As backscatter-based IoT applications get proliferated, how to exploit backscattered signals for efficient sensing becomes a significant issue. Backscatter-based sensing requires accurate estimation of a backscatter channel (phase and amplitude), which is distorted when multiple signals collide with each other. As a result, the state of the arts is limited to either parallel decoding of collided signal or channel estimation with clean signal. Motivated by the need of high sensing capacity, we in this article present Fireworks, the first approach for channel estimation of parallel backscattered signals. The insight of Fireworks is that although the channel is distorted due to collision, the movements of the ON-OFF Keying modulated signal still preserve the channel properties of the respective tags. By modeling the relationship between the channels and the signal's moving trajectory in the IQ domain, one can make accurate estimation of the channels directly from the collision. We address practical problems of Fireworks, such as the high computing complexity and the compatibility with the commercial MAC protocol, and implement Fireworks. The results show that Fireworks is able to estimate the channels of up to five tags in parallel. When applied to the tracking application, Fireworks achieves 2 ~ 4× improvement in the tracking accuracy, compared with the state-of-the-art approach.

Threshold-Based Fast Successive-Cancellation Decoding of Polar Codes

Fast SC decoding overcomes the latency caused by the serial nature of the SC decoding by identifying new nodes in the upper levels of the SC decoding tree and implementing their fast parallel decoders. In this work, we first present a novel sequence repetition node corresponding to a particular class of bit sequences. Most existing special node types are special cases of the proposed sequence repetition node. Then, a fast parallel decoder is proposed for this class of node. To further speed up the decoding process of general nodes outside this class, a threshold-based hard-decision-aided scheme is introduced. The threshold value that guarantees a given error-correction performance in the proposed scheme is derived theoretically. Analysis and hardware implementation results on a polar code of length 1024 with code rates 1/4, 1/2, and 3/4 show that our proposed algorithm reduces the required clock cycles by up to 8%, and leads to a 10% improvement in the maximum operating frequency compared to state-of-the-art decoders without tangibly altering the error-correction performance. In addition, using the proposed threshold-based hard-decision-aided scheme, the decoding latency can be further reduced by 57% at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> /N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> = 5.0 dB.

Design of A Parallel Decoding Method for LDPC Code Generated via Primitive Polynomial

An effective way of improving decoding performance of an LDPC code is to extend the single-decoder decoding method to a parallel decoding method with multiple sub-decoders. To this end, this paper proposes a parallel decoding method for the LDPC codes constructed by m-sequence. In this method, the sub-decoders have two types. The first one contains only one decoding module using the original parity-check constraints to implement a belief propagation (BP) algorithm. The second one consists of a pre-decode module and a decoding module. The parity-check matrices for pre-decode modules are generated by the parity-check constraints of the sub-sequences sampled from an m-sequence. Then, the number of iterations of the BP process in each pre-decode module is set as half of the girth of the parity-check matrix, resulting in the elimination of the impact of short cycles. Using maximum a posterior (MAP), the least metric selector (LMS) finally picks out a codeword from the outputs of sub-decoders. Our simulation results show that the performance gain of the proposed parallel decoding method with five sub-decoders is about 0.4 dB, compared to the single-decoder decoding method at the bit error rate (BER) of 10−5.

Input-Distribution-Aware Successive Cancellation List Decoding of Polar Codes

Polar codes are linear block codes that can achieve channel capacity at infinite code length. Successive cancellation list (SCL) decoding relies on a set of parallel decoders; it yields good error-correction performance at finite code length, at the cost of increased implementation complexity and power consumption. Current efforts in literature focus on design-time decoder complexity reduction, while lacking practical run-time power reduction methods. In this work, input-distribution-aware SCL (IDA-SCL) decoding is proposed, that allows to determine the parallelism to adopt by performing simple observations on the input of the decoder. This technique guarantees fixed, short latency and allows hardware SCL decoders to dynamically shut down part of the internal parallelism before each decoding process. It can be combined with existing complexity- and power- reduction techniques. Simulation results show that IDA-SCL can reduce the run-time complexity of SCL of up to 50%.

A comprehensive review of parallel concatenation of LDPC code techniques

Objective: In the code theory, parallel concatenation of codes becomes more popular after the introduction of turbo codes. In recent years, the Low Density Parity Check (LDPC) code has found remarkable advancement and has seen them outshine turbo codes in terms of performance especially in the error floor and higher code rate. The main objective of this paper is to address the various techniques of a parallel concatenation of LDPC code in code theory. Method/Finding: To reduce the complexity of encoding and decoding for longer codes various parallel concatenation of LDPC coding methods were introduced and the performance was compared with other work. Novelty: When a longer block length is used, the parallel LDPC decoder is suffered from the complexity of prohibitive implementation. To overcome this issue and to achieve the best performance for longer codes, the different methods for parallel concatenation of LDPC codes were introduced with reduced complexity. This will helps to break the long and complex LDPC code into less complex and smaller LDPC to distribute the decoding and encoding load. Also, this will provides scalability and scope for improving the performance of LDPC codes in practical delay-sensitive and energy-aware applications. Keywords: Parallel concatenation; LowDensity ParityCheck (LDPC); turbo codes; Parallel Concatenated Gallager Codes (PCGC)

Semi-Siamese U-Net for separation of lung and heart bioimpedance images: A simulation study of thorax EIT.

Electrical impedance tomography (EIT) is widely used for bedside monitoring of lung ventilation status. Its goal is to reflect the internal conductivity changes and estimate the electrical properties of the tissues in the thorax. However, poor spatial resolution affects EIT image reconstruction to the extent that the heart and lung-related impedance images are barely distinguishable. Several studies have attempted to tackle this problem, and approaches based on decomposition of EIT images using linear transformations have been developed, and recently, U-Net has become a prominent architecture for semantic segmentation. In this paper, we propose a novel semi-Siamese U-Net specifically tailored for EIT application. It is based on the state-of-the-art U-Net, whose structure is modified and extended, forming shared encoder with parallel decoders and has multi-task weighted losses added to adapt to the individual separation tasks. The trained semi-Siamese U-Net model was evaluated with a test dataset, and the results were compared with those of the classical U-Net in terms of Dice similarity coefficient and mean absolute error. Results showed that compared with the classical U-Net, semi-Siamese U-Net exhibited performance improvements of 11.37% and 3.2% in Dice similarity coefficient, and 3.16% and 5.54% in mean absolute error, in terms of heart and lung-impedance image separation, respectively.

Implementation of FPGA Based on High Throughput Parallel CRC-SCL Decoder of Polar Codes

Implementation of FPGA Based on High Throughput Parallel CRC-SCL Decoder of Polar Codes

Adaptive Adapters: An Efficient Way to Incorporate BERT Into Neural Machine Translation

Large-scale pre-trained language models (e.g., BERT) have attracted great attention in recent years. It is straightforward to fine-tune them on natural language understanding tasks such as text classification, however, effectively and efficiently incorporating them into natural language generation tasks such as neural machine translation remains a challenging problem. In this paper, we integrate two pre-trained BERT models from the source and target language domains into a sequence-to-sequence model by introducing light-weight adapter modules. The adapters are inserted between BERT layers and tuned on downstream tasks, while the parameters of BERT models are fixed during fine-tuning. As pre-trained language models are usually very deep, inserting adapters into all layers will result in a considerable scale of new parameters. To deal with this problem, we introduce latent variables to decide whether using adapters or not in each layer, which are learned during fine-tuning. In this way, the model is able to automatically determine which adapters to use, therefore hugely promoting the parameter efficiency and decoding speed. We evaluate the proposed framework on various neural machine translation tasks. Equipped with parallel sequence decoding, our model consistently outperforms autoregressive baselines while reducing the inference latency by half. With automatic adapter selection, the proposed model further achieves 20% speedup while still outperforming autoregressive baselines. When applied to autoregressive decoding, the proposed model can also achieve comparable performance with the state-of-the-art baseline models.

Sublinear Latency for Simplified Successive Cancellation Decoding of Polar Codes

This work analyzes the latency of the simplified successive cancellation (SSC) decoding scheme for polar codes proposed by Alamdar-Yazdi and Kschischang. It is shown that, unlike conventional successive cancellation decoding, where latency is linear in the block length, the latency of SSC decoding is sublinear. More specifically, the latency of SSC decoding is O(N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-1/μ</sup> ), where N is the block length and μ is the scaling exponent of the channel, which captures the speed of convergence of the rate to capacity. Numerical results demonstrate the tightness of the bound and show that most of the latency reduction arises from the parallel decoding of subcodes of rate 0 or 1.

PEPSI++: Fast and Lightweight Network for Image Inpainting.

Among the various generative adversarial network (GAN)-based image inpainting methods, a coarse-to-fine network with a contextual attention module (CAM) has shown remarkable performance. However, due to two stacked generative networks, the coarse-to-fine network needs numerous computational resources, such as convolution operations and network parameters, which result in low speed. To address this problem, we propose a novel network architecture called parallel extended-decoder path for semantic inpainting (PEPSI) network, which aims at reducing the hardware costs and improving the inpainting performance. PEPSI consists of a single shared encoding network and parallel decoding networks called coarse and inpainting paths. The coarse path produces a preliminary inpainting result to train the encoding network for the prediction of features for the CAM. Simultaneously, the inpainting path generates higher inpainting quality using the refined features reconstructed via the CAM. In addition, we propose Diet-PEPSI that significantly reduces the network parameters while maintaining the performance. In Diet-PEPSI, to capture the global contextual information with low hardware costs, we propose novel rate-adaptive dilated convolutional layers that employ the common weights but produce dynamic features depending on the given dilation rates. Extensive experiments comparing the performance with state-of-the-art image inpainting methods demonstrate that both PEPSI and Diet-PEPSI improve the qualitative scores, i.e., the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM), as well as significantly reduce hardware costs, such as computational time and the number of network parameters.

Minimum Distance Optimization with Chord Edge Growth for High Girth Non-Binary LDPC Codes

Short or moderate-length non-binary low-density parity-check (NB-LDPC) codes have the potential applications in future low latency and high-reliability communication thanks to the strong error correction capability and parallel decoding. Because of the existence of the error floor, the NB-LDPC codes usually cannot satisfy very low bit error rate (BER) requirements. In this paper, a low-complexity method is proposed for optimizing the minimum distance of the NB-LDPC code in a progressive chord edge growth manner. Specifically, each chord edge connecting two non-adjacent vertices is added to the Hamiltonian cycle one-by-one. For each newly added chord edge, the configuration of non-zero entries corresponding to the chord edge is determined according to the so-called full rank condition (FRC) of all cycles that are related to the chord edge in the obtained subgraph. With minor modifications to the designed method, it can be used to construct the NB-LDPC codes with an efficient encoding structure. The analysis results show that the method for designing NB-LDPC codes while using progressive chord edge growth has lower complexity than traditional methods. The simulation results show that the proposed method can effectively improve the performance of the NB-LDPC code in the high signal-to-noise ratio (SNR) region. While using the proposed scheme, an NB-LDPC code with a quite low BER can be constructed with extremely low complexity.

Semantic Structured Image Coding Framework for Multiple Intelligent Applications

Fast-growing intelligent media processing applications demand efficient processing throughout the processing chain from the edge to the cloud, and the complexity bottleneck usually lies in the parallel decoding of multiple-channel compressed bitstreams before analyzing. This occurs because the traditional media coding scheme generates a binary stream without a semantic structure, which is unable to be operated directly at the bitstream level to support different tasks such as classification, recognition, detection, etc. Therefore, in this article, we propose a learning-based semantically structured image coding (SSIC) framework to generate a semantically structured bitstream (SSB), where each part of the bitstream represents a specific object and can be directly used for the aforementioned intelligent tasks. Specifically, we integrate an object location extraction module into the compression framework to locate and align objects in the feature domain. Then, each object together with the background is compressed separately and reorganized to form a structured bitstream to enable the analysis or reconstruction of specific objects directly from partial bitstream. Furthermore, in contrast to existing learning-based compression schemes that train the specific model for a specific bitrate, we share most of the model parameters among various bitrates to significantly reduce the model size for variable-rate compression. The experimental results demonstrate the effectiveness of the proposed coding scheme whose compression performance is comparable to existing image coding schemes, where intelligent tasks such as classification and pose estimation can be directly performed on a partial bitstream without performance degradation, significantly reducing the complexity for analyzing tasks.

Low delay non-binary error correction codes based on Orthogonal Latin Squares

Due to the scaling of technology and the environment effects, such as radiation, memory systems that are on board of spacecraft such as satellites, are more sensitive to errors. This kind of error is difficult to predict and its correction in real-time is crucial for the correct behavior of the whole system. In this paper, a low delay fully parallel non-binary decoder based on orthogonal Latin squares defined in a Galois field is presented. The proposed approach corrects a single symbol in GF(2q) with very low complexity applying a one-step majority logic algorithm that allows reaching high-speed decoding with very low latency. The decoder introduced in this manuscript was implemented for 64 and 128-bit codes over GF(28) in a 45 nm CMOS process. Our implementation outperforms state-of-the-art decoders with the same error correction capacity, achieving lower latency, delay and area in both cases. The results show that the proposed solution can be suitable for the protection of some types of memories like DRAM or 3D-memories and other radioactive environment applications.

FTrack: Parallel Decoding for LoRa Transmissions

LoRa has emerged as a promising Low-Power Wide Area Network (LP-WAN) technology to connect a huge number of Internet-of-Things (IoT) devices. The dense deployment and an increasing number of IoT devices lead to intense collisions due to uncoordinated transmissions. However, the current MAC/PHY design of LoRaWAN fails to recover collisions, resulting in degraded performance as the system scales. This article presents FTrack, a novel communication paradigm that enables demodulation of collided LoRa transmissions. FTrack resolves LoRa collisions at the physical layer and thereby supports parallel decoding for LoRa transmissions. We propose a novel technique to separate collided transmissions by jointly considering both the time domain and the frequency domain features. The proposed technique is motivated from two key observations: (1) the symbol edges of the same frame exhibit periodic patterns, while the symbol edges of different frames are usually misaligned in time; (2) the frequency of LoRa signal increases continuously in between the edges of symbol, yet exhibits sudden changes at the symbol edges. We detect the continuity of signal frequency to remove interference and further exploit the time-domain information of symbol edges to recover symbols of all collided frames. We substantially optimize computation-intensive tasks and meet the real-time requirements of parallel LoRa decoding. We implement FTrack on a low-cost software defined radio. Our testbed evaluations show that FTrack demodulates collided LoRa frames with low symbol error rates in diverse SNR conditions. It increases the throughput of LoRaWAN in real usage scenarios by up to 3 times.

Symbol positions‐based Slepian–Wolf coding with application to distributed video coding

In this study, the authors will show that coding the positions of the symbols, instead of their values, can be a good way to implement efficient Slepian–Wolf (SW) coding and can reduce the complexity of both the encoder and the decoder. The authors will also propose a practical distributed video coding (DVC) system that exploits this idea. This system will use binary maps to indicate the positions of the most probable symbols, instead of separating them into bitplanes. Simulations show that this position-based SW coding allows a simple and more efficient DVC system with improved rate-distortion performance, compared to the bitplane-based DVC system that uses the same side information. The memory requirements at the encoder are reduced by about 50% and the number of channel coding operations is also reduced. This DVC system also allows to use an easy way to control quantisation, reduces the decoding latency, and allows fast parallel decoding.

Inf-Net: Automatic COVID-19 Lung Infection Segmentation From CT Images.

Coronavirus Disease 2019 (COVID-19) spread globally in early 2020, causing the world to face an existential health crisis. Automated detection of lung infections from computed tomography (CT) images offers a great potential to augment the traditional healthcare strategy for tackling COVID-19. However, segmenting infected regions from CT slices faces several challenges, including high variation in infection characteristics, and low intensity contrast between infections and normal tissues. Further, collecting a large amount of data is impractical within a short time period, inhibiting the training of a deep model. To address these challenges, a novel COVID-19 Lung Infection Segmentation Deep Network (Inf-Net) is proposed to automatically identify infected regions from chest CT slices. In our Inf-Net, a parallel partial decoder is used to aggregate the high-level features and generate a global map. Then, the implicit reverse attention and explicit edge-attention are utilized to model the boundaries and enhance the representations. Moreover, to alleviate the shortage of labeled data, we present a semi-supervised segmentation framework based on a randomly selected propagation strategy, which only requires a few labeled images and leverages primarily unlabeled data. Our semi-supervised framework can improve the learning ability and achieve a higher performance. Extensive experiments on our COVID-SemiSeg and real CT volumes demonstrate that the proposed Inf-Net outperforms most cutting-edge segmentation models and advances the state-of-the-art performance.

Implementation of 16bit Fully Parallel Polar Encoder and Decoder using Partially Parallel Register Less Technique

This paper is about implementation of fully parallel polar encoder and decoder using partially parallel register less technique. Internal architecture consists of register less partially polar encoders and decoders. Compared to fully parallel polar encoder and SC polar decoder, proposed design has less area and less power consumption. Implementing long polar codes using fully parallel polar encoder and decoder is complex. In such cases proposed design can be used. Polar codes having simple structures and good performance. Proposed design is implemented using Synopsis. Simulation process is done in VCS and Xilinx. Polar codes widely used in 5G technology, these are the codess for control channels in 5G standard.