Parallel Circuit Simulation Research Articles

Parallel Large-scale MOSFET Circuit Simulation using Multi-core CPU and Time-saving Techniques

In this paper, we investigate the acceleration properties of fine-grain parallel large-scale MOSFET circuit simulation using multi-core CPU. Several CPU have been tested for understanding maximum possible accelerations. A parallel circuit simulator, MOSTIME, is used to simulate experimental circuits. Performing tests on CPU and MOSTIME, we find that more advanced accelerations on large-scale fine-grain parallel circuit simulation would rely on time-saving software techniques and GPU (Graphic Processing Unit) cards. A newly implemented time-saving technique for MOSTIME has been tested to show promising effects.

Hierarchical Linking-Domain Extraction Decomposition Method for Fast and Parallel Power System Electromagnetic Transient Simulation

The linking-domain extraction (LDE) decomposition method is a new non-overlapping domain decomposition method for parallel circuit simulation. However, the original LDE method is inefficient in both the computational procedure and storage cost. In this work, a novel hierarchical LDE (H-LDE) method is proposed to further improve the LDE method, which leverages all the hidden features of LDE that are not exploited in the original work to perform a multi-level decomposition of power systems. The LDE-based matrix equation solution computation procedure is first proposed to eliminate the necessity of computing the entire matrix inversion, and then the multi-level computation structure is proposed for fast matrix inversion of the decomposed sub-matrices. The mathematical complexity of the H-LDE method is analyzed, which is used to derive the two principles for decomposing a power system. These principles can be applied on both parallel and sequential compute architecture. The 4-level LDE decomposition is applied on the IEEE 118-bus test power system and implemented in both sequential and parallel, which is used to verify the validity and efficiency of the proposed H-LDE decomposition method. The simulation results of various benchmark test power systems show that the proposed H-LDE method can achieve better performance than the classical LU factorization and sparse KLU method within a certain system scale.

回路分割法によるパワーエレクトロニクス回路の並列化シミュレーション

This paper proposes a fast parallel circuit simulation method for a power electric system by applying an explicit integration formula to selected energy storage elements such as inductors and capacitors. The forward Euler (FE) formula is applied to selected series inductors and parallel capacitors. Then an implicit formula such as the backward Euler (BE) formula is applied for stable numerical integration, and the optimum step size is selected for each subcircuit. A parallel processing method that utilizes thread processing techniques based on OpenMP application program interfaces with a multicore CPU and shared-memory system reduces its processing time. A new general algorithm based on a thread processing technique, a subcircuit memory processing technique, and a binary variable step size method is described to utilize numerical processing at each time step synchronously and efficiently. Then a new automatic partitioning method of a system into subcircuits is described. This paper also proposes how to process a PE system with a DSP-based digital control principle. The proposed method is applied to power electronic systems. It is investigated how the proposed method works and shown for effectiveness of parallel simulation by the circuit partitioning.

Addressing Partitioning Issues in Parallel Circuit Simulation

With the rapidly increasing demands for high-speed and high-density electronic products, complexity and size of the associated circuits have increased significantly in the recent years. The large size of these circuits poses major challenges for simulation in terms of excessive CPU cost. To address this, a parallel circuit simulation algorithm has been recently developed that allows modern multicore processors to be exploited to realize higher parallel scalability with an increasing number of CPUs. In this paper, several methods have been proposed to improve efficiency and flexibility during the partitioning of analog circuits. The proposed methods reduce the constraints for partitioning, allowing a more efficient set of partitions to be found, which improves scalability when used in a parallel implementation.

Parallel Circuit Simulation by Using Simulation-on-Demand and Iterated Timing Analysis

This paper considers utilizing the popular ITA (Iterated Timing Analysis) algorithm in CSM (Combining Simulation Method) to do parallel large-scale circuit simulation. An automatic partitioning method for jobs of CSM is presented, in which the related load balancing issue is also discussed. All proposed methods have been implemented and tested. Experimental results justify pleasing effects of proposed methods.

Optimizing Techniques for Parallel Digital Logic Simulation

A major part of the design process for Integrated Circuits (IC) is the process of circuit verification, in which the correctness of a circuit's design is evaluated. Discrete event simulation is a central tool in this effort. As proscribed by Moore's law, the number of transistors which can be placed on an IC doubles every 18 months. As a result, simulation has become the major bottleneck in the circuit design process. To alleviate this difficulty, it is possible to make use of parallel (or distributed) circuit simulation. In this paper, we make use of a parallel gate-level simulator which we developed and which is based upon Time Warp. Gate-level simulations exhibit two characteristics which can easily result in either instability or severely degraded simulation performance. Because of the low computational granularity of a gate-level simulation and because the computational load varies throughout the course of the simulation, the performance of Time Warp can be either severely degraded or be unstable. Restraining the optimism of Time Warp via a bounded window and utilizing dynamic load balancing are approaches to deal with these difficulties. In this paper, we make use of learning techniques from artificial intelligence (multiagent Q-learning, simulated annealing) to develop a combined bounded window and dynamic load balancing algorithm for parallel digital logic simulation. We evaluated the performance of these algorithms on open source Sparc and Leon designs and on two Viterbi decoder designs. We observed up to 60 percent improvement in simulation time of one of the decoders using this approach.

Parallel circuit simulation with adaptively controlled projective integration

In this article, a parallel transient circuit simulation approach based on an adaptively-controlled time-stepping scheme is proposed. Different from the widely-used implicit numerical integration techniques in most transient simulators, this work exploits the recently-developed explicit telescopic projective numerical integration method for efficient parallel circuit simulation. Because telescopic projective integration addresses the well-known stability issue of explicit numerical integrations by adopting combinations of inner integrators and outer integrators in a multilevel fashion, the simulation time-step is no longer limited by the smallest time constant in the circuit. With dynamic control of telescopic projective integration, the proposed projective integration framework not only leads to noticeable efficiency improvement in circuit simulation, it also lends itself to straightforward parallelization due to its explicit nature. The latter has led to encouraging runtime efficiencies, observed on shared-memory parallel platforms. In addition to solving standard initial-value problems (IVPs) of differential equations, the same telescopic integration framework is adopted for solving final-value problems (FVPs), where the system is integrated backwards in time. Through a new elegant formulation, we show how an IVP and FVP can be simultaneously solved to allow for a coarse-grained bidirectional parallel circuit simulation scheme. Such a bidirectional approach is demonstrated in the context of parallel shooting-Newton-based steady-state circuit analysis. The proposed bidirectional approach has unique and favorable properties: the solutions of the two ODE problems are completely data-independent with built-in automatic load balancing.

An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation

The sparse matrix solver has become the bottleneck in a Simulation Program with Integrated Circuit Emphasis circuit simulator. It is difficult to parallelize the sparse matrix solver because of the high data dependence during the numerical LU factorization. In this brief, a parallel LU factorization algorithm is developed on shared-memory computers with multicore central processing units, based on KLU algorithms. An Elimination Scheduler (EScheduler) is proposed to represent the data dependence during the LU factorization. Based on the EScheduler, the parallel tasks are scheduled in two modes to achieve a high level of concurrence, i.e., cluster mode and pipeline mode . The experimental results on 26 circuit matrices reveal that the developed algorithm can achieve speedup of 1.18-4.55t (on geometric average), as compared with KLU, with 1-8 threads. The result analysis indicates that for different data dependence, different parallel strategies should be dynamically selected to obtain optimal performance.

Hierarchical Multialgorithm Parallel Circuit Simulation

The emergence of multicore and many-core processors has introduced new opportunities and challenges to electronic design automation research and development. While the availability of increasing parallel computing power holds new promise to address many challenges in computer-aided design (CAD), the leverage of hardware parallelism can only be possible with a new generation of parallel CAD applications. In this paper, we propose a novel hierarchical multialgorithm (MA) parallel circuit simulation approach and its multicore implementation to expedite one of the most fundamental CAD applications: transistor-level transient circuit simulation. In our parallel circuit simulation approach, we create two levels of parallelism. At the higher level of parallelism, we start multiple simulation algorithms in parallel for a given simulation task. Interalgorithm communication is established to enable simulation algorithms to exchange useful information so that they could advance faster than without doing so. At the lower level of parallelism, each algorithm within the MA framework utilizes fine-grained parallel techniques such as parallel device evaluation and parallel matrix solve to fully harness the available hardware resources. By combining the two levels of parallelism, the computing power of the multicore or many-core processor platforms can be fully utilized to achieve superlinear speedup in circuit simulation.

What is parallel circuit simulation?

Transistor-level circuit simulation, i.e. SPICE simulation [1], is a fundamental tool for design and verification of a wide range of integrated circuits such as memories, custom digital ICs, analog, mixed-signal and RF circuits as well as digital cell library characterization. It is common for today's designers to spend days, weeks or even months of CPU time to perform expensive transistor-level circuit analysis. The simulation bottleneck significantly limits pre-silicon verification and design space exploration, contributing to long design turnaround time, suboptimal designs and even chip failures. With the advent of more complex device models and increased design complexity, high-capacity circuit simulation is strongly desirable in order to boost design productivity.

What is parallel circuit simulation?

Transistor-level circuit simulation, i.e. SPICE simulation [1], is a fundamental tool for design and verification of a wide range of integrated circuits such as memories, custom digital ICs, analog, mixed-signal and RF circuits as well as digital cell library characterization. It is common for today's designers to spend days, weeks or even months of CPU time to perform expensive transistor-level circuit analysis. The simulation bottleneck significantly limits pre-silicon verification and design space exploration, contributing to long design turnaround time, suboptimal designs and even chip failures. With the advent of more complex device models and increased design complexity, high-capacity circuit simulation is strongly desirable in order to boost design productivity.

A circuit representation technique for automated circuit design

We present a method of automatically generating circuit designs using evolutionary search and a set of circuit constructing primitives arranged in a linear sequence. This representation has the desirable property that virtually all sets of circuit-constructing primitives result in valid circuit graphs. While this representation excludes certain circuit topologies, it is capable of generating a rich set of them including many of the useful topologies seen in hand-designed circuits. Our system allows circuit size (number of devices), circuit topology, and device values to he evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. In all tasks, our system is able to generate circuits that achieve the target specifications. Although the evolved circuits exist as software models, detailed examinations of each suggest that they are electrically well behaved and thus suitable for physical implementation. The modest computational requirements suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation.

A multidimensional study on the feasibility of parallel switch-level circuit simulation

This paper presents the results of an experimental study to evaluate the effectiveness of multiple synchronization protocols and partitioning algorithms in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: (i) parallelizing an existing switch-level simulator such that the model can be executed using conservative and optimistic simulation protocols with minor changes, (ii) evaluating effectiveness of several partitioning algorithms for parallel simulation, and (iii) demonstrating speedups with both conservative and optimistic simulation protocols for seven circuits, ranging in size from 3K transistors to about 87K transistors.

Parallel gate-level circuit simulation on shared memory architectures

This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-level parallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuit simulation have failed to extract speedups with conservative protocols); in particular we showed that a speedup of about 3 was obtained on 8 processors of Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite; and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.

Improving the performance of parallel relaxation-based circuit simulators

Describes methods of increasing parallelism, thereby improving the performance, of waveform relaxation-based parallel circuit simulators. The key contribution is the use of parallel nonlinear relaxation and parallel model evaluation to solve large subcircuits that may lead to load balancing problems. These large subcircuits are further partitioned and solved on clusters of tightly-coupled multiprocessors. This paper describes a general hybrid/hierarchical approach for waveform relaxation, and then focuses on the implementation issues regarding parallel nonlinear relaxation and parallel model evaluation. A number of benchmark circuits are used to demonstrate the improved performance of this approach and its range of applicability in parallel circuit simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parallel circuit simulation on supercomputers

Circuit simulation is a very time-consuming and numerically intensive application, especially when the problem size is large as in the case of VLSI circuits. To improve the performance of circuit simulators without sacrificing accuracy, a variety of parallel processing algorithms have been investigated. Research in the field of parallel circuit simulation is surveyed, and the ongoing research in this area at the University of Illinois is described. Both standard and relaxation-based approaches are considered. In particular, the forms of parallelism available within the direct method approach, used in programs such as SPICE2 and SLATE, and within the relaxation-based approaches, such as waveform relaxation, iterated timing analysis, and waveform-relaxation-Newton, are described. The specific implementation issues addressed are primarily related to general-purpose multiprocessors with a shared-memory architecture having a limited number of processors, although many of the comments apply to a number of other architectures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>