Parallel Bus Research Articles

Remotely Powered Two-Wire Cooperative Sensors for Bioimpedance Imaging Wearables.

Bioimpedance imaging aims to generate a 3D map of the resistivity and permittivity of biological tissue from multiple impedance channels measured with electrodes applied to the skin. When the electrodes are distributed around the body (for example, by delineating a cross section of the chest or a limb), bioimpedance imaging is called electrical impedance tomography (EIT) and results in functional 2D images. Conventional EIT systems rely on individually cabling each electrode to master electronics in a star configuration. This approach works well for rack-mounted equipment; however, the bulkiness of the cabling is unsuitable for a wearable system. Previously presented cooperative sensors solve this cabling problem using active (dry) electrodes connected via a two-wire parallel bus. The bus can be implemented with two unshielded wires or even two conductive textile layers, thus replacing the cumbersome wiring of the conventional star arrangement. Prior research demonstrated cooperative sensors for measuring bioimpedances, successfully realizing a measurement reference signal, sensor synchronization, and data transfer though still relying on individual batteries to power the sensors. Subsequent research using cooperative sensors for biopotential measurements proposed a method to remove batteries from the sensors and have the central unit supply power over the two-wire bus. Building from our previous research, this paper presents the application of this method to the measurement of bioimpedances. Two different approaches are discussed, one using discrete, commercially available components, and the other with an application-specific integrated circuit (ASIC). The initial experimental results reveal that both approaches are feasible, but the ASIC approach offers advantages for medical safety, as well as lower power consumption and a smaller size.

Suppression of Simultaneous Switching Noise Using Embedded Capacitor Method in High-Speed Systems

Gbps signals are commonly used in modern high-speed IO designs. These systems require a high level of signal accuracy. However, these signals can cause current fluctuations at high frequencies due to parasitic inductance on the package and board, leading to significant changes in supply voltage. DDRX interfaces that transmit data up to 4.8 Gbps induce simultaneous switching noise (SSN) in the voltage regulator module (VRM). One of the adverse effects of SSN is timing jitter, also known as power supply-induced jitter. The amount of SSN is directly proportional to the number of signals on a parallel bus. Discrete capacitors may not be effective in reducing SSN impact when data is transmitted at high speeds. The current approach used to predict and evaluate errors in SSNs relies on the designer's expertise, which requires accurate estimates of packaging parasitic. In this paper, a practical approach to lessen SSN is presented through the use of embedded capacitors placed between planes and optimizing discrete capacitors by connecting them in a way that measures the impact of supply noise on the I/O transistor circuit performance at the DDRX interface. Two boards were designed, evaluated, and subsequently compared their results.

Package Board Co-Simulation Using Equivalent Circuit Modeling Method for High-Speed System

This research paper focuses on the challenges of system-level simulations for high-speed data transfer and the importance of modeling methodology in achieving accurate results. The simulating of PCB alone without considering the package model is not enough. Instead, to ensure optimal system performance, simulating the packages and PCBs together is essential. When simulating the high-speed parallel bus at the PCB level, it's crucial to consider the package model. If the package model is missing, achieving successful results can be challenging. In this paper, a method is proposed for developing a package model that is specific to the nets required for simulation purposes. The paper explores the challenge of simulating high-speed interfaces with a DDRx example that includes an RLC package model. An interconnect model technique is developed to apply the package RLC model through the equivalent circuit modeling method for the high-speed DDRx test board. This solution aims to simplify the co-design process by using simulation and verifying the model with the assistance of an eye diagram of the data bus. The proposed package model reduces jitter in co-simulation and ensures timing compliance for high-speed interfaces.

An Adaptive ECMS Based on Traffic Information for Plug-in Hybrid Electric Buses

Nowadays, a growing interest is in improving the efficiency of a parallel hybrid electric bus (PHEB). This paper proposes an adaptive energy management strategy based on an equivalent consumption minimization strategy (ECMS) by using real-time traffic information described by the average speed, average acceleration, and standard deviation of speed for different road sections. The whole adaptive energy management system consists of offline and online components. Three velocity characteristic parameters are derived by utilizing the data from the vehicle. Firstly, the road segments are classified through the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -means. Then three Markov transition matrices on different types of roads are constructed with the velocity feature parameters which can be used to predict the speed in the following time. On the other hand, the online component implements the energy management strategy (EMS) involved. The EMS incorporates predicted vehicle speed and road information into the ECMS. Based on this, the predicted vehicle speed and traffic information are applied to make adaptive changes to the equivalent factors in the ECMS. Finally, the performance of the proposed strategy is evaluated through a comparative simulation study and the results show the superiority of the approach in improving fuel economy. Comparative outcomes from HIL tests additionally illustrate that the proposed strategy's fuel efficiency is compatible with the original design intent.

Modelling Method on Dynamic Optimal Setting and Associated Control for Intermittent Bus Lane

A new type of dynamic bus lane not only ensures the strategy of bus priority but also significantly improves the spatiotemporal utilization of road resources and reduces the conflicting demands of buses and social vehicles on road resources. Firstly, the heterogeneity of bus arrival time is analysed according to the process of aggregation and dissipation of vehicle queues at intersections. Considering the correlation between the operating states of social vehicles and buses, a dynamic control strategy for bus lane based on the insertable interval of social vehicles is established. Secondly, combining the setting conditions of the intermittent bus lane control area with the correlation scenario of signal control at intersections and then according to the HCM 2010 vehicle delay equation and the BPR function, the associated optimized control model with the minimum total travel time consumption of the road section as the objective function is constructed. The global optimal control of the intermittent bus lane is realized through the computational experiment. Finally, the setting conditions and benefits of three lane organization schemes (including intersect (i.e., no bus priority), parallel, and intermittent bus lanes) are compared and analysed through case study. The results indicate that the intermittent priority bus lanes have opening hours, which can not only ensure bus priority but also expand the right way for social vehicles and make full use of road space resources, thus improving the overall traffic efficiency.

NeuSB: A Scalable Interconnect Architecture for Spiking Neuromorphic Hardware

Neuromorphic systems are typically designed as a tile-based architecture where inter-tile data communication is facilitated using a shared global interconnect. Congestion on this interconnect can increase both interconnect energy, which increases the total energy consumption of the hardware and latency, which impacts the performance e.g., accuracy of the application that is being executed on the hardware. Mesh-based Network-on-Chip (NoC) that is used in most hardware prototypes is not the optimal interconnect solution for neuromorphic systems. This is because of the following two reasons. First, power consumption and average latency of a NoC increases exponentially with the number of tiles in the hardware. Second, a NoC cannot exploit an application’s data communication pattern efficiently. Once designed for a target hardware, the bandwidth on each NoC link stays the same, independent of the volume of data traffic between different tile pairs of the NoC. In other words, a NoC cannot be customized at a finer granularity based on an individual application running on the hardware. We show that these NoC limitations prevent opportunities to further improve energy and latency of a neuromorphic hardware. To address these limitations, we propose Dynamic Segmented Bus (SB) interconnect for neuromorphic systems. Here, a bus lane is partitioned into segments with each segment connecting a few tiles. Connection of tiles to segments and those between segments are bridged using our novel three-way segmentation switches that are programmed using the software before admitting an application to the hardware. We partition an application by analyzing its workload and place partitions intelligently onto segments. This exploits application characteristics to use the segments without any routing collisions while exploiting the latency and energy savings in the design-time mapping phase. At a high-level, our mapping algorithm places tiles that communicate the most on shorter segments utilizing fewer number of switches, thereby reducing network congestion. It can adjust the bandwidth by controlling the number of segments connected to a destination tile. At run time, our controller dynamically executes the predefined routing paths without requiring any additionally routing decisions, unlike a NoC. This allows us to improve both energy and latency. Using parallel segmented busses, our proposed interconnect architecture can support a large number of tiles without significantly increasing the design cost, energy, and latency. Simulation results show that compared to the most widely-used mesh-based NoC design, our interconnect architecture, which we call NeuSB, reduces the switch area by 20x, average interconnect energy by 6.2x, and latency by 23%.

Powertrain Parameters’ Optimization for a Series–Parallel Plug-In Hybrid Electric Bus by Using a Combinatorial Optimization Algorithm

Whether the powertrain parameters are reasonable will directly affect the fuel economy of a plug-in hybrid electric bus (PHEB). In this article, the fuel economy is chosen as the optimization target of a serial–parallel PHEB. A global optimal strategy, which is formulated by dynamic programming (DP) algorithm, is used as an energy management strategy for PHEB. First, PHEB fuel economy is chosen as the optimization objective. Then, a combinatorial optimization algorithm is designed by combining a multi-island genetic algorithm (MIGA) with non-linear programming by quadratic lagrangian (NLPQL). MIGA is used for global optimization, and the NLPQL is used for a local optimization to make up for the poor ability of MIGA in local optimization. Finally, several hardware-in-the-loop (HIL) experiments were carried out, and the results prove that the fuel consumption per 100 km has reduced from 25.7- to 22.9-l diesel, and the electricity consumption per 100 km has reduced from 14.7 to 14.3 kW <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot \text{h}$ </tex-math></inline-formula> .

Optimal Allocation of BESS to Maximize Efficiency Under Constrained SOC in Parallel Inverter-Based Scaled-Up Slack Bus

The parallel inverter-based scaled-up slack bus includes multiple battery energy storage systems (BESSs) to support the slack operation without short of real power. The multiple BESSs require a well-designed state of the charge (SOC) balancing algorithm for maximally effective usage. Until now, however, the SOC balancing algorithms only focus on strong SOC balancing without careful consideration of BESS efficiency during its charging and discharging. This paper proposes a soft SOC balancing algorithm based on the Levenberg-Marquardt (L-M) algorithm considering BESS’s charging and discharging efficiency. The charges or discharges of the BESSs are primarily determined by their efficiencies that indirectly reflect the SOCs. As a result, the proposed method provides some margins to improve efficiency rather than tightly focusing on only the SOCs balancing between multiple BESSs (e.g., two BESSs with 0.7 and 0.4 pu of SOCs discharge rather than only one BESS with large SOC discharges when total output is 0.86 pus). The optimizations and balancing are conducted by MATLAB software. Their related converter interactions are simulated using a power system computer-aided design/electromagnetic transient including DC (PSCAD/EMTDC <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\mathrm {TM}}$ </tex-math></inline-formula> ), to measure data for optimization.

Remotely Powered Two-Wire Cooperative Sensors for Biopotential Imaging Wearables.

Biopotential imaging (e.g., ECGi, EEGi, EMGi) processes multiple potential signals, each requiring an electrode applied to the body's skin. Conventional approaches based on individual wiring of each electrode are not suitable for wearable systems. Cooperative sensors solve the wiring problem since they consist of active (dry) electrodes connected by a two-wire parallel bus that can be implemented, for example, as a textile spacer with both sides made conductive. As a result, the cumbersome wiring of the classical star arrangement is replaced by a seamless solution. Previous work has shown that potential reference, current return, synchronization, and data transfer functions can all be implemented on a two-wire parallel bus while keeping the noise of the measured biopotentials within the limits specified by medical standards. We present the addition of the power supply function to the two-wire bus. Two approaches are discussed. One of them has been implemented with commercially available components and the other with an ASIC. Initial experimental results show that both approaches are feasible, but the ASIC approach better addresses medical safety concerns and offers other advantages, such as lower power consumption, more sensors on the two-wire bus, and smaller size.

Energy-Efficient Encoding for High-Speed Serial Interfaces

Energy consumption has become a bottleneck in modern integrated circuits (ICs) with a significant part of the energy spent on data communication. High-speed, serial interfaces are widely used, offering important advantages over parallel buses. The energy demand of source synchronous, serial buses can be effectively decreased by employing encoding techniques that reduce the bit transitions of the transmitted data stream. However, these techniques are not applicable for asynchronous interfaces, such as Peripheral Component Interconnect Express (PCIe), where frequent bit transitions are required to recover the clock at the receiver to maintain link integrity. Recognizing this fundamental trait, an encoding technique named serial tuned transition encoding (STTE) is proposed that regulates the number of transitions such that the clock can be reliably recovered, while the communication energy is lowered. The proposed scheme provides at least 25% decrease in energy for a short interposer-based interconnect compared to scrambling, which is typically used in serializer/deserializer (SerDes) devices. The link integrity is experimentally evaluated using both an electrical and an optical link that interconnect two field-programmable gate array (FPGA) devices. Results demonstrate that STTE successfully preserves link integrity as no errors are induced during transmission. In addition, STTE adjusts the number of transitions, thus allowing energy reduction and link integrity to be traded off.

Cryptography-Based Medical Signal Securing Using Improved Variation Mode Decomposition with Machine Learning Techniques.

There is no question about the value that digital signal processing brings to the area of biomedical research. DSP processors are used to sample and process the analog inputs that are received from a human organ. These inputs come from the organ itself. DSP processors, because of their multidimensional data processing nature, are the electrical components that take up the greatest space and use the most power. In this age of digital technology and electronic gizmos, portable biomedical devices represent an essential step forward in technological advancement. Electrocardiogram (ECG) units are among the most common types of biomedical equipment, and their functions are absolutely necessary to the process of saving human life. In the latter part of the 1990s, portable electrocardiogram (ECG) devices began to appear on the market, and research into their signal processing and electronics design capabilities continues today. System-on-chip (SoC) design refers to the process through which the separate computing components of a DSP unit are combined onto a single chip in order to achieve greater power and space efficiency. In the design of biomedical DSP devices, this body of research presents a number of different solutions for reducing power consumption and space requirements. Using serial or parallel data buses, which are often the region that consumes the most power, it is possible to send data between the system-on-chip (SoC) and other components. To cut down on the number of needless switching operations that take place during data transmission, a hybrid solution that makes use of the shift invert bus encoding scheme has been developed. Using a phase-encoded shift invert bus encoding approach, which embeds the two-bit indication lines into a single-bit encoded line, is one way to solve the issue of having two distinct indicator bits. This method reduces the problem. The PESHINV approach is compared to the SHINV method that already exists, and the comparison reveals that the suggested PESHINV method reduces the total power consumption of the encoding circuit by around 30 percent. The computing unit of the DSP processor is the target of further optimization efforts. Virtually, all signal processing methods need memory and multiplier circuits to function properly.

A mathematical model for vibration analysis of a parallel hybrid electric bus powertrain

This paper presents a parallel hybrid electric bus equipped with an automated manual transmission (AMT) and a mathematical model of the hybrid powertrain is developed for vibration analysis. The powertrain dynamic model is established by a modular modelling approach. A detailed AMT dynamic model, considering gear time-varying meshing stiffness, shaft elastic deformation, and bearing elastic support, is incorporated into the powertrain dynamic model. The damping and gyroscopic effect of gear-rotor in the AMT are considered as well. The AMT dynamic model is validated by experiment data from the time and frequency domain comparisons. Finally, the parameter analysis of the dual-mass flywheel (DMF) is utilised to illustrate how to use the proposed powertrain dynamic model for vibration reduction. The influence of the DMF parameters on vibration responses of the system with varying engine rotation speed is investigated. This study provides a basis for further vibration control of the hybrid powertrain during the engine driving mode.

A mathematical model for vibration analysis of a parallel hybrid electric bus powertrain

A mathematical model for vibration analysis of a parallel hybrid electric bus powertrain

System modeling and fault studies in data center power distribution

ABB&apos;s isolated parallel ring bus (IPRB) architecture with static uninterruptible power supplies (UPS) provides a solution with excellent scalability, power sharing, and fault handling capability. Critical components in a data center power distribution system are modeled for system simulations. In the modeling approach, a balance is struck between computation speed and fidelity such that useful system simulation results can be obtained for use in planning, design, and protection. The UPS model includes low short circuit current fault modes. The dual-corded load (DCL), used widely in data centers is modeled with DC link control. Transformers and chokes are modeled with saturation characteristics. Various fault scenarios have been analysed and presented. Verified system simulations in the SIMULINK modeling environment are used for fault studies to obtain protection design requirements. It is shown that system simulations with the appropriate fidelity are very useful to explore system issues and protection. Modeling the components&apos; fault mode behaviour is critical to obtain useful results.

Research Analysis of PCB Design’s Influence on DDR4 Highspeed Signal Integrity

With the increase of the signal transmission rate of electronic devices and the increase of the PCB wiring density, PCB design has a growing influence on signal integrity. To reduce the number of the problems concerning signal integrity at the initial stage of electronic product design and increase the success rate of the designing of electronic products, some interference signals of PCB are canceled to improve the accuracy of signal integrity test, with the high-speed parallel bus of DDR4 as an example. Analysis is done through measurement of various simulation tools to change the PCB design parameters of DDR4 data transmission line, hence the optimum wiring method will influence the signal quality. Meanwhile, RC parallel impedance matching optimization is carried out to deal with the impedance mismatch at the network load end. In this way, the problem concerning DDR4 high-speed signal integrity is effectively solved.

The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

In this work, a bus encoding method is proposed that reduces the effect of crosstalk. The crosstalk usually occurs when the data is in parallel communicated. In planar structures, the crosstalk effect is large due to the usage of parallel communication and wide data patterns. In bus technique, the huge amount of wires is laid in equal over a significant time. One way to reduce crosstalk without changing the parallel communicating data lines is to reduce the wideband data patterns so as to reduce the power utilization. The proposed encoding method can minimize the crosstalk by reducing wide data patterns without degrading the performance. The architecture is implemented on Artix 7 FPGA at a 28nm technology node. The simulation is done using the HDL tool and the results are compared with the existing FPGA architecture. With the proposed method, the wire density and the power consumption are reduced by 57.4% and 50% respectively as compared with existing 45 nm technologies.

Analytical, Logit Model-based Examination of the Hungarian Regional Parallel Public Transport System

The ongoing competition between bus and railway systems in the Hungarian regional passenger transport is a current problem, because these subsectors need to complement each other, instead of being in the government-funded competition. Long-term sustainability and efficiency in passenger transport require a balanced transport policy. The parallel bus and railway links, which are present in all regions of Hungary can result in competition. This research explores the solutions to this issue for long-term environmental and economic sustainability optimization. An objective index and interventions developed in previous studies have been applied here. This investigation is to validate the objective index and the interventions by using the Logit model.

Sustainability Analysis of Competition in Public Transport Systems: A Comparative Case Study in Hungary and Finland

Ongoing competition between bus and railway systems in European (especially in the middle, south and east part) regional passenger transport is a current problem. Long term sustainability and efficiency in passenger transport requires a balanced transport policy. These subsectors need to be complement each other, not compete. The parallel bus and railway links can result in a competition. This research explores solutions to this issue for long term environmental and economic sustainability optimization. Some of the important factors include the number of inhabitants to be served, public transport availability, and efficiency in time of travel for vehicles and passengers. To ensure long term sustainability of the presented methodology, the effect of interventions was analyzed. The study compares Finland and Hungary in terms of the competition regional railway and bus links.

Demonstration of a Push-Pull Silicon Dual-Ring Modulator With Enhanced Optical Modulation Amplitude

In this article, we demonstrate a push-pull silicon dual-ring modulator based on two cascaded rings which are coupled with each other through two parallel bus waveguides. In the transmission spectrum of the modulator, a narrow transparency peak exists in the center of the broad dip based on the electromagnetically induced transparency (EIT)-like effect. Benefiting from both the EIT-like effect and push-pull drive configuration, a low insertion loss (IL) of 1.4 dB and an extinction ratio (ER) over 6.4 dB are obtained at a bit rate of 10 Gb/s with a peak-to-peak driving voltage (Vpp) of 5 V. The corresponding maximum optical modulation amplitude (OMA) is 0.56, which is almost twice that of a single micro-ring modulator with the same driving voltage. Moreover, the maximum OMA is 0.47 at 20 Gb/s, which is 81% larger than that of a single micro-ring modulator.

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