Parallel Bit Research Articles

Heterodyne Random Bit Generation Using an Optically Injected Semiconductor Laser in Chaos

Heterodyne generation of parallel random bit streams from chaotic emission of an optically injected semiconductor laser is investigated. The continuous-wave optical injection invokes chaotic dynamics in the laser. The broadband chaotic emission is detected through optical heterodyning and electrical heterodyning into different channels. The channels digitize the signals into parallel independent random bit streams. Because of efficient utilization of different portions of the chaos bandwidth, heterodyne detections enable parallel generation of random bit streams, offer high total output bit rates, and require no high-bandwidth analogue-to-digital converters. In the experiment, two optical heterodyne channels and four electrical heterodyne channels are implemented. Each channel is required to digitize only 2.5 GHz of a much broader chaos bandwidth. The sampling rate is 10 GHz with five least significant bits selected from every 8-bit sample. The total output bit rate reaches 100 Gb/s and 200 Gb/s for optical and electrical heterodyning, respectively. The standard test suite of the National Institute of Standards and Technology verifies the randomness of both individual and interleaved output bit streams.

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface

This brief presents an 8-bit parallel transceiver for low-power memory interface with a current-regulated voltage-mode driver and a clock and data recovery performing both bit recovery and byte alignment. Sharing a current source by output drivers enables voltage swing control without any regulator circuit while holding the benefits of low-power voltage-mode driving. In the receiver, with only one phase rotator in a globally shared phase-locked loop, a narrow-range delay line in each deskewing phase recovery loop effectively performs seamless phase adjustment. The transceiver, implemented in a 90-nm CMOS, shows a data rate of 6 Gbit/s/ch with a bit error rate of $10^{-12}$ and a power consumption of 2.8 mW/Gbit/s.

Development of a pulse programmer for magnetic resonance imaging using a personal computer and a high-speed digital input–output board

We have developed a pulse programmer for magnetic resonance imaging (MRI) using a personal computer and a commercially available high-speed digital input-output board. The software for the pulse programmer was developed using C∕C++ and .NET Framework 2.0 running under the Windows 7 operating system. The pulse programmer was connected to a digital MRI transceiver using a 32-bit parallel interface, and 128-bit data (16 bits × 8 words) for the pulse sequence and the digitally detected MRI signal were transferred bi-directionally every 1 μs. The performance of the pulse programmer was evaluated using a 1.0 T permanent magnet MRI system. The acquired MR images demonstrated the usefulness of the pulse programmer. Although our pulse programmer was developed for a specially designed digital MRI transceiver, our approach can be used for any MRI system if the interface for the transceiver is properly designed. Therefore, we have concluded that our approach is promising for MRI pulse programmers.

A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-<TEX>${\mu}m$</TEX> 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 <TEX>$mm^2$</TEX> and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

Implementation of 10-Gb/s Parallel BCH Decoder Based on Virtex-5 FPGA

This paper presents a design of 10Gb/s BCH decoder which is compatible with the protocol of G.975 and can be applied in optical fiber communication. The main blocks of this decoder include syndrome calculator, key-equation solver, Chien search and error correction. In order to achieve high speed, 8-bit parallel syndrome calculator and Chien search block are adopted. By sharing the key-equation solver, the numb er of key-equation solver is reduced and the hardware resources are saved. This decoder has been implemented in Virtex-5 FPGA and the verification results show that the decoder can work properly under the clock of 166MHz and the data rate can be up to 10Gb/s.

基于Linux下的OLED显示模块设计

The characteristics of main display devices in the current market is analyzed.And this paper chooses the OLED display module,based on the general requirements of the S3C2440-based-system and the advantages and disadvantages of the display devices above.By analyzing the structure of S3C2440,this work uses SPI bus interface to solve the problem that the 8-bit parallel interface take too many I/O pins.Through the design of the hardware and software,the design meets the demand of the system saving interfaces,and achieving the OLED screen display module application on the condition.

A new high performance PBV-based approach for simultaneous packet classification and conflict detection

In this paper, the searching speed of one of the algorithms for packet classification – the parallel bit vector algorithm – is increased. This is done by pre-computing the lookup step of the algorithm. Then by applying cache memory techniques, the required memory of the proposed approach is reduced. The result of internet traffic modelling analysis shows that the proposed algorithm has good performance in edge routers where the locality reference principal dominates. Our algorithm could be used for conflict detection as well at cost of reduction in performance.

Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects

The authors present a performance boosting technique with a better power efficiency for delay-insensitive on-chip interconnects. The increase in signal propagation delay uncertainty with technology scaling makes self-timed delay-insensitive on-chip interconnects the most appropriate alternative. However, achieving high-performance communication in self-timed delay-insensitive links is difficult, especially for large bit parallel transmission because of the time-consuming detection of each bit validity. The authors present a high-speed completion detection technique along with its circuit implementation and two on-chip interconnects which use the proposed completion detection circuit. The performance, power consumption, power efficiency and area of the presented on-chip interconnects are analysed and compared with the conventionally implemented delay-insensitive interconnects. For 64-bit parallel transmission, 2.07 and 1.72 times throughput improvement with 47 and 39% more power efficiency have been achieved for the two interconnects compared to their conventional counterparts. The interconnect circuits are designed and simulated using Cadence Analog Spectre and Hspice with 65 nm complementary metal–oxide semiconductor technology from STMicroelectronics.

Design and Implementation of a Latency Efficient Encoder for LTE Systems

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

On Trapping Sets and Guaranteed Error Correction Capability of LDPC Codes and GLDPC Codes

The relation between the girth and the guaranteed error correction capability of $\gamma$-left regular LDPC codes when decoded using the bit flipping (serial and parallel) algorithms is investigated. A lower bound on the size of variable node sets which expand by a factor of at least $3 \gamma/4$ is found based on the Moore bound. An upper bound on the guaranteed error correction capability is established by studying the sizes of smallest possible trapping sets. The results are extended to generalized LDPC codes. It is shown that generalized LDPC codes can correct a linear fraction of errors under the parallel bit flipping algorithm when the underlying Tanner graph is a good expander. It is also shown that the bound cannot be improved when $\gamma$ is even by studying a class of trapping sets. A lower bound on the size of variable node sets which have the required expansion is established.

Hybrid decoding of finite geometry low-density parity-check codes

For finite geometry low-density parity-check codes, heavy row and column weights in their parity check matrix make the decoding with even min–Sum (MS) variants computationally expensive. To alleviate it, the authors present a class of hybrid schemes by concatenating a parallel bit flipping (BF) variant with an MS variant. Meanwhile, the BF variant, with much less computational complexity, attempts decoding the receive sequence firstly, and only decoding failure of the BF variant triggers the MS variant. Hence the BF variant performance heavily impacts the overall hybrid scheme, which is illustrated in two case studies. Computational and hardware complexity is then elaborated to justify the feasibility of the hybrid schemes. In most SNR region of interest, without compromising performance or convergence rate, the proposed hybrid schemes can save substantial computational complexity when compared with the MS variant decoding alone.

The Synthesis of Stochastic Circuits for Nanoscale Computation

Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively.

Architectural support for SWAR text processing with parallel bit streams

Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF-8 to UTF-16 transcoding, XML parsing, string search and regular expression matching. Direct architectural support for these algorithms in future SWAR instruction sets could further increase performance as well as simplifying the programming task. A set of simple SWAR instruction set extensions are proposed for this purpose based on the principle of systematic support for inductive doubling as an algorithmic technique. These extensions are shown to significantly reduce instruction count in core parallel bit stream algorithms, often providing a 3X or better improvement. The extensions are also shown to be useful for SWAR programming in other application areas, including providing a systematic treatment for horizontal operations. An implementation model for these extensions involves relatively simple circuitry added to the operand fetch components in a pipelined processor.

Architectural support for SWAR text processing with parallel bit streams

Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF-8 to UTF-16 transcoding, XML parsing, string search and regular expression matching. Direct architectural support for these algorithms in future SWAR instruction sets could further increase performance as well as simplifying the programming task. A set of simple SWAR instruction set extensions are proposed for this purpose based on the principle of systematic support for inductive doubling as an algorithmic technique. These extensions are shown to significantly reduce instruction count in core parallel bit stream algorithms, often providing a 3X or better improvement. The extensions are also shown to be useful for SWAR programming in other application areas, including providing a systematic treatment for horizontal operations. An implementation model for these extensions involves relatively simple circuitry added to the operand fetch components in a pipelined processor.

Transition faults detection in bit parallel multipliers over GF(2 m )

In this article, a C-testable design for detecting transition faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m) is discussed. For 100 percent transition fault coverage, the proposed technique requires only 10 vectors, irrespective of multiplier size, at the cost of 6 percent extra hardware. The proposed constant test vectors which are sufficient to detect both the transition and stuck-at faults in the multiplier circuits can be derived directly without any requirement of an ATPG tool. As the GF(2m) multipliers have found critical applications in public key cryptography and need secure internal testing, a Built-in Self-Test (BIST) circuit may be used for generating test patterns internally. This will obviate the need of having three extra pins for the control inputs and also provides public-key security in cryptography. Area and delay of the testable circuit are analyzed using Synopsys® tools with 0.18µ CMOS technology library from UMC.

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)

This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial-basis (PB) bit-parallel (BP) multiplier circuits over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of the ATPG tool. This low- complexity testing method requires (2m + 1) test vectors for detecting single stuck-at faults in the AND part and multiple stuck-at faults in the EXOR part of the multiplier circuits. The test vectors are independent of the multiplier's structure, as proposed in (T. A. Gulliver et al., 1991), but are dependent on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100 percent single stuck-at fault coverage.

High performance word level sequential and parallel coding methods and architectures for bit plane coding

This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding (BPC) in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel & pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture (PA) was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture (HA) was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an N×N code-block could be completed in approximate N 2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.

C-testable bit parallel multipliers over GF (2 m )

We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2 m ) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys® tools using UMC 0.18 micron CMOS technology library.

Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

This paper proposes an 8 × 8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8 × 8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35 μm standard CMOS process.

A 120-dB Dynamic Range CMOS Image Sensor With Programmable Power Responsivity

A high dynamic range CMOS image sensor providing a user-programmable power responsivity curve is presented. Each pixel integrates, besides a 4T active pixel structure, a voltage comparator and an analog memory to implement a time-to-saturation scheme while also providing the standard integrated photo-current signal. The sensor generates two 10-bit analog outputs allowing a typical dynamic range exceeding 120 dB with a temporal noise lower than 0.13% and a fixed pattern noise of 0.4% (1.7%) of the total signal swing (2 V) at low (high) irradiance without any external calibration procedures. A 140 times 140-pixel array has been fabricated in a 0.35-mum, two-poly four-metal (2P4M), 3.3-V standard CMOS technology. The chip measures 3.9 times 4.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a pixel pitch of 15 mum and a fill factor of 20%.